1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36#ifdef CONFIG_ENABLE_MMU 37#include <asm/proc/domain.h> 38#endif 39 40#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 41#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 42#endif 43 44/* 45 ************************************************************************* 46 * 47 * Jump vector table as in table 3.1 in [1] 48 * 49 ************************************************************************* 50 */ 51 52.globl _start 53_start: b reset 54#ifndef CONFIG_NAND_SPL 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: 64 .word undefined_instruction 65_software_interrupt: 66 .word software_interrupt 67_prefetch_abort: 68 .word prefetch_abort 69_data_abort: 70 .word data_abort 71_not_used: 72 .word not_used 73_irq: 74 .word irq 75_fiq: 76 .word fiq 77_pad: 78 .word 0x12345678 /* now 16*4=64 */ 79#else 80 . = _start + 64 81#endif 82 83.global _end_vect 84_end_vect: 85 .balignl 16,0xdeadbeef 86/* 87 ************************************************************************* 88 * 89 * Startup Code (reset vector) 90 * 91 * do important init only if we don't start from memory! 92 * setup Memory and board specific bits prior to relocation. 93 * relocate armboot to ram 94 * setup stack 95 * 96 ************************************************************************* 97 */ 98 99.globl _TEXT_BASE 100_TEXT_BASE: 101#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 102 .word CONFIG_SYS_TEXT_BASE 103#else 104#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 105 .word CONFIG_SPL_TEXT_BASE 106#else 107 .word CONFIG_SYS_TEXT_BASE 108#endif 109#endif 110 111/* 112 * Below variable is very important because we use MMU in U-Boot. 113 * Without it, we cannot run code correctly before MMU is ON. 114 * by scsuh. 115 */ 116_TEXT_PHY_BASE: 117 .word CONFIG_SYS_PHY_UBOOT_BASE 118 119/* 120 * These are defined in the board-specific linker script. 121 * Subtracting _start from them lets the linker put their 122 * relative position in the executable instead of leaving 123 * them null. 124 */ 125 126.globl _bss_start_ofs 127_bss_start_ofs: 128 .word __bss_start - _start 129 130.globl _bss_end_ofs 131_bss_end_ofs: 132 .word __bss_end - _start 133 134.globl _end_ofs 135_end_ofs: 136 .word _end - _start 137 138/* IRQ stack memory (calculated at run-time) + 8 bytes */ 139.globl IRQ_STACK_START_IN 140IRQ_STACK_START_IN: 141 .word 0x0badc0de 142 143/* 144 * the actual reset code 145 */ 146 147reset: 148 /* 149 * set the cpu to SVC32 mode 150 */ 151 mrs r0, cpsr 152 bic r0, r0, #0x3f 153 orr r0, r0, #0xd3 154 msr cpsr, r0 155 156/* 157 ************************************************************************* 158 * 159 * CPU_init_critical registers 160 * 161 * setup important registers 162 * setup memory timing 163 * 164 ************************************************************************* 165 */ 166 /* 167 * we do sys-critical inits only at reboot, 168 * not when booting from ram! 169 */ 170cpu_init_crit: 171 /* 172 * When booting from NAND - it has definitely been a reset, so, no need 173 * to flush caches and disable the MMU 174 */ 175#ifndef CONFIG_NAND_SPL 176 /* 177 * flush v4 I/D caches 178 */ 179 mov r0, #0 180 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 181 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 182 183 /* 184 * disable MMU stuff and caches 185 */ 186 mrc p15, 0, r0, c1, c0, 0 187 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 188 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 189 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 190 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 191 192 /* Prepare to disable the MMU */ 193 adr r2, mmu_disable_phys 194 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 195 b mmu_disable 196 197 .align 5 198 /* Run in a single cache-line */ 199mmu_disable: 200 mcr p15, 0, r0, c1, c0, 0 201 nop 202 nop 203 mov pc, r2 204mmu_disable_phys: 205 206#ifdef CONFIG_DISABLE_TCM 207 /* 208 * Disable the TCMs 209 */ 210 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 211 cmp r0, #0 212 beq skip_tcmdisable 213 mov r1, #0 214 mov r2, #1 215 tst r0, r2 216 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 217 tst r0, r2, LSL #16 218 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 219skip_tcmdisable: 220#endif 221#endif 222 223#ifdef CONFIG_PERIPORT_REMAP 224 /* Peri port setup */ 225 ldr r0, =CONFIG_PERIPORT_BASE 226 orr r0, r0, #CONFIG_PERIPORT_SIZE 227 mcr p15,0,r0,c15,c2,4 228#endif 229 230 /* 231 * Go setup Memory and board specific bits prior to relocation. 232 */ 233 bl lowlevel_init /* go setup pll,mux,memory */ 234 235 bl _main 236 237/*------------------------------------------------------------------------------*/ 238 239/* 240 * void relocate_code (addr_sp, gd, addr_moni) 241 * 242 * This function relocates the monitor code. 243 */ 244 .globl relocate_code 245relocate_code: 246 mov r4, r0 /* save addr_sp */ 247 mov r5, r1 /* save addr of gd */ 248 mov r6, r2 /* save addr of destination */ 249 250 adr r0, _start 251 subs r9, r6, r0 /* r9 <- relocation offset */ 252 beq relocate_done /* skip relocation */ 253 mov r1, r6 /* r1 <- scratch for copy_loop */ 254 ldr r3, _bss_start_ofs 255 add r2, r0, r3 /* r2 <- source end address */ 256 257copy_loop: 258 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 259 stmia r1!, {r10-r11} /* copy to target address [r1] */ 260 cmp r0, r2 /* until source end address [r2] */ 261 blo copy_loop 262 263#ifndef CONFIG_SPL_BUILD 264 /* 265 * fix .rel.dyn relocations 266 */ 267 ldr r0, _TEXT_BASE /* r0 <- Text base */ 268 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 269 add r10, r10, r0 /* r10 <- sym table in FLASH */ 270 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 271 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 272 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 273 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 274fixloop: 275 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 276 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 277 ldr r1, [r2, #4] 278 and r7, r1, #0xff 279 cmp r7, #23 /* relative fixup? */ 280 beq fixrel 281 cmp r7, #2 /* absolute fixup? */ 282 beq fixabs 283 /* ignore unknown type of fixup */ 284 b fixnext 285fixabs: 286 /* absolute fix: set location to (offset) symbol value */ 287 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 288 add r1, r10, r1 /* r1 <- address of symbol in table */ 289 ldr r1, [r1, #4] /* r1 <- symbol value */ 290 add r1, r1, r9 /* r1 <- relocated sym addr */ 291 b fixnext 292fixrel: 293 /* relative fix: increase location by offset */ 294 ldr r1, [r0] 295 add r1, r1, r9 296fixnext: 297 str r1, [r0] 298 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 299 cmp r2, r3 300 blo fixloop 301#endif 302 303#ifdef CONFIG_ENABLE_MMU 304enable_mmu: 305 /* enable domain access */ 306 ldr r5, =0x0000ffff 307 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 308 309 /* Set the TTB register */ 310 ldr r0, _mmu_table_base 311 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 312 ldr r2, =0xfff00000 313 bic r0, r0, r2 314 orr r1, r0, r1 315 mcr p15, 0, r1, c2, c0, 0 316 317 /* Enable the MMU */ 318 mrc p15, 0, r0, c1, c0, 0 319 orr r0, r0, #1 /* Set CR_M to enable MMU */ 320 321 /* Prepare to enable the MMU */ 322 adr r1, skip_hw_init 323 and r1, r1, #0x3fc 324 ldr r2, _TEXT_BASE 325 ldr r3, =0xfff00000 326 and r2, r2, r3 327 orr r2, r2, r1 328 b mmu_enable 329 330 .align 5 331 /* Run in a single cache-line */ 332mmu_enable: 333 334 mcr p15, 0, r0, c1, c0, 0 335 nop 336 nop 337 mov pc, r2 338skip_hw_init: 339#endif 340 341relocate_done: 342 343 bx lr 344 345_rel_dyn_start_ofs: 346 .word __rel_dyn_start - _start 347_rel_dyn_end_ofs: 348 .word __rel_dyn_end - _start 349_dynsym_start_ofs: 350 .word __dynsym_start - _start 351 352#ifdef CONFIG_ENABLE_MMU 353_mmu_table_base: 354 .word mmu_table 355#endif 356 357 .globl c_runtime_cpu_setup 358c_runtime_cpu_setup: 359 360 mov pc, lr 361 362#ifndef CONFIG_NAND_SPL 363/* 364 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 365 * actually, we don't need to do anything about cache if not use d-cache in 366 * U-Boot. So, in this function we clean only MMU. by scsuh 367 * 368 * void theLastJump(void *kernel, int arch_num, uint boot_params); 369 */ 370#ifdef CONFIG_ENABLE_MMU 371 .globl theLastJump 372theLastJump: 373 mov r9, r0 374 ldr r3, =0xfff00000 375 ldr r4, _TEXT_PHY_BASE 376 adr r5, phy_last_jump 377 bic r5, r5, r3 378 orr r5, r5, r4 379 mov pc, r5 380phy_last_jump: 381 /* 382 * disable MMU stuff 383 */ 384 mrc p15, 0, r0, c1, c0, 0 385 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 386 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 387 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 388 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 389 mcr p15, 0, r0, c1, c0, 0 390 391 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 392 393 mov r0, #0 394 mov pc, r9 395#endif 396 397 398/* 399 ************************************************************************* 400 * 401 * Interrupt handling 402 * 403 ************************************************************************* 404 */ 405@ 406@ IRQ stack frame. 407@ 408#define S_FRAME_SIZE 72 409 410#define S_OLD_R0 68 411#define S_PSR 64 412#define S_PC 60 413#define S_LR 56 414#define S_SP 52 415 416#define S_IP 48 417#define S_FP 44 418#define S_R10 40 419#define S_R9 36 420#define S_R8 32 421#define S_R7 28 422#define S_R6 24 423#define S_R5 20 424#define S_R4 16 425#define S_R3 12 426#define S_R2 8 427#define S_R1 4 428#define S_R0 0 429 430#define MODE_SVC 0x13 431#define I_BIT 0x80 432 433/* 434 * use bad_save_user_regs for abort/prefetch/undef/swi ... 435 */ 436 437 .macro bad_save_user_regs 438 /* carve out a frame on current user stack */ 439 sub sp, sp, #S_FRAME_SIZE 440 /* Save user registers (now in svc mode) r0-r12 */ 441 stmia sp, {r0 - r12} 442 443 ldr r2, IRQ_STACK_START_IN 444 /* get values for "aborted" pc and cpsr (into parm regs) */ 445 ldmia r2, {r2 - r3} 446 /* grab pointer to old stack */ 447 add r0, sp, #S_FRAME_SIZE 448 449 add r5, sp, #S_SP 450 mov r1, lr 451 /* save sp_SVC, lr_SVC, pc, cpsr */ 452 stmia r5, {r0 - r3} 453 /* save current stack into r0 (param register) */ 454 mov r0, sp 455 .endm 456 457 .macro get_bad_stack 458 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 459 460 /* save caller lr in position 0 of saved stack */ 461 str lr, [r13] 462 /* get the spsr */ 463 mrs lr, spsr 464 /* save spsr in position 1 of saved stack */ 465 str lr, [r13, #4] 466 467 /* prepare SVC-Mode */ 468 mov r13, #MODE_SVC 469 @ msr spsr_c, r13 470 /* switch modes, make sure moves will execute */ 471 msr spsr, r13 472 /* capture return pc */ 473 mov lr, pc 474 /* jump to next instruction & switch modes. */ 475 movs pc, lr 476 .endm 477 478 .macro get_bad_stack_swi 479 /* space on current stack for scratch reg. */ 480 sub r13, r13, #4 481 /* save R0's value. */ 482 str r0, [r13] 483 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 484 /* save caller lr in position 0 of saved stack */ 485 str lr, [r0] 486 /* get the spsr */ 487 mrs r0, spsr 488 /* save spsr in position 1 of saved stack */ 489 str lr, [r0, #4] 490 /* restore r0 */ 491 ldr r0, [r13] 492 /* pop stack entry */ 493 add r13, r13, #4 494 .endm 495 496/* 497 * exception handlers 498 */ 499 .align 5 500undefined_instruction: 501 get_bad_stack 502 bad_save_user_regs 503 bl do_undefined_instruction 504 505 .align 5 506software_interrupt: 507 get_bad_stack_swi 508 bad_save_user_regs 509 bl do_software_interrupt 510 511 .align 5 512prefetch_abort: 513 get_bad_stack 514 bad_save_user_regs 515 bl do_prefetch_abort 516 517 .align 5 518data_abort: 519 get_bad_stack 520 bad_save_user_regs 521 bl do_data_abort 522 523 .align 5 524not_used: 525 get_bad_stack 526 bad_save_user_regs 527 bl do_not_used 528 529 .align 5 530irq: 531 get_bad_stack 532 bad_save_user_regs 533 bl do_irq 534 535 .align 5 536fiq: 537 get_bad_stack 538 bad_save_user_regs 539 bl do_fiq 540#endif /* CONFIG_NAND_SPL */ 541