1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gr�ger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Z�pke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_PRELOADER 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_PRELOADER */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91 .word CONFIG_SYS_TEXT_BASE 92 93/* 94 * These are defined in the board-specific linker script. 95 * Subtracting _start from them lets the linker put their 96 * relative position in the executable instead of leaving 97 * them null. 98 */ 99.globl _bss_start_ofs 100_bss_start_ofs: 101 .word __bss_start - _start 102 103.globl _bss_end_ofs 104_bss_end_ofs: 105 .word _end - _start 106 107#ifdef CONFIG_USE_IRQ 108/* IRQ stack memory (calculated at run-time) */ 109.globl IRQ_STACK_START 110IRQ_STACK_START: 111 .word 0x0badc0de 112 113/* IRQ stack memory (calculated at run-time) */ 114.globl FIQ_STACK_START 115FIQ_STACK_START: 116 .word 0x0badc0de 117#endif 118 119/* IRQ stack memory (calculated at run-time) + 8 bytes */ 120.globl IRQ_STACK_START_IN 121IRQ_STACK_START_IN: 122 .word 0x0badc0de 123 124/* 125 * the actual reset code 126 */ 127 128reset: 129 /* 130 * set the cpu to SVC32 mode 131 */ 132 mrs r0,cpsr 133 bic r0,r0,#0x1f 134 orr r0,r0,#0xd3 135 msr cpsr,r0 136 137#ifdef CONFIG_OMAP2420H4 138 /* Copy vectors to mask ROM indirect addr */ 139 adr r0, _start /* r0 <- current position of code */ 140 add r0, r0, #4 /* skip reset vector */ 141 mov r2, #64 /* r2 <- size to copy */ 142 add r2, r0, r2 /* r2 <- source end address */ 143 mov r1, #SRAM_OFFSET0 /* build vect addr */ 144 mov r3, #SRAM_OFFSET1 145 add r1, r1, r3 146 mov r3, #SRAM_OFFSET2 147 add r1, r1, r3 148next: 149 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 150 stmia r1!, {r3-r10} /* copy to target address [r1] */ 151 cmp r0, r2 /* until source end address [r2] */ 152 bne next /* loop until equal */ 153 bl cpy_clk_code /* put dpll adjust code behind vectors */ 154#endif 155 /* the mask ROM code should have PLL and others stable */ 156#ifndef CONFIG_SKIP_LOWLEVEL_INIT 157 bl cpu_init_crit 158#endif 159 160/* Set stackpointer in internal RAM to call board_init_f */ 161call_board_init_f: 162 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 163 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 164 ldr r0,=0x00000000 165 166#ifdef CONFIG_NAND_SPL 167 bl nand_boot 168#else 169#ifdef CONFIG_ONENAND_IPL 170 bl start_oneboot 171#else 172 bl board_init_f 173#endif /* CONFIG_ONENAND_IPL */ 174#endif /* CONFIG_NAND_SPL */ 175 176/*------------------------------------------------------------------------------*/ 177 178/* 179 * void relocate_code (addr_sp, gd, addr_moni) 180 * 181 * This "function" does not return, instead it continues in RAM 182 * after relocating the monitor code. 183 * 184 */ 185 .globl relocate_code 186relocate_code: 187 mov r4, r0 /* save addr_sp */ 188 mov r5, r1 /* save addr of gd */ 189 mov r6, r2 /* save addr of destination */ 190 191 /* Set up the stack */ 192stack_setup: 193 mov sp, r4 194 195 adr r0, _start 196 cmp r0, r6 197 beq clear_bss /* skip relocation */ 198 mov r1, r6 /* r1 <- scratch for copy_loop */ 199 ldr r3, _bss_start_ofs 200 add r2, r0, r3 /* r2 <- source end address */ 201 202copy_loop: 203 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 204 stmia r1!, {r9-r10} /* copy to target address [r1] */ 205 cmp r0, r2 /* until source end address [r2] */ 206 blo copy_loop 207 208#ifndef CONFIG_PRELOADER 209 /* 210 * fix .rel.dyn relocations 211 */ 212 ldr r0, _TEXT_BASE /* r0 <- Text base */ 213 sub r9, r6, r0 /* r9 <- relocation offset */ 214 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 215 add r10, r10, r0 /* r10 <- sym table in FLASH */ 216 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 217 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 218 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 219 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 220fixloop: 221 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 222 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 223 ldr r1, [r2, #4] 224 and r7, r1, #0xff 225 cmp r7, #23 /* relative fixup? */ 226 beq fixrel 227 cmp r7, #2 /* absolute fixup? */ 228 beq fixabs 229 /* ignore unknown type of fixup */ 230 b fixnext 231fixabs: 232 /* absolute fix: set location to (offset) symbol value */ 233 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 234 add r1, r10, r1 /* r1 <- address of symbol in table */ 235 ldr r1, [r1, #4] /* r1 <- symbol value */ 236 add r1, r1, r9 /* r1 <- relocated sym addr */ 237 b fixnext 238fixrel: 239 /* relative fix: increase location by offset */ 240 ldr r1, [r0] 241 add r1, r1, r9 242fixnext: 243 str r1, [r0] 244 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 245 cmp r2, r3 246 blo fixloop 247#endif 248 249clear_bss: 250#ifndef CONFIG_PRELOADER 251 ldr r0, _bss_start_ofs 252 ldr r1, _bss_end_ofs 253 mov r4, r6 /* reloc addr */ 254 add r0, r0, r4 255 add r1, r1, r4 256 mov r2, #0x00000000 /* clear */ 257 258clbss_l:str r2, [r0] /* clear loop... */ 259 add r0, r0, #4 260 cmp r0, r1 261 bne clbss_l 262#endif /* #ifndef CONFIG_PRELOADER */ 263 264/* 265 * We are done. Do not return, instead branch to second part of board 266 * initialization, now running from RAM. 267 */ 268#ifdef CONFIG_NAND_SPL 269 ldr r0, _nand_boot_ofs 270 adr r1, _start 271 add pc, r0, r1 272_nand_boot_ofs 273 : .word nand_boot - _start 274#else 275jump_2_ram: 276 ldr r0, _board_init_r_ofs 277 adr r1, _start 278 add lr, r0, r1 279 add lr, lr, r9 280 /* setup parameters for board_init_r */ 281 mov r0, r5 /* gd_t */ 282 mov r1, r6 /* dest_addr */ 283 /* jump to it ... */ 284 mov pc, lr 285 286_board_init_r_ofs: 287 .word board_init_r - _start 288#endif 289 290_rel_dyn_start_ofs: 291 .word __rel_dyn_start - _start 292_rel_dyn_end_ofs: 293 .word __rel_dyn_end - _start 294_dynsym_start_ofs: 295 .word __dynsym_start - _start 296 297/* 298 ************************************************************************* 299 * 300 * CPU_init_critical registers 301 * 302 * setup important registers 303 * setup memory timing 304 * 305 ************************************************************************* 306 */ 307#ifndef CONFIG_SKIP_LOWLEVEL_INIT 308cpu_init_crit: 309 /* 310 * flush v4 I/D caches 311 */ 312 mov r0, #0 313 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 314 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 315 316 /* 317 * disable MMU stuff and caches 318 */ 319 mrc p15, 0, r0, c1, c0, 0 320 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 321 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 322 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 323 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 324 mcr p15, 0, r0, c1, c0, 0 325 326 /* 327 * Jump to board specific initialization... The Mask ROM will have already initialized 328 * basic memory. Go here to bump up clock rate and handle wake up conditions. 329 */ 330 mov ip, lr /* persevere link reg across call */ 331 bl lowlevel_init /* go setup pll,mux,memory */ 332 mov lr, ip /* restore link */ 333 mov pc, lr /* back to my caller */ 334#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 335 336#ifndef CONFIG_PRELOADER 337/* 338 ************************************************************************* 339 * 340 * Interrupt handling 341 * 342 ************************************************************************* 343 */ 344@ 345@ IRQ stack frame. 346@ 347#define S_FRAME_SIZE 72 348 349#define S_OLD_R0 68 350#define S_PSR 64 351#define S_PC 60 352#define S_LR 56 353#define S_SP 52 354 355#define S_IP 48 356#define S_FP 44 357#define S_R10 40 358#define S_R9 36 359#define S_R8 32 360#define S_R7 28 361#define S_R6 24 362#define S_R5 20 363#define S_R4 16 364#define S_R3 12 365#define S_R2 8 366#define S_R1 4 367#define S_R0 0 368 369#define MODE_SVC 0x13 370#define I_BIT 0x80 371 372/* 373 * use bad_save_user_regs for abort/prefetch/undef/swi ... 374 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 375 */ 376 377 .macro bad_save_user_regs 378 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 379 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 380 381 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 382 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 383 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 384 385 add r5, sp, #S_SP 386 mov r1, lr 387 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 388 mov r0, sp @ save current stack into r0 (param register) 389 .endm 390 391 .macro irq_save_user_regs 392 sub sp, sp, #S_FRAME_SIZE 393 stmia sp, {r0 - r12} @ Calling r0-r12 394 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 395 stmdb r8, {sp, lr}^ @ Calling SP, LR 396 str lr, [r8, #0] @ Save calling PC 397 mrs r6, spsr 398 str r6, [r8, #4] @ Save CPSR 399 str r0, [r8, #8] @ Save OLD_R0 400 mov r0, sp 401 .endm 402 403 .macro irq_restore_user_regs 404 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 405 mov r0, r0 406 ldr lr, [sp, #S_PC] @ Get PC 407 add sp, sp, #S_FRAME_SIZE 408 subs pc, lr, #4 @ return & move spsr_svc into cpsr 409 .endm 410 411 .macro get_bad_stack 412 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 413 414 str lr, [r13] @ save caller lr in position 0 of saved stack 415 mrs lr, spsr @ get the spsr 416 str lr, [r13, #4] @ save spsr in position 1 of saved stack 417 418 mov r13, #MODE_SVC @ prepare SVC-Mode 419 @ msr spsr_c, r13 420 msr spsr, r13 @ switch modes, make sure moves will execute 421 mov lr, pc @ capture return pc 422 movs pc, lr @ jump to next instruction & switch modes. 423 .endm 424 425 .macro get_bad_stack_swi 426 sub r13, r13, #4 @ space on current stack for scratch reg. 427 str r0, [r13] @ save R0's value. 428 ldr r0, IRQ_STACK_START_IN @ get data regions start 429 str lr, [r0] @ save caller lr in position 0 of saved stack 430 mrs r0, spsr @ get the spsr 431 str lr, [r0, #4] @ save spsr in position 1 of saved stack 432 ldr r0, [r13] @ restore r0 433 add r13, r13, #4 @ pop stack entry 434 .endm 435 436 .macro get_irq_stack @ setup IRQ stack 437 ldr sp, IRQ_STACK_START 438 .endm 439 440 .macro get_fiq_stack @ setup FIQ stack 441 ldr sp, FIQ_STACK_START 442 .endm 443#endif /* CONFIG_PRELOADER */ 444 445/* 446 * exception handlers 447 */ 448#ifdef CONFIG_PRELOADER 449 .align 5 450do_hang: 451 ldr sp, _TEXT_BASE /* use 32 words about stack */ 452 bl hang /* hang and never return */ 453#else /* !CONFIG_PRELOADER */ 454 .align 5 455undefined_instruction: 456 get_bad_stack 457 bad_save_user_regs 458 bl do_undefined_instruction 459 460 .align 5 461software_interrupt: 462 get_bad_stack_swi 463 bad_save_user_regs 464 bl do_software_interrupt 465 466 .align 5 467prefetch_abort: 468 get_bad_stack 469 bad_save_user_regs 470 bl do_prefetch_abort 471 472 .align 5 473data_abort: 474 get_bad_stack 475 bad_save_user_regs 476 bl do_data_abort 477 478 .align 5 479not_used: 480 get_bad_stack 481 bad_save_user_regs 482 bl do_not_used 483 484#ifdef CONFIG_USE_IRQ 485 486 .align 5 487irq: 488 get_irq_stack 489 irq_save_user_regs 490 bl do_irq 491 irq_restore_user_regs 492 493 .align 5 494fiq: 495 get_fiq_stack 496 /* someone ought to write a more effiction fiq_save_user_regs */ 497 irq_save_user_regs 498 bl do_fiq 499 irq_restore_user_regs 500 501#else 502 503 .align 5 504irq: 505 get_bad_stack 506 bad_save_user_regs 507 bl do_irq 508 509 .align 5 510fiq: 511 get_bad_stack 512 bad_save_user_regs 513 bl do_fiq 514 515#endif 516 .align 5 517.global arm1136_cache_flush 518arm1136_cache_flush: 519#if !defined(CONFIG_SYS_NO_ICACHE) 520 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 521#endif 522#if !defined(CONFIG_SYS_NO_DCACHE) 523 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 524#endif 525 mov pc, lr @ back to caller 526#endif /* CONFIG_PRELOADER */ 527