1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 92 .word CONFIG_SPL_TEXT_BASE 93#else 94 .word CONFIG_SYS_TEXT_BASE 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 * Subtracting _start from them lets the linker put their 100 * relative position in the executable instead of leaving 101 * them null. 102 */ 103.globl _bss_start_ofs 104_bss_start_ofs: 105 .word __bss_start - _start 106 107.global _image_copy_end_ofs 108_image_copy_end_ofs: 109 .word __image_copy_end - _start 110 111.globl _bss_end_ofs 112_bss_end_ofs: 113 .word __bss_end - _start 114 115.globl _end_ofs 116_end_ofs: 117 .word _end - _start 118 119#ifdef CONFIG_USE_IRQ 120/* IRQ stack memory (calculated at run-time) */ 121.globl IRQ_STACK_START 122IRQ_STACK_START: 123 .word 0x0badc0de 124 125/* IRQ stack memory (calculated at run-time) */ 126.globl FIQ_STACK_START 127FIQ_STACK_START: 128 .word 0x0badc0de 129#endif 130 131/* IRQ stack memory (calculated at run-time) + 8 bytes */ 132.globl IRQ_STACK_START_IN 133IRQ_STACK_START_IN: 134 .word 0x0badc0de 135 136/* 137 * the actual reset code 138 */ 139 140reset: 141 /* 142 * set the cpu to SVC32 mode 143 */ 144 mrs r0,cpsr 145 bic r0,r0,#0x1f 146 orr r0,r0,#0xd3 147 msr cpsr,r0 148 149#ifdef CONFIG_OMAP2420H4 150 /* Copy vectors to mask ROM indirect addr */ 151 adr r0, _start /* r0 <- current position of code */ 152 add r0, r0, #4 /* skip reset vector */ 153 mov r2, #64 /* r2 <- size to copy */ 154 add r2, r0, r2 /* r2 <- source end address */ 155 mov r1, #SRAM_OFFSET0 /* build vect addr */ 156 mov r3, #SRAM_OFFSET1 157 add r1, r1, r3 158 mov r3, #SRAM_OFFSET2 159 add r1, r1, r3 160next: 161 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 162 stmia r1!, {r3-r10} /* copy to target address [r1] */ 163 cmp r0, r2 /* until source end address [r2] */ 164 bne next /* loop until equal */ 165 bl cpy_clk_code /* put dpll adjust code behind vectors */ 166#endif 167 /* the mask ROM code should have PLL and others stable */ 168#ifndef CONFIG_SKIP_LOWLEVEL_INIT 169 bl cpu_init_crit 170#endif 171 172 bl _main 173 174/*------------------------------------------------------------------------------*/ 175 176/* 177 * void relocate_code (addr_sp, gd, addr_moni) 178 * 179 * This function relocates the monitor code. 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 187 adr r0, _start 188 cmp r0, r6 189 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 190 beq relocate_done /* skip relocation */ 191 mov r1, r6 /* r1 <- scratch for copy_loop */ 192 ldr r3, _image_copy_end_ofs 193 add r2, r0, r3 /* r2 <- source end address */ 194 195copy_loop: 196 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 197 stmia r1!, {r9-r10} /* copy to target address [r1] */ 198 cmp r0, r2 /* until source end address [r2] */ 199 blo copy_loop 200 201#ifndef CONFIG_SPL_BUILD 202 /* 203 * fix .rel.dyn relocations 204 */ 205 ldr r0, _TEXT_BASE /* r0 <- Text base */ 206 sub r9, r6, r0 /* r9 <- relocation offset */ 207 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 208 add r10, r10, r0 /* r10 <- sym table in FLASH */ 209 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 210 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 211 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 212 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 213fixloop: 214 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 215 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 216 ldr r1, [r2, #4] 217 and r7, r1, #0xff 218 cmp r7, #23 /* relative fixup? */ 219 beq fixrel 220 cmp r7, #2 /* absolute fixup? */ 221 beq fixabs 222 /* ignore unknown type of fixup */ 223 b fixnext 224fixabs: 225 /* absolute fix: set location to (offset) symbol value */ 226 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 227 add r1, r10, r1 /* r1 <- address of symbol in table */ 228 ldr r1, [r1, #4] /* r1 <- symbol value */ 229 add r1, r1, r9 /* r1 <- relocated sym addr */ 230 b fixnext 231fixrel: 232 /* relative fix: increase location by offset */ 233 ldr r1, [r0] 234 add r1, r1, r9 235fixnext: 236 str r1, [r0] 237 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 238 cmp r2, r3 239 blo fixloop 240 bx lr 241 242#endif 243 244relocate_done: 245 246 bx lr 247 248#ifndef CONFIG_SPL_BUILD 249 250_rel_dyn_start_ofs: 251 .word __rel_dyn_start - _start 252_rel_dyn_end_ofs: 253 .word __rel_dyn_end - _start 254_dynsym_start_ofs: 255 .word __dynsym_start - _start 256 257#endif 258 259 .globl c_runtime_cpu_setup 260c_runtime_cpu_setup: 261 262 bx lr 263 264/* 265 ************************************************************************* 266 * 267 * CPU_init_critical registers 268 * 269 * setup important registers 270 * setup memory timing 271 * 272 ************************************************************************* 273 */ 274#ifndef CONFIG_SKIP_LOWLEVEL_INIT 275cpu_init_crit: 276 /* 277 * flush v4 I/D caches 278 */ 279 mov r0, #0 280 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 281 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 282 283 /* 284 * disable MMU stuff and caches 285 */ 286 mrc p15, 0, r0, c1, c0, 0 287 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 288 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 289 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 290 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 291 mcr p15, 0, r0, c1, c0, 0 292 293 /* 294 * Jump to board specific initialization... The Mask ROM will have already initialized 295 * basic memory. Go here to bump up clock rate and handle wake up conditions. 296 */ 297 mov ip, lr /* persevere link reg across call */ 298 bl lowlevel_init /* go setup pll,mux,memory */ 299 mov lr, ip /* restore link */ 300 mov pc, lr /* back to my caller */ 301#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 302 303#ifndef CONFIG_SPL_BUILD 304/* 305 ************************************************************************* 306 * 307 * Interrupt handling 308 * 309 ************************************************************************* 310 */ 311@ 312@ IRQ stack frame. 313@ 314#define S_FRAME_SIZE 72 315 316#define S_OLD_R0 68 317#define S_PSR 64 318#define S_PC 60 319#define S_LR 56 320#define S_SP 52 321 322#define S_IP 48 323#define S_FP 44 324#define S_R10 40 325#define S_R9 36 326#define S_R8 32 327#define S_R7 28 328#define S_R6 24 329#define S_R5 20 330#define S_R4 16 331#define S_R3 12 332#define S_R2 8 333#define S_R1 4 334#define S_R0 0 335 336#define MODE_SVC 0x13 337#define I_BIT 0x80 338 339/* 340 * use bad_save_user_regs for abort/prefetch/undef/swi ... 341 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 342 */ 343 344 .macro bad_save_user_regs 345 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 346 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 347 348 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 349 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 350 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 351 352 add r5, sp, #S_SP 353 mov r1, lr 354 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 355 mov r0, sp @ save current stack into r0 (param register) 356 .endm 357 358 .macro irq_save_user_regs 359 sub sp, sp, #S_FRAME_SIZE 360 stmia sp, {r0 - r12} @ Calling r0-r12 361 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 362 stmdb r8, {sp, lr}^ @ Calling SP, LR 363 str lr, [r8, #0] @ Save calling PC 364 mrs r6, spsr 365 str r6, [r8, #4] @ Save CPSR 366 str r0, [r8, #8] @ Save OLD_R0 367 mov r0, sp 368 .endm 369 370 .macro irq_restore_user_regs 371 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 372 mov r0, r0 373 ldr lr, [sp, #S_PC] @ Get PC 374 add sp, sp, #S_FRAME_SIZE 375 subs pc, lr, #4 @ return & move spsr_svc into cpsr 376 .endm 377 378 .macro get_bad_stack 379 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 380 381 str lr, [r13] @ save caller lr in position 0 of saved stack 382 mrs lr, spsr @ get the spsr 383 str lr, [r13, #4] @ save spsr in position 1 of saved stack 384 385 mov r13, #MODE_SVC @ prepare SVC-Mode 386 @ msr spsr_c, r13 387 msr spsr, r13 @ switch modes, make sure moves will execute 388 mov lr, pc @ capture return pc 389 movs pc, lr @ jump to next instruction & switch modes. 390 .endm 391 392 .macro get_bad_stack_swi 393 sub r13, r13, #4 @ space on current stack for scratch reg. 394 str r0, [r13] @ save R0's value. 395 ldr r0, IRQ_STACK_START_IN @ get data regions start 396 str lr, [r0] @ save caller lr in position 0 of saved stack 397 mrs r0, spsr @ get the spsr 398 str lr, [r0, #4] @ save spsr in position 1 of saved stack 399 ldr r0, [r13] @ restore r0 400 add r13, r13, #4 @ pop stack entry 401 .endm 402 403 .macro get_irq_stack @ setup IRQ stack 404 ldr sp, IRQ_STACK_START 405 .endm 406 407 .macro get_fiq_stack @ setup FIQ stack 408 ldr sp, FIQ_STACK_START 409 .endm 410#endif /* CONFIG_SPL_BUILD */ 411 412/* 413 * exception handlers 414 */ 415#ifdef CONFIG_SPL_BUILD 416 .align 5 417do_hang: 418 ldr sp, _TEXT_BASE /* use 32 words about stack */ 419 bl hang /* hang and never return */ 420#else /* !CONFIG_SPL_BUILD */ 421 .align 5 422undefined_instruction: 423 get_bad_stack 424 bad_save_user_regs 425 bl do_undefined_instruction 426 427 .align 5 428software_interrupt: 429 get_bad_stack_swi 430 bad_save_user_regs 431 bl do_software_interrupt 432 433 .align 5 434prefetch_abort: 435 get_bad_stack 436 bad_save_user_regs 437 bl do_prefetch_abort 438 439 .align 5 440data_abort: 441 get_bad_stack 442 bad_save_user_regs 443 bl do_data_abort 444 445 .align 5 446not_used: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_not_used 450 451#ifdef CONFIG_USE_IRQ 452 453 .align 5 454irq: 455 get_irq_stack 456 irq_save_user_regs 457 bl do_irq 458 irq_restore_user_regs 459 460 .align 5 461fiq: 462 get_fiq_stack 463 /* someone ought to write a more effiction fiq_save_user_regs */ 464 irq_save_user_regs 465 bl do_fiq 466 irq_restore_user_regs 467 468#else 469 470 .align 5 471irq: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_irq 475 476 .align 5 477fiq: 478 get_bad_stack 479 bad_save_user_regs 480 bl do_fiq 481 482#endif 483 .align 5 484.global arm1136_cache_flush 485arm1136_cache_flush: 486#if !defined(CONFIG_SYS_ICACHE_OFF) 487 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 488#endif 489#if !defined(CONFIG_SYS_DCACHE_OFF) 490 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 491#endif 492 mov pc, lr @ back to caller 493#endif /* CONFIG_SPL_BUILD */ 494