1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 92 .word CONFIG_SPL_TEXT_BASE 93#else 94 .word CONFIG_SYS_TEXT_BASE 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 * Subtracting _start from them lets the linker put their 100 * relative position in the executable instead of leaving 101 * them null. 102 */ 103.globl _bss_start_ofs 104_bss_start_ofs: 105 .word __bss_start - _start 106 107.global _image_copy_end_ofs 108_image_copy_end_ofs: 109 .word __image_copy_end - _start 110 111.globl _bss_end_ofs 112_bss_end_ofs: 113 .word __bss_end - _start 114 115.globl _end_ofs 116_end_ofs: 117 .word _end - _start 118 119#ifdef CONFIG_USE_IRQ 120/* IRQ stack memory (calculated at run-time) */ 121.globl IRQ_STACK_START 122IRQ_STACK_START: 123 .word 0x0badc0de 124 125/* IRQ stack memory (calculated at run-time) */ 126.globl FIQ_STACK_START 127FIQ_STACK_START: 128 .word 0x0badc0de 129#endif 130 131/* IRQ stack memory (calculated at run-time) + 8 bytes */ 132.globl IRQ_STACK_START_IN 133IRQ_STACK_START_IN: 134 .word 0x0badc0de 135 136/* 137 * the actual reset code 138 */ 139 140reset: 141 /* 142 * set the cpu to SVC32 mode 143 */ 144 mrs r0,cpsr 145 bic r0,r0,#0x1f 146 orr r0,r0,#0xd3 147 msr cpsr,r0 148 149#ifdef CONFIG_OMAP2420H4 150 /* Copy vectors to mask ROM indirect addr */ 151 adr r0, _start /* r0 <- current position of code */ 152 add r0, r0, #4 /* skip reset vector */ 153 mov r2, #64 /* r2 <- size to copy */ 154 add r2, r0, r2 /* r2 <- source end address */ 155 mov r1, #SRAM_OFFSET0 /* build vect addr */ 156 mov r3, #SRAM_OFFSET1 157 add r1, r1, r3 158 mov r3, #SRAM_OFFSET2 159 add r1, r1, r3 160next: 161 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 162 stmia r1!, {r3-r10} /* copy to target address [r1] */ 163 cmp r0, r2 /* until source end address [r2] */ 164 bne next /* loop until equal */ 165 bl cpy_clk_code /* put dpll adjust code behind vectors */ 166#endif 167 /* the mask ROM code should have PLL and others stable */ 168#ifndef CONFIG_SKIP_LOWLEVEL_INIT 169 bl cpu_init_crit 170#endif 171 172 bl _main 173 174/*------------------------------------------------------------------------------*/ 175 176/* 177 * void relocate_code (addr_sp, gd, addr_moni) 178 * 179 * This "function" does not return, instead it continues in RAM 180 * after relocating the monitor code. 181 * 182 */ 183 .globl relocate_code 184relocate_code: 185 mov r4, r0 /* save addr_sp */ 186 mov r5, r1 /* save addr of gd */ 187 mov r6, r2 /* save addr of destination */ 188 189 adr r0, _start 190 cmp r0, r6 191 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 192 beq relocate_done /* skip relocation */ 193 mov r1, r6 /* r1 <- scratch for copy_loop */ 194 ldr r3, _image_copy_end_ofs 195 add r2, r0, r3 /* r2 <- source end address */ 196 197copy_loop: 198 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 199 stmia r1!, {r9-r10} /* copy to target address [r1] */ 200 cmp r0, r2 /* until source end address [r2] */ 201 blo copy_loop 202 203#ifndef CONFIG_SPL_BUILD 204 /* 205 * fix .rel.dyn relocations 206 */ 207 ldr r0, _TEXT_BASE /* r0 <- Text base */ 208 sub r9, r6, r0 /* r9 <- relocation offset */ 209 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 210 add r10, r10, r0 /* r10 <- sym table in FLASH */ 211 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 212 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 213 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 214 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 215fixloop: 216 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 217 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 218 ldr r1, [r2, #4] 219 and r7, r1, #0xff 220 cmp r7, #23 /* relative fixup? */ 221 beq fixrel 222 cmp r7, #2 /* absolute fixup? */ 223 beq fixabs 224 /* ignore unknown type of fixup */ 225 b fixnext 226fixabs: 227 /* absolute fix: set location to (offset) symbol value */ 228 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 229 add r1, r10, r1 /* r1 <- address of symbol in table */ 230 ldr r1, [r1, #4] /* r1 <- symbol value */ 231 add r1, r1, r9 /* r1 <- relocated sym addr */ 232 b fixnext 233fixrel: 234 /* relative fix: increase location by offset */ 235 ldr r1, [r0] 236 add r1, r1, r9 237fixnext: 238 str r1, [r0] 239 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 240 cmp r2, r3 241 blo fixloop 242 bx lr 243 244#endif 245 246relocate_done: 247 248 bx lr 249 250#ifndef CONFIG_SPL_BUILD 251 252_rel_dyn_start_ofs: 253 .word __rel_dyn_start - _start 254_rel_dyn_end_ofs: 255 .word __rel_dyn_end - _start 256_dynsym_start_ofs: 257 .word __dynsym_start - _start 258 259#endif 260 261 .globl c_runtime_cpu_setup 262c_runtime_cpu_setup: 263 264 bx lr 265 266/* 267 ************************************************************************* 268 * 269 * CPU_init_critical registers 270 * 271 * setup important registers 272 * setup memory timing 273 * 274 ************************************************************************* 275 */ 276#ifndef CONFIG_SKIP_LOWLEVEL_INIT 277cpu_init_crit: 278 /* 279 * flush v4 I/D caches 280 */ 281 mov r0, #0 282 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 283 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 284 285 /* 286 * disable MMU stuff and caches 287 */ 288 mrc p15, 0, r0, c1, c0, 0 289 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 290 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 291 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 292 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 293 mcr p15, 0, r0, c1, c0, 0 294 295 /* 296 * Jump to board specific initialization... The Mask ROM will have already initialized 297 * basic memory. Go here to bump up clock rate and handle wake up conditions. 298 */ 299 mov ip, lr /* persevere link reg across call */ 300 bl lowlevel_init /* go setup pll,mux,memory */ 301 mov lr, ip /* restore link */ 302 mov pc, lr /* back to my caller */ 303#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 304 305#ifndef CONFIG_SPL_BUILD 306/* 307 ************************************************************************* 308 * 309 * Interrupt handling 310 * 311 ************************************************************************* 312 */ 313@ 314@ IRQ stack frame. 315@ 316#define S_FRAME_SIZE 72 317 318#define S_OLD_R0 68 319#define S_PSR 64 320#define S_PC 60 321#define S_LR 56 322#define S_SP 52 323 324#define S_IP 48 325#define S_FP 44 326#define S_R10 40 327#define S_R9 36 328#define S_R8 32 329#define S_R7 28 330#define S_R6 24 331#define S_R5 20 332#define S_R4 16 333#define S_R3 12 334#define S_R2 8 335#define S_R1 4 336#define S_R0 0 337 338#define MODE_SVC 0x13 339#define I_BIT 0x80 340 341/* 342 * use bad_save_user_regs for abort/prefetch/undef/swi ... 343 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 344 */ 345 346 .macro bad_save_user_regs 347 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 348 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 349 350 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 351 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 352 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 353 354 add r5, sp, #S_SP 355 mov r1, lr 356 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 357 mov r0, sp @ save current stack into r0 (param register) 358 .endm 359 360 .macro irq_save_user_regs 361 sub sp, sp, #S_FRAME_SIZE 362 stmia sp, {r0 - r12} @ Calling r0-r12 363 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 364 stmdb r8, {sp, lr}^ @ Calling SP, LR 365 str lr, [r8, #0] @ Save calling PC 366 mrs r6, spsr 367 str r6, [r8, #4] @ Save CPSR 368 str r0, [r8, #8] @ Save OLD_R0 369 mov r0, sp 370 .endm 371 372 .macro irq_restore_user_regs 373 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 374 mov r0, r0 375 ldr lr, [sp, #S_PC] @ Get PC 376 add sp, sp, #S_FRAME_SIZE 377 subs pc, lr, #4 @ return & move spsr_svc into cpsr 378 .endm 379 380 .macro get_bad_stack 381 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 382 383 str lr, [r13] @ save caller lr in position 0 of saved stack 384 mrs lr, spsr @ get the spsr 385 str lr, [r13, #4] @ save spsr in position 1 of saved stack 386 387 mov r13, #MODE_SVC @ prepare SVC-Mode 388 @ msr spsr_c, r13 389 msr spsr, r13 @ switch modes, make sure moves will execute 390 mov lr, pc @ capture return pc 391 movs pc, lr @ jump to next instruction & switch modes. 392 .endm 393 394 .macro get_bad_stack_swi 395 sub r13, r13, #4 @ space on current stack for scratch reg. 396 str r0, [r13] @ save R0's value. 397 ldr r0, IRQ_STACK_START_IN @ get data regions start 398 str lr, [r0] @ save caller lr in position 0 of saved stack 399 mrs r0, spsr @ get the spsr 400 str lr, [r0, #4] @ save spsr in position 1 of saved stack 401 ldr r0, [r13] @ restore r0 402 add r13, r13, #4 @ pop stack entry 403 .endm 404 405 .macro get_irq_stack @ setup IRQ stack 406 ldr sp, IRQ_STACK_START 407 .endm 408 409 .macro get_fiq_stack @ setup FIQ stack 410 ldr sp, FIQ_STACK_START 411 .endm 412#endif /* CONFIG_SPL_BUILD */ 413 414/* 415 * exception handlers 416 */ 417#ifdef CONFIG_SPL_BUILD 418 .align 5 419do_hang: 420 ldr sp, _TEXT_BASE /* use 32 words about stack */ 421 bl hang /* hang and never return */ 422#else /* !CONFIG_SPL_BUILD */ 423 .align 5 424undefined_instruction: 425 get_bad_stack 426 bad_save_user_regs 427 bl do_undefined_instruction 428 429 .align 5 430software_interrupt: 431 get_bad_stack_swi 432 bad_save_user_regs 433 bl do_software_interrupt 434 435 .align 5 436prefetch_abort: 437 get_bad_stack 438 bad_save_user_regs 439 bl do_prefetch_abort 440 441 .align 5 442data_abort: 443 get_bad_stack 444 bad_save_user_regs 445 bl do_data_abort 446 447 .align 5 448not_used: 449 get_bad_stack 450 bad_save_user_regs 451 bl do_not_used 452 453#ifdef CONFIG_USE_IRQ 454 455 .align 5 456irq: 457 get_irq_stack 458 irq_save_user_regs 459 bl do_irq 460 irq_restore_user_regs 461 462 .align 5 463fiq: 464 get_fiq_stack 465 /* someone ought to write a more effiction fiq_save_user_regs */ 466 irq_save_user_regs 467 bl do_fiq 468 irq_restore_user_regs 469 470#else 471 472 .align 5 473irq: 474 get_bad_stack 475 bad_save_user_regs 476 bl do_irq 477 478 .align 5 479fiq: 480 get_bad_stack 481 bad_save_user_regs 482 bl do_fiq 483 484#endif 485 .align 5 486.global arm1136_cache_flush 487arm1136_cache_flush: 488#if !defined(CONFIG_SYS_ICACHE_OFF) 489 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 490#endif 491#if !defined(CONFIG_SYS_DCACHE_OFF) 492 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 493#endif 494 mov pc, lr @ back to caller 495#endif /* CONFIG_SPL_BUILD */ 496