1 /* 2 * (C) Copyright 2007 3 * Sascha Hauer, Pengutronix 4 * 5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <div64.h> 28 #include <asm/io.h> 29 #include <asm/errno.h> 30 #include <asm/arch/imx-regs.h> 31 #include <asm/arch/crm_regs.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/sys_proto.h> 34 #ifdef CONFIG_FSL_ESDHC 35 #include <fsl_esdhc.h> 36 #endif 37 #include <netdev.h> 38 39 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) 40 #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) 41 #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) 42 #define CLK_CODE_PATH(c) ((c) & 0xFF) 43 44 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) 45 46 #ifdef CONFIG_FSL_ESDHC 47 DECLARE_GLOBAL_DATA_PTR; 48 #endif 49 50 static int g_clk_mux_auto[8] = { 51 CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, 52 CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, 53 }; 54 55 static int g_clk_mux_consumer[16] = { 56 CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, 57 -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), 58 CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, 59 -1, -1, CLK_CODE(4, 2, 0), -1, 60 }; 61 62 static int hsp_div_table[3][16] = { 63 {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, 64 {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, 65 {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, 66 }; 67 68 u32 get_cpu_rev(void) 69 { 70 int reg; 71 struct iim_regs *iim = 72 (struct iim_regs *)IIM_BASE_ADDR; 73 reg = readl(&iim->iim_srev); 74 if (!reg) { 75 reg = readw(ROMPATCH_REV); 76 reg <<= 4; 77 } else { 78 reg += CHIP_REV_1_0; 79 } 80 81 return 0x35000 + (reg & 0xFF); 82 } 83 84 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) 85 { 86 int *pclk_mux; 87 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 88 pclk_mux = g_clk_mux_consumer + 89 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 90 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 91 } else { 92 pclk_mux = g_clk_mux_auto + 93 ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> 94 MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); 95 } 96 97 if ((*pclk_mux) == -1) 98 return -1; 99 100 if (fi && fd) { 101 if (!CLK_CODE_PATH(*pclk_mux)) { 102 *fi = *fd = 1; 103 return CLK_CODE_ARM(*pclk_mux); 104 } 105 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { 106 *fi = 3; 107 *fd = 4; 108 } else { 109 *fi = 2; 110 *fd = 3; 111 } 112 } 113 return CLK_CODE_ARM(*pclk_mux); 114 } 115 116 static int get_ahb_div(u32 pdr0) 117 { 118 int *pclk_mux; 119 120 pclk_mux = g_clk_mux_consumer + 121 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> 122 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); 123 124 if ((*pclk_mux) == -1) 125 return -1; 126 127 return CLK_CODE_AHB(*pclk_mux); 128 } 129 130 static u32 decode_pll(u32 reg, u32 infreq) 131 { 132 u32 mfi = (reg >> 10) & 0xf; 133 s32 mfn = reg & 0x3ff; 134 u32 mfd = (reg >> 16) & 0x3ff; 135 u32 pd = (reg >> 26) & 0xf; 136 137 mfi = mfi <= 5 ? 5 : mfi; 138 mfn = mfn >= 512 ? mfn - 1024 : mfn; 139 mfd += 1; 140 pd += 1; 141 142 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), 143 mfd * pd); 144 } 145 146 static u32 get_mcu_main_clk(void) 147 { 148 u32 arm_div = 0, fi = 0, fd = 0; 149 struct ccm_regs *ccm = 150 (struct ccm_regs *)IMX_CCM_BASE; 151 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); 152 fi *= 153 decode_pll(readl(&ccm->mpctl), 154 CONFIG_MX35_HCLK_FREQ); 155 return fi / (arm_div * fd); 156 } 157 158 static u32 get_ipg_clk(void) 159 { 160 u32 freq = get_mcu_main_clk(); 161 struct ccm_regs *ccm = 162 (struct ccm_regs *)IMX_CCM_BASE; 163 u32 pdr0 = readl(&ccm->pdr0); 164 165 return freq / (get_ahb_div(pdr0) * 2); 166 } 167 168 static u32 get_ipg_per_clk(void) 169 { 170 u32 freq = get_mcu_main_clk(); 171 struct ccm_regs *ccm = 172 (struct ccm_regs *)IMX_CCM_BASE; 173 u32 pdr0 = readl(&ccm->pdr0); 174 u32 pdr4 = readl(&ccm->pdr4); 175 u32 div; 176 if (pdr0 & MXC_CCM_PDR0_PER_SEL) { 177 div = CCM_GET_DIVIDER(pdr4, 178 MXC_CCM_PDR4_PER0_PODF_MASK, 179 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; 180 } else { 181 div = CCM_GET_DIVIDER(pdr0, 182 MXC_CCM_PDR0_PER_PODF_MASK, 183 MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; 184 div *= get_ahb_div(pdr0); 185 } 186 return freq / div; 187 } 188 189 u32 imx_get_uartclk(void) 190 { 191 u32 freq; 192 struct ccm_regs *ccm = 193 (struct ccm_regs *)IMX_CCM_BASE; 194 u32 pdr4 = readl(&ccm->pdr4); 195 196 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { 197 freq = get_mcu_main_clk(); 198 } else { 199 freq = decode_pll(readl(&ccm->ppctl), 200 CONFIG_MX35_HCLK_FREQ); 201 } 202 freq /= CCM_GET_DIVIDER(pdr4, 203 MXC_CCM_PDR4_UART_PODF_MASK, 204 MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; 205 return freq; 206 } 207 208 unsigned int mxc_get_main_clock(enum mxc_main_clock clk) 209 { 210 u32 nfc_pdf, hsp_podf; 211 u32 pll, ret_val = 0, usb_podf; 212 struct ccm_regs *ccm = 213 (struct ccm_regs *)IMX_CCM_BASE; 214 215 u32 reg = readl(&ccm->pdr0); 216 u32 reg4 = readl(&ccm->pdr4); 217 218 reg |= 0x1; 219 220 switch (clk) { 221 case CPU_CLK: 222 ret_val = get_mcu_main_clk(); 223 break; 224 case AHB_CLK: 225 ret_val = get_mcu_main_clk(); 226 break; 227 case HSP_CLK: 228 if (reg & CLKMODE_CONSUMER) { 229 hsp_podf = (reg >> 20) & 0x3; 230 pll = get_mcu_main_clk(); 231 hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; 232 if (hsp_podf > 0) { 233 ret_val = pll / hsp_podf; 234 } else { 235 puts("mismatch HSP with ARM clock setting\n"); 236 ret_val = 0; 237 } 238 } else { 239 ret_val = get_mcu_main_clk(); 240 } 241 break; 242 case IPG_CLK: 243 ret_val = get_ipg_clk(); 244 break; 245 case IPG_PER_CLK: 246 ret_val = get_ipg_per_clk(); 247 break; 248 case NFC_CLK: 249 nfc_pdf = (reg4 >> 28) & 0xF; 250 pll = get_mcu_main_clk(); 251 /* AHB/nfc_pdf */ 252 ret_val = pll / (nfc_pdf + 1); 253 break; 254 case USB_CLK: 255 usb_podf = (reg4 >> 22) & 0x3F; 256 if (reg4 & 0x200) { 257 pll = get_mcu_main_clk(); 258 } else { 259 pll = decode_pll(readl(&ccm->ppctl), 260 CONFIG_MX35_HCLK_FREQ); 261 } 262 263 ret_val = pll / (usb_podf + 1); 264 break; 265 default: 266 printf("Unknown clock: %d\n", clk); 267 break; 268 } 269 270 return ret_val; 271 } 272 unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) 273 { 274 u32 ret_val = 0, pdf, pre_pdf, clk_sel; 275 struct ccm_regs *ccm = 276 (struct ccm_regs *)IMX_CCM_BASE; 277 u32 mpdr2 = readl(&ccm->pdr2); 278 u32 mpdr3 = readl(&ccm->pdr3); 279 u32 mpdr4 = readl(&ccm->pdr4); 280 281 switch (clk) { 282 case UART1_BAUD: 283 case UART2_BAUD: 284 case UART3_BAUD: 285 clk_sel = mpdr3 & (1 << 14); 286 pdf = (mpdr4 >> 10) & 0x3F; 287 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 288 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 289 (pdf + 1); 290 break; 291 case SSI1_BAUD: 292 pre_pdf = (mpdr2 >> 24) & 0x7; 293 pdf = mpdr2 & 0x3F; 294 clk_sel = mpdr2 & (1 << 6); 295 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 296 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 297 ((pre_pdf + 1) * (pdf + 1)); 298 break; 299 case SSI2_BAUD: 300 pre_pdf = (mpdr2 >> 27) & 0x7; 301 pdf = (mpdr2 >> 8) & 0x3F; 302 clk_sel = mpdr2 & (1 << 6); 303 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 304 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 305 ((pre_pdf + 1) * (pdf + 1)); 306 break; 307 case CSI_BAUD: 308 clk_sel = mpdr2 & (1 << 7); 309 pdf = (mpdr2 >> 16) & 0x3F; 310 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 311 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 312 (pdf + 1); 313 break; 314 case MSHC_CLK: 315 pre_pdf = readl(&ccm->pdr1); 316 clk_sel = (pre_pdf & 0x80); 317 pdf = (pre_pdf >> 22) & 0x3F; 318 pre_pdf = (pre_pdf >> 28) & 0x7; 319 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 320 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 321 ((pre_pdf + 1) * (pdf + 1)); 322 break; 323 case ESDHC1_CLK: 324 clk_sel = mpdr3 & 0x40; 325 pdf = mpdr3 & 0x3F; 326 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 327 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 328 (pdf + 1); 329 break; 330 case ESDHC2_CLK: 331 clk_sel = mpdr3 & 0x40; 332 pdf = (mpdr3 >> 8) & 0x3F; 333 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 334 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 335 (pdf + 1); 336 break; 337 case ESDHC3_CLK: 338 clk_sel = mpdr3 & 0x40; 339 pdf = (mpdr3 >> 16) & 0x3F; 340 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 341 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 342 (pdf + 1); 343 break; 344 case SPDIF_CLK: 345 clk_sel = mpdr3 & 0x400000; 346 pre_pdf = (mpdr3 >> 29) & 0x7; 347 pdf = (mpdr3 >> 23) & 0x3F; 348 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : 349 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / 350 ((pre_pdf + 1) * (pdf + 1)); 351 break; 352 default: 353 printf("%s(): This clock: %d not supported yet\n", 354 __func__, clk); 355 break; 356 } 357 358 return ret_val; 359 } 360 361 unsigned int mxc_get_clock(enum mxc_clock clk) 362 { 363 switch (clk) { 364 case MXC_ARM_CLK: 365 return get_mcu_main_clk(); 366 case MXC_AHB_CLK: 367 break; 368 case MXC_IPG_CLK: 369 return get_ipg_clk(); 370 case MXC_IPG_PERCLK: 371 return get_ipg_per_clk(); 372 case MXC_UART_CLK: 373 return imx_get_uartclk(); 374 case MXC_ESDHC_CLK: 375 return mxc_get_peri_clock(ESDHC1_CLK); 376 case MXC_USB_CLK: 377 return mxc_get_main_clock(USB_CLK); 378 case MXC_FEC_CLK: 379 return get_ipg_clk(); 380 case MXC_CSPI_CLK: 381 return get_ipg_clk(); 382 } 383 return -1; 384 } 385 386 #ifdef CONFIG_FEC_MXC 387 /* 388 * The MX35 has no fuse for MAC, return a NULL MAC 389 */ 390 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) 391 { 392 memset(mac, 0, 6); 393 } 394 395 u32 imx_get_fecclk(void) 396 { 397 return mxc_get_clock(MXC_IPG_CLK); 398 } 399 #endif 400 401 int do_mx35_showclocks(cmd_tbl_t *cmdtp, 402 int flag, int argc, char * const argv[]) 403 { 404 u32 cpufreq = get_mcu_main_clk(); 405 printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); 406 printf("ipg clock : %dHz\n", get_ipg_clk()); 407 printf("ipg per clock : %dHz\n", get_ipg_per_clk()); 408 printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); 409 410 return 0; 411 } 412 413 U_BOOT_CMD( 414 clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, 415 "display clocks", 416 "" 417 ); 418 419 #if defined(CONFIG_DISPLAY_CPUINFO) 420 static char *get_reset_cause(void) 421 { 422 /* read RCSR register from CCM module */ 423 struct ccm_regs *ccm = 424 (struct ccm_regs *)IMX_CCM_BASE; 425 426 u32 cause = readl(&ccm->rcsr) & 0x0F; 427 428 switch (cause) { 429 case 0x0000: 430 return "POR"; 431 case 0x0002: 432 return "JTAG"; 433 case 0x0004: 434 return "RST"; 435 case 0x0008: 436 return "WDOG"; 437 default: 438 return "unknown reset"; 439 } 440 } 441 442 int print_cpuinfo(void) 443 { 444 u32 srev = get_cpu_rev(); 445 446 printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", 447 (srev & 0xF0) >> 4, (srev & 0x0F), 448 get_mcu_main_clk() / 1000000); 449 450 printf("Reset cause: %s\n", get_reset_cause()); 451 452 return 0; 453 } 454 #endif 455 456 /* 457 * Initializes on-chip ethernet controllers. 458 * to override, implement board_eth_init() 459 */ 460 int cpu_eth_init(bd_t *bis) 461 { 462 int rc = -ENODEV; 463 464 #if defined(CONFIG_FEC_MXC) 465 rc = fecmxc_initialize(bis); 466 #endif 467 468 return rc; 469 } 470 471 #ifdef CONFIG_FSL_ESDHC 472 /* 473 * Initializes on-chip MMC controllers. 474 * to override, implement board_mmc_init() 475 */ 476 int cpu_mmc_init(bd_t *bis) 477 { 478 return fsl_esdhc_mmc_init(bis); 479 } 480 #endif 481 482 int get_clocks(void) 483 { 484 #ifdef CONFIG_FSL_ESDHC 485 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 486 #endif 487 return 0; 488 } 489 490 void reset_cpu(ulong addr) 491 { 492 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; 493 writew(4, &wdog->wcr); 494 } 495