1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef __ASM_ARC_CACHE_H 8288aaacfSAlexey Brodkin #define __ASM_ARC_CACHE_H 9288aaacfSAlexey Brodkin 10288aaacfSAlexey Brodkin #include <config.h> 11288aaacfSAlexey Brodkin 12288aaacfSAlexey Brodkin /* 13288aaacfSAlexey Brodkin * The current upper bound for ARC L1 data cache line sizes is 128 bytes. 14288aaacfSAlexey Brodkin * We use that value for aligning DMA buffers unless the board config has 15288aaacfSAlexey Brodkin * specified an alternate cache line size. 16288aaacfSAlexey Brodkin */ 17288aaacfSAlexey Brodkin #ifdef CONFIG_SYS_CACHELINE_SIZE 18288aaacfSAlexey Brodkin #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 19288aaacfSAlexey Brodkin #else 20288aaacfSAlexey Brodkin #define ARCH_DMA_MINALIGN 128 21288aaacfSAlexey Brodkin #endif 22288aaacfSAlexey Brodkin 23*812980bdSAlexey Brodkin #if defined(CONFIG_ARC_MMU_V2) 24*812980bdSAlexey Brodkin #define CONFIG_ARC_MMU_VER 2 25*812980bdSAlexey Brodkin #elif defined(CONFIG_ARC_MMU_V3) 26*812980bdSAlexey Brodkin #define CONFIG_ARC_MMU_VER 3 27*812980bdSAlexey Brodkin #endif 28*812980bdSAlexey Brodkin 29288aaacfSAlexey Brodkin #endif /* __ASM_ARC_CACHE_H */ 30