1*288aaacfSAlexey Brodkin /* 2*288aaacfSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3*288aaacfSAlexey Brodkin * 4*288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5*288aaacfSAlexey Brodkin */ 6*288aaacfSAlexey Brodkin 7*288aaacfSAlexey Brodkin #ifndef __ASM_ARC_CACHE_H 8*288aaacfSAlexey Brodkin #define __ASM_ARC_CACHE_H 9*288aaacfSAlexey Brodkin 10*288aaacfSAlexey Brodkin #include <config.h> 11*288aaacfSAlexey Brodkin 12*288aaacfSAlexey Brodkin /* 13*288aaacfSAlexey Brodkin * The current upper bound for ARC L1 data cache line sizes is 128 bytes. 14*288aaacfSAlexey Brodkin * We use that value for aligning DMA buffers unless the board config has 15*288aaacfSAlexey Brodkin * specified an alternate cache line size. 16*288aaacfSAlexey Brodkin */ 17*288aaacfSAlexey Brodkin #ifdef CONFIG_SYS_CACHELINE_SIZE 18*288aaacfSAlexey Brodkin #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 19*288aaacfSAlexey Brodkin #else 20*288aaacfSAlexey Brodkin #define ARCH_DMA_MINALIGN 128 21*288aaacfSAlexey Brodkin #endif 22*288aaacfSAlexey Brodkin 23*288aaacfSAlexey Brodkin #endif /* __ASM_ARC_CACHE_H */ 24