1288aaacfSAlexey Brodkin /* 2288aaacfSAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3288aaacfSAlexey Brodkin * 4288aaacfSAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5288aaacfSAlexey Brodkin */ 6288aaacfSAlexey Brodkin 7288aaacfSAlexey Brodkin #ifndef __ASM_ARC_CACHE_H 8288aaacfSAlexey Brodkin #define __ASM_ARC_CACHE_H 9288aaacfSAlexey Brodkin 10288aaacfSAlexey Brodkin #include <config.h> 11288aaacfSAlexey Brodkin 12*379b3280SAlexey Brodkin /* 13*379b3280SAlexey Brodkin * As of today we may handle any L1 cache line length right in software. 14*379b3280SAlexey Brodkin * For that essentially cache line length is a variable not constant. 15*379b3280SAlexey Brodkin * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length 16*379b3280SAlexey Brodkin * that may exist in either L1 or L2 (AKA SLC) caches on ARC. 17*379b3280SAlexey Brodkin */ 18288aaacfSAlexey Brodkin #define ARCH_DMA_MINALIGN 128 19288aaacfSAlexey Brodkin 20f13606b7SAlexey Brodkin #if defined(ARC_MMU_ABSENT) 21f13606b7SAlexey Brodkin #define CONFIG_ARC_MMU_VER 0 22f13606b7SAlexey Brodkin #elif defined(CONFIG_ARC_MMU_V2) 23812980bdSAlexey Brodkin #define CONFIG_ARC_MMU_VER 2 24812980bdSAlexey Brodkin #elif defined(CONFIG_ARC_MMU_V3) 25812980bdSAlexey Brodkin #define CONFIG_ARC_MMU_VER 3 26f13606b7SAlexey Brodkin #elif defined(CONFIG_ARC_MMU_V4) 27f13606b7SAlexey Brodkin #define CONFIG_ARC_MMU_VER 4 28812980bdSAlexey Brodkin #endif 29812980bdSAlexey Brodkin 306eb15e50SAlexey Brodkin #ifndef __ASSEMBLY__ 316eb15e50SAlexey Brodkin 32ef639e6fSAlexey Brodkin void cache_init(void); 336eb15e50SAlexey Brodkin 346eb15e50SAlexey Brodkin #endif /* __ASSEMBLY__ */ 356eb15e50SAlexey Brodkin 36288aaacfSAlexey Brodkin #endif /* __ASM_ARC_CACHE_H */ 37