xref: /rk3399_rockchip-uboot/arch/arc/dts/nsim.dts (revision 7c760f6021b7a7a37f8a4b8741ce032bb0afc620)
1cc8be222SAlexey Brodkin/*
2cc8be222SAlexey Brodkin * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
3cc8be222SAlexey Brodkin *
4cc8be222SAlexey Brodkin * SPDX-License-Identifier:	GPL-2.0+
5cc8be222SAlexey Brodkin */
6cc8be222SAlexey Brodkin/dts-v1/;
7cc8be222SAlexey Brodkin
8cc8be222SAlexey Brodkin#include "skeleton.dtsi"
9cc8be222SAlexey Brodkin
10cc8be222SAlexey Brodkin/ {
11cc8be222SAlexey Brodkin	aliases {
12cc8be222SAlexey Brodkin		console = &arcuart0;
13cc8be222SAlexey Brodkin	};
14cc8be222SAlexey Brodkin
15*7c760f60SVlad Zakharov	cpu_card {
16*7c760f60SVlad Zakharov		core_clk: core_clk {
17*7c760f60SVlad Zakharov			#clock-cells = <0>;
18*7c760f60SVlad Zakharov			compatible = "fixed-clock";
19*7c760f60SVlad Zakharov			clock-frequency = <70000000>;
20*7c760f60SVlad Zakharov			u-boot,dm-pre-reloc;
21*7c760f60SVlad Zakharov		};
22*7c760f60SVlad Zakharov	};
23*7c760f60SVlad Zakharov
24cc8be222SAlexey Brodkin	arcuart0: serial@0xc0fc1000 {
25cc8be222SAlexey Brodkin		compatible = "snps,arc-uart";
26cc8be222SAlexey Brodkin		reg = <0xc0fc1000 0x100>;
27*7c760f60SVlad Zakharov		clock-frequency = <70000000>;
28cc8be222SAlexey Brodkin	};
29cc8be222SAlexey Brodkin
30cc8be222SAlexey Brodkin};
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