1dd84058dSMasahiro Yamadamenu "ARC architecture" 2dd84058dSMasahiro Yamada depends on ARC 3dd84058dSMasahiro Yamada 4dd84058dSMasahiro Yamadaconfig SYS_ARCH 5dd84058dSMasahiro Yamada default "arc" 6dd84058dSMasahiro Yamada 7e20bcb04SAlexey Brodkinconfig SYS_CPU 8fdff2370SAlexey Brodkin default "arcv1" 9e20bcb04SAlexey Brodkin 10dd84058dSMasahiro Yamadachoice 11812980bdSAlexey Brodkin prompt "CPU selection" 12812980bdSAlexey Brodkin default CPU_ARC770D 13812980bdSAlexey Brodkin 14812980bdSAlexey Brodkinconfig CPU_ARC750D 15812980bdSAlexey Brodkin bool "ARC 750D" 16812980bdSAlexey Brodkin select ARC_MMU_V2 17812980bdSAlexey Brodkin help 18812980bdSAlexey Brodkin Choose this option to build an U-Boot for ARC750D CPU. 19812980bdSAlexey Brodkin 20812980bdSAlexey Brodkinconfig CPU_ARC770D 21812980bdSAlexey Brodkin bool "ARC 770D" 22812980bdSAlexey Brodkin select ARC_MMU_V3 23812980bdSAlexey Brodkin help 24812980bdSAlexey Brodkin Choose this option to build an U-Boot for ARC770D CPU. 25812980bdSAlexey Brodkin 26812980bdSAlexey Brodkinendchoice 27812980bdSAlexey Brodkin 28812980bdSAlexey Brodkinchoice 29812980bdSAlexey Brodkin prompt "MMU Version" 30812980bdSAlexey Brodkin default ARC_MMU_V3 if CPU_ARC770D 31812980bdSAlexey Brodkin default ARC_MMU_V2 if CPU_ARC750D 32812980bdSAlexey Brodkin 33812980bdSAlexey Brodkinconfig ARC_MMU_V2 34812980bdSAlexey Brodkin bool "MMU v2" 35812980bdSAlexey Brodkin depends on CPU_ARC750D 36812980bdSAlexey Brodkin help 37812980bdSAlexey Brodkin Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 38812980bdSAlexey Brodkin when 2 D-TLB and 1 I-TLB entries index into same 2way set. 39812980bdSAlexey Brodkin 40812980bdSAlexey Brodkinconfig ARC_MMU_V3 41812980bdSAlexey Brodkin bool "MMU v3" 42812980bdSAlexey Brodkin depends on CPU_ARC770D 43812980bdSAlexey Brodkin help 44812980bdSAlexey Brodkin Introduced with ARC700 4.10: New Features 45812980bdSAlexey Brodkin Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 46812980bdSAlexey Brodkin Shared Address Spaces (SASID) 47812980bdSAlexey Brodkin 48812980bdSAlexey Brodkinendchoice 49812980bdSAlexey Brodkin 50*205e7a7bSAlexey Brodkinconfig SYS_ICACHE_OFF 51*205e7a7bSAlexey Brodkin bool "Do not use Instruction Cache" 52*205e7a7bSAlexey Brodkin default n 53*205e7a7bSAlexey Brodkin 54*205e7a7bSAlexey Brodkinconfig SYS_DCACHE_OFF 55*205e7a7bSAlexey Brodkin bool "Do not use Data Cache" 56*205e7a7bSAlexey Brodkin default n 57*205e7a7bSAlexey Brodkin 58*205e7a7bSAlexey Brodkinconfig ARC_CACHE_LINE_SHIFT 59*205e7a7bSAlexey Brodkin int "Cache Line Length (as power of 2)" 60*205e7a7bSAlexey Brodkin range 5 7 61*205e7a7bSAlexey Brodkin default "6" 62*205e7a7bSAlexey Brodkin depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF 63*205e7a7bSAlexey Brodkin help 64*205e7a7bSAlexey Brodkin Starting with ARC700 4.9, Cache line length is configurable, 65*205e7a7bSAlexey Brodkin This option specifies "N", with Line-len = 2 power N 66*205e7a7bSAlexey Brodkin So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 67*205e7a7bSAlexey Brodkin Linux only supports same line lengths for I and D caches. 68*205e7a7bSAlexey Brodkin 69812980bdSAlexey Brodkinchoice 70dd84058dSMasahiro Yamada prompt "Target select" 71dd84058dSMasahiro Yamada 72dd84058dSMasahiro Yamadaconfig TARGET_TB100 73dd84058dSMasahiro Yamada bool "Support tb100" 74dd84058dSMasahiro Yamada 75dd84058dSMasahiro Yamadaconfig TARGET_ARCANGEL4 76dd84058dSMasahiro Yamada bool "Support arcangel4" 77dd84058dSMasahiro Yamada 78dd84058dSMasahiro Yamadaconfig TARGET_ARCANGEL4_BE 79dd84058dSMasahiro Yamada bool "Support arcangel4-be" 80dd84058dSMasahiro Yamada 81dd84058dSMasahiro Yamadaconfig TARGET_AXS101 82dd84058dSMasahiro Yamada bool "Support axs101" 83dd84058dSMasahiro Yamada 84dd84058dSMasahiro Yamadaendchoice 85dd84058dSMasahiro Yamada 86dd84058dSMasahiro Yamadasource "board/abilis/tb100/Kconfig" 87dd84058dSMasahiro Yamadasource "board/synopsys/Kconfig" 88dd84058dSMasahiro Yamadasource "board/synopsys/axs101/Kconfig" 89dd84058dSMasahiro Yamada 90dd84058dSMasahiro Yamadaendmenu 91