1bdd2596dSAchin Gupta /* 2*9944f557SDaniel Boulby * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3bdd2596dSAchin Gupta * 4bdd2596dSAchin Gupta * SPDX-License-Identifier: BSD-3-Clause 5bdd2596dSAchin Gupta */ 6bdd2596dSAchin Gupta 7bdd2596dSAchin Gupta #ifndef SPMD_PRIVATE_H 8bdd2596dSAchin Gupta #define SPMD_PRIVATE_H 9bdd2596dSAchin Gupta 10bdd2596dSAchin Gupta #include <context.h> 11bdd2596dSAchin Gupta 12bdd2596dSAchin Gupta /******************************************************************************* 13bdd2596dSAchin Gupta * Constants that allow assembler code to preserve callee-saved registers of the 14bdd2596dSAchin Gupta * C runtime context while performing a security state switch. 15bdd2596dSAchin Gupta ******************************************************************************/ 16bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X19 0x0 17bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X20 0x8 18bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X21 0x10 19bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X22 0x18 20bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X23 0x20 21bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X24 0x28 22bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X25 0x30 23bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X26 0x38 24bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X27 0x40 25bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X28 0x48 26bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X29 0x50 27bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X30 0x58 28bdd2596dSAchin Gupta 29bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_SIZE 0x60 30bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_ENTRIES (SPMD_C_RT_CTX_SIZE >> DWORD_SHIFT) 31bdd2596dSAchin Gupta 32bdd2596dSAchin Gupta #ifndef __ASSEMBLER__ 33bdd2596dSAchin Gupta #include <stdint.h> 34a334c4e6SOlivier Deprez #include <lib/psci/psci_lib.h> 35a334c4e6SOlivier Deprez #include <plat/common/platform.h> 36a334c4e6SOlivier Deprez #include <services/ffa_svc.h> 37bdd2596dSAchin Gupta 38bdd2596dSAchin Gupta typedef enum spmc_state { 39bdd2596dSAchin Gupta SPMC_STATE_RESET = 0, 409dcf63ddSOlivier Deprez SPMC_STATE_OFF, 419dcf63ddSOlivier Deprez SPMC_STATE_ON_PENDING, 429dcf63ddSOlivier Deprez SPMC_STATE_ON 43bdd2596dSAchin Gupta } spmc_state_t; 44bdd2596dSAchin Gupta 45bdd2596dSAchin Gupta /* 46bdd2596dSAchin Gupta * Data structure used by the SPM dispatcher (SPMD) in EL3 to track context of 47bdd2596dSAchin Gupta * the SPM core (SPMC) at the next lower EL. 48bdd2596dSAchin Gupta */ 49bdd2596dSAchin Gupta typedef struct spmd_spm_core_context { 50bdd2596dSAchin Gupta uint64_t c_rt_ctx; 51bdd2596dSAchin Gupta cpu_context_t cpu_ctx; 52bdd2596dSAchin Gupta spmc_state_t state; 538cb99c3fSOlivier Deprez bool secure_interrupt_ongoing; 54bdd2596dSAchin Gupta } spmd_spm_core_context_t; 55bdd2596dSAchin Gupta 56bdd2596dSAchin Gupta /* 57662af36dSJ-Alves * Reserve ID for NS physical FFA Endpoint. 58ac03ac5eSMax Shvetsov */ 59662af36dSJ-Alves #define FFA_NS_ENDPOINT_ID U(0) 60ac03ac5eSMax Shvetsov 61c2901419SOlivier Deprez /* Mask and shift to check valid secure FF-A Endpoint ID. */ 6252696946SOlivier Deprez #define SPMC_SECURE_ID_MASK U(1) 6352696946SOlivier Deprez #define SPMC_SECURE_ID_SHIFT U(15) 64ac03ac5eSMax Shvetsov 65c2901419SOlivier Deprez #define SPMD_DIRECT_MSG_ENDPOINT_ID U(FFA_ENDPOINT_ID_MAX - 1) 66c2901419SOlivier Deprez 67*9944f557SDaniel Boulby /* Define SPMD target function IDs for framework messages to the SPMC */ 68*9944f557SDaniel Boulby #define SPMD_FWK_MSG_BIT BIT(31) 69*9944f557SDaniel Boulby #define SPMD_FWK_MSG_PSCI U(0) 70*9944f557SDaniel Boulby #define SPMD_FWK_MSG_FFA_VERSION_REQ U(0x8) 71*9944f557SDaniel Boulby #define SPMD_FWK_MSG_FFA_VERSION_RESP U(0x9) 72*9944f557SDaniel Boulby 73*9944f557SDaniel Boulby /* Function to build SPMD to SPMC message */ 74*9944f557SDaniel Boulby void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target, 75*9944f557SDaniel Boulby unsigned long long message); 76*9944f557SDaniel Boulby 7752696946SOlivier Deprez /* Functions used to enter/exit SPMC synchronously */ 78bdd2596dSAchin Gupta uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx); 79bdd2596dSAchin Gupta __dead2 void spmd_spm_core_sync_exit(uint64_t rc); 80bdd2596dSAchin Gupta 81bdd2596dSAchin Gupta /* Assembly helpers */ 82bdd2596dSAchin Gupta uint64_t spmd_spm_core_enter(uint64_t *c_rt_ctx); 83bdd2596dSAchin Gupta void __dead2 spmd_spm_core_exit(uint64_t c_rt_ctx, uint64_t ret); 84bdd2596dSAchin Gupta 85a334c4e6SOlivier Deprez /* SPMD SPD power management handlers */ 86a334c4e6SOlivier Deprez extern const spd_pm_ops_t spmd_pm; 87a334c4e6SOlivier Deprez 88c0267cc9SOlivier Deprez /* SPMC entry point information helper */ 89c0267cc9SOlivier Deprez entry_point_info_t *spmd_spmc_ep_info_get(void); 90c0267cc9SOlivier Deprez 91a92bc73bSOlivier Deprez /* SPMC ID getter */ 92a92bc73bSOlivier Deprez uint16_t spmd_spmc_id_get(void); 93a92bc73bSOlivier Deprez 9402d50bb0SOlivier Deprez /* SPMC context on CPU based on mpidr */ 9502d50bb0SOlivier Deprez spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr); 9602d50bb0SOlivier Deprez 9752696946SOlivier Deprez /* SPMC context on current CPU get helper */ 9852696946SOlivier Deprez spmd_spm_core_context_t *spmd_get_context(void); 9952696946SOlivier Deprez 100cdb49d47SOlivier Deprez int spmd_pm_secondary_ep_register(uintptr_t entry_point); 101f0d743dbSOlivier Deprez bool spmd_check_address_in_binary_image(uint64_t address); 102f0d743dbSOlivier Deprez 103bdd2596dSAchin Gupta #endif /* __ASSEMBLER__ */ 104bdd2596dSAchin Gupta 105bdd2596dSAchin Gupta #endif /* SPMD_PRIVATE_H */ 106