1bdd2596dSAchin Gupta /* 2f0b64e50SMadhukar Pappireddy * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved. 3bdd2596dSAchin Gupta * 4bdd2596dSAchin Gupta * SPDX-License-Identifier: BSD-3-Clause 5bdd2596dSAchin Gupta */ 6bdd2596dSAchin Gupta 7bdd2596dSAchin Gupta #ifndef SPMD_PRIVATE_H 8bdd2596dSAchin Gupta #define SPMD_PRIVATE_H 9bdd2596dSAchin Gupta 10885e2683SClaus Pedersen #include <common/bl_common.h> 11bdd2596dSAchin Gupta #include <context.h> 12bdd2596dSAchin Gupta 13bdd2596dSAchin Gupta /******************************************************************************* 14bdd2596dSAchin Gupta * Constants that allow assembler code to preserve callee-saved registers of the 15bdd2596dSAchin Gupta * C runtime context while performing a security state switch. 16bdd2596dSAchin Gupta ******************************************************************************/ 17bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X19 0x0 18bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X20 0x8 19bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X21 0x10 20bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X22 0x18 21bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X23 0x20 22bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X24 0x28 23bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X25 0x30 24bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X26 0x38 25bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X27 0x40 26bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X28 0x48 27bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X29 0x50 28bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_X30 0x58 29bdd2596dSAchin Gupta 30bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_SIZE 0x60 31bdd2596dSAchin Gupta #define SPMD_C_RT_CTX_ENTRIES (SPMD_C_RT_CTX_SIZE >> DWORD_SHIFT) 32bdd2596dSAchin Gupta 33bdd2596dSAchin Gupta #ifndef __ASSEMBLER__ 34bdd2596dSAchin Gupta #include <stdint.h> 35a334c4e6SOlivier Deprez #include <lib/psci/psci_lib.h> 36a334c4e6SOlivier Deprez #include <plat/common/platform.h> 37a334c4e6SOlivier Deprez #include <services/ffa_svc.h> 38bdd2596dSAchin Gupta 39bdd2596dSAchin Gupta typedef enum spmc_state { 40bdd2596dSAchin Gupta SPMC_STATE_RESET = 0, 419dcf63ddSOlivier Deprez SPMC_STATE_OFF, 429dcf63ddSOlivier Deprez SPMC_STATE_ON_PENDING, 439dcf63ddSOlivier Deprez SPMC_STATE_ON 44bdd2596dSAchin Gupta } spmc_state_t; 45bdd2596dSAchin Gupta 46bdd2596dSAchin Gupta /* 47bdd2596dSAchin Gupta * Data structure used by the SPM dispatcher (SPMD) in EL3 to track context of 48bdd2596dSAchin Gupta * the SPM core (SPMC) at the next lower EL. 49bdd2596dSAchin Gupta */ 50bdd2596dSAchin Gupta typedef struct spmd_spm_core_context { 51bdd2596dSAchin Gupta uint64_t c_rt_ctx; 52bdd2596dSAchin Gupta cpu_context_t cpu_ctx; 53bdd2596dSAchin Gupta spmc_state_t state; 548cb99c3fSOlivier Deprez bool secure_interrupt_ongoing; 5566bdfd6eSRaghu Krishnamurthy #if ENABLE_SPMD_LP 5666bdfd6eSRaghu Krishnamurthy uint8_t spmd_lp_sync_req_ongoing; 5766bdfd6eSRaghu Krishnamurthy #endif 58bdd2596dSAchin Gupta } spmd_spm_core_context_t; 59bdd2596dSAchin Gupta 6066bdfd6eSRaghu Krishnamurthy /* Flags to indicate ongoing requests for SPMD EL3 logical partitions */ 6166bdfd6eSRaghu Krishnamurthy #define SPMD_LP_FFA_DIR_REQ_ONGOING U(0x1) 620b850e9eSRaghu Krishnamurthy #define SPMD_LP_FFA_INFO_GET_REG_ONGOING U(0x2) 6366bdfd6eSRaghu Krishnamurthy 64bdd2596dSAchin Gupta /* 65662af36dSJ-Alves * Reserve ID for NS physical FFA Endpoint. 66ac03ac5eSMax Shvetsov */ 67662af36dSJ-Alves #define FFA_NS_ENDPOINT_ID U(0) 68ac03ac5eSMax Shvetsov 699944f557SDaniel Boulby /* Define SPMD target function IDs for framework messages to the SPMC */ 709944f557SDaniel Boulby #define SPMD_FWK_MSG_FFA_VERSION_REQ U(0x8) 719944f557SDaniel Boulby #define SPMD_FWK_MSG_FFA_VERSION_RESP U(0x9) 729944f557SDaniel Boulby 739944f557SDaniel Boulby /* Function to build SPMD to SPMC message */ 749944f557SDaniel Boulby void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target, 759944f557SDaniel Boulby unsigned long long message); 769944f557SDaniel Boulby 7752696946SOlivier Deprez /* Functions used to enter/exit SPMC synchronously */ 78bdd2596dSAchin Gupta uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx); 79bdd2596dSAchin Gupta __dead2 void spmd_spm_core_sync_exit(uint64_t rc); 80bdd2596dSAchin Gupta 81bdd2596dSAchin Gupta /* Assembly helpers */ 82bdd2596dSAchin Gupta uint64_t spmd_spm_core_enter(uint64_t *c_rt_ctx); 83bdd2596dSAchin Gupta void __dead2 spmd_spm_core_exit(uint64_t c_rt_ctx, uint64_t ret); 84bdd2596dSAchin Gupta 85a334c4e6SOlivier Deprez /* SPMD SPD power management handlers */ 86a334c4e6SOlivier Deprez extern const spd_pm_ops_t spmd_pm; 87a334c4e6SOlivier Deprez 88c0267cc9SOlivier Deprez /* SPMC entry point information helper */ 89c0267cc9SOlivier Deprez entry_point_info_t *spmd_spmc_ep_info_get(void); 90c0267cc9SOlivier Deprez 91a92bc73bSOlivier Deprez /* SPMC ID getter */ 92a92bc73bSOlivier Deprez uint16_t spmd_spmc_id_get(void); 93a92bc73bSOlivier Deprez 9402d50bb0SOlivier Deprez /* SPMC context on CPU based on mpidr */ 9502d50bb0SOlivier Deprez spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr); 9602d50bb0SOlivier Deprez 9752696946SOlivier Deprez /* SPMC context on current CPU get helper */ 9852696946SOlivier Deprez spmd_spm_core_context_t *spmd_get_context(void); 9952696946SOlivier Deprez 100cdb49d47SOlivier Deprez int spmd_pm_secondary_ep_register(uintptr_t entry_point); 101f0d743dbSOlivier Deprez bool spmd_check_address_in_binary_image(uint64_t address); 102f0d743dbSOlivier Deprez 103f0b64e50SMadhukar Pappireddy /* 104f0b64e50SMadhukar Pappireddy * Platform hook in EL3 firmware to handle for Group0 secure interrupt. 105f0b64e50SMadhukar Pappireddy * Return values: 106f0b64e50SMadhukar Pappireddy * 0 = success 107f0b64e50SMadhukar Pappireddy * otherwise it returns a negative value 108f0b64e50SMadhukar Pappireddy */ 109f0b64e50SMadhukar Pappireddy int plat_spmd_handle_group0_interrupt(uint32_t id); 110*95f7f6d8SRaghu Krishnamurthy 111*95f7f6d8SRaghu Krishnamurthy uint64_t spmd_ffa_error_return(void *handle, int error_code); 112*95f7f6d8SRaghu Krishnamurthy 113bdd2596dSAchin Gupta #endif /* __ASSEMBLER__ */ 114bdd2596dSAchin Gupta 115bdd2596dSAchin Gupta #endif /* SPMD_PRIVATE_H */ 116