1 /* 2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch/aarch64/arch_features.h> 15 #include <bl31/bl31.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/debug.h> 18 #include <common/runtime_svc.h> 19 #include <common/tbbr/tbbr_img_def.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/fconf/fconf.h> 22 #include <lib/fconf/fconf_dyn_cfg_getter.h> 23 #include <lib/smccc.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/common_def.h> 28 #include <plat/common/platform.h> 29 #include <platform_def.h> 30 #include <services/el3_spmd_logical_sp.h> 31 #include <services/ffa_svc.h> 32 #include <services/spmc_svc.h> 33 #include <services/spmd_svc.h> 34 #include <smccc_helpers.h> 35 #include "spmd_private.h" 36 37 /******************************************************************************* 38 * SPM Core context information. 39 ******************************************************************************/ 40 static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT]; 41 42 /******************************************************************************* 43 * SPM Core attribute information is read from its manifest if the SPMC is not 44 * at EL3. Else, it is populated from the SPMC directly. 45 ******************************************************************************/ 46 static spmc_manifest_attribute_t spmc_attrs; 47 48 /******************************************************************************* 49 * SPM Core entry point information. Discovered on the primary core and reused 50 * on secondary cores. 51 ******************************************************************************/ 52 static entry_point_info_t *spmc_ep_info; 53 54 /******************************************************************************* 55 * SPM Core context on current CPU get helper. 56 ******************************************************************************/ 57 spmd_spm_core_context_t *spmd_get_context(void) 58 { 59 return &spm_core_context[plat_my_core_pos()]; 60 } 61 62 /******************************************************************************* 63 * SPM Core ID getter. 64 ******************************************************************************/ 65 uint16_t spmd_spmc_id_get(void) 66 { 67 return spmc_attrs.spmc_id; 68 } 69 70 /******************************************************************************* 71 * Static function declaration. 72 ******************************************************************************/ 73 static int32_t spmd_init(void); 74 static int spmd_spmc_init(void *pm_addr); 75 76 static uint64_t spmd_smc_forward(uint32_t smc_fid, 77 bool secure_origin, 78 uint64_t x1, 79 uint64_t x2, 80 uint64_t x3, 81 uint64_t x4, 82 void *cookie, 83 void *handle, 84 uint64_t flags); 85 86 /****************************************************************************** 87 * Builds an SPMD to SPMC direct message request. 88 *****************************************************************************/ 89 void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target_func, 90 unsigned long long message) 91 { 92 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); 93 write_ctx_reg(gpregs, CTX_GPREG_X1, 94 (SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) | 95 spmd_spmc_id_get()); 96 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); 97 write_ctx_reg(gpregs, CTX_GPREG_X3, message); 98 99 /* Zero out x4-x7 for the direct request emitted towards the SPMC. */ 100 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 101 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 102 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 103 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 104 } 105 106 107 /******************************************************************************* 108 * This function takes an SPMC context pointer and performs a synchronous 109 * SPMC entry. 110 ******************************************************************************/ 111 uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx) 112 { 113 uint64_t rc; 114 115 assert(spmc_ctx != NULL); 116 117 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE); 118 119 /* Restore the context assigned above */ 120 #if SPMD_SPM_AT_SEL2 121 cm_el2_sysregs_context_restore(SECURE); 122 #else 123 cm_el1_sysregs_context_restore(SECURE); 124 #endif 125 cm_set_next_eret_context(SECURE); 126 127 /* Enter SPMC */ 128 rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx); 129 130 /* Save secure state */ 131 #if SPMD_SPM_AT_SEL2 132 cm_el2_sysregs_context_save(SECURE); 133 #else 134 cm_el1_sysregs_context_save(SECURE); 135 #endif 136 137 return rc; 138 } 139 140 /******************************************************************************* 141 * This function returns to the place where spmd_spm_core_sync_entry() was 142 * called originally. 143 ******************************************************************************/ 144 __dead2 void spmd_spm_core_sync_exit(uint64_t rc) 145 { 146 spmd_spm_core_context_t *ctx = spmd_get_context(); 147 148 /* Get current CPU context from SPMC context */ 149 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx)); 150 151 /* 152 * The SPMD must have initiated the original request through a 153 * synchronous entry into SPMC. Jump back to the original C runtime 154 * context with the value of rc in x0; 155 */ 156 spmd_spm_core_exit(ctx->c_rt_ctx, rc); 157 158 panic(); 159 } 160 161 /******************************************************************************* 162 * Jump to the SPM Core for the first time. 163 ******************************************************************************/ 164 static int32_t spmd_init(void) 165 { 166 spmd_spm_core_context_t *ctx = spmd_get_context(); 167 uint64_t rc; 168 169 VERBOSE("SPM Core init start.\n"); 170 171 /* Primary boot core enters the SPMC for initialization. */ 172 ctx->state = SPMC_STATE_ON_PENDING; 173 174 rc = spmd_spm_core_sync_entry(ctx); 175 if (rc != 0ULL) { 176 ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc); 177 return 0; 178 } 179 180 ctx->state = SPMC_STATE_ON; 181 182 VERBOSE("SPM Core init end.\n"); 183 184 spmd_logical_sp_set_spmc_initialized(); 185 rc = spmd_logical_sp_init(); 186 if (rc != 0) { 187 WARN("SPMD Logical partitions failed init.\n"); 188 } 189 190 return 1; 191 } 192 193 /******************************************************************************* 194 * spmd_secure_interrupt_handler 195 * Enter the SPMC for further handling of the secure interrupt by the SPMC 196 * itself or a Secure Partition. 197 ******************************************************************************/ 198 static uint64_t spmd_secure_interrupt_handler(uint32_t id, 199 uint32_t flags, 200 void *handle, 201 void *cookie) 202 { 203 spmd_spm_core_context_t *ctx = spmd_get_context(); 204 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 205 int64_t rc; 206 207 /* Sanity check the security state when the exception was generated */ 208 assert(get_interrupt_src_ss(flags) == NON_SECURE); 209 210 /* Sanity check the pointer to this cpu's context */ 211 assert(handle == cm_get_context(NON_SECURE)); 212 213 /* Save the non-secure context before entering SPMC */ 214 #if SPMD_SPM_AT_SEL2 215 cm_el2_sysregs_context_save(NON_SECURE); 216 #else 217 cm_el1_sysregs_context_save(NON_SECURE); 218 219 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 220 /* 221 * The hint bit denoting absence of SVE live state is effectively false 222 * in this scenario where execution was trapped to EL3 due to FIQ. 223 */ 224 simd_ctx_save(NON_SECURE, false); 225 #endif 226 #endif 227 228 /* Convey the event to the SPMC through the FFA_INTERRUPT interface. */ 229 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); 230 write_ctx_reg(gpregs, CTX_GPREG_X1, 0); 231 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); 232 write_ctx_reg(gpregs, CTX_GPREG_X3, 0); 233 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 234 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 235 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 236 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 237 238 /* Mark current core as handling a secure interrupt. */ 239 ctx->secure_interrupt_ongoing = true; 240 241 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 242 simd_ctx_restore(SECURE); 243 #endif 244 rc = spmd_spm_core_sync_entry(ctx); 245 246 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 247 simd_ctx_save(SECURE, false); 248 #endif 249 if (rc != 0ULL) { 250 ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, plat_my_core_pos()); 251 } 252 253 ctx->secure_interrupt_ongoing = false; 254 255 #if SPMD_SPM_AT_SEL2 256 cm_el2_sysregs_context_restore(NON_SECURE); 257 #else 258 cm_el1_sysregs_context_restore(NON_SECURE); 259 260 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 261 simd_ctx_restore(NON_SECURE); 262 #endif 263 #endif 264 cm_set_next_eret_context(NON_SECURE); 265 266 SMC_RET0(&ctx->cpu_ctx); 267 } 268 269 #if (EL3_EXCEPTION_HANDLING == 0) 270 /******************************************************************************* 271 * spmd_group0_interrupt_handler_nwd 272 * Group0 secure interrupt in the normal world are trapped to EL3. Delegate the 273 * handling of the interrupt to the platform handler, and return only upon 274 * successfully handling the Group0 interrupt. 275 ******************************************************************************/ 276 static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id, 277 uint32_t flags, 278 void *handle, 279 void *cookie) 280 { 281 uint32_t intid; 282 283 /* Sanity check the security state when the exception was generated. */ 284 assert(get_interrupt_src_ss(flags) == NON_SECURE); 285 286 /* Sanity check the pointer to this cpu's context. */ 287 assert(handle == cm_get_context(NON_SECURE)); 288 289 assert(id == INTR_ID_UNAVAILABLE); 290 291 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 292 293 intid = plat_ic_acknowledge_interrupt(); 294 295 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 296 ERROR("Group0 interrupt %u not handled\n", intid); 297 panic(); 298 } 299 300 /* Deactivate the corresponding Group0 interrupt. */ 301 plat_ic_end_of_interrupt(intid); 302 303 return 0U; 304 } 305 #endif 306 307 /******************************************************************************* 308 * spmd_handle_group0_intr_swd 309 * SPMC delegates handling of Group0 secure interrupt to EL3 firmware using 310 * FFA_EL3_INTR_HANDLE SMC call. Further, SPMD delegates the handling of the 311 * interrupt to the platform handler, and returns only upon successfully 312 * handling the Group0 interrupt. 313 ******************************************************************************/ 314 static uint64_t spmd_handle_group0_intr_swd(void *handle) 315 { 316 uint32_t intid; 317 318 /* Sanity check the pointer to this cpu's context */ 319 assert(handle == cm_get_context(SECURE)); 320 321 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 322 323 intid = plat_ic_acknowledge_interrupt(); 324 325 /* 326 * TODO: Currently due to a limitation in SPMD implementation, the 327 * platform handler is expected to not delegate handling to NWd while 328 * processing Group0 secure interrupt. 329 */ 330 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 331 /* Group0 interrupt was not handled by the platform. */ 332 ERROR("Group0 interrupt %u not handled\n", intid); 333 panic(); 334 } 335 336 /* Deactivate the corresponding Group0 interrupt. */ 337 plat_ic_end_of_interrupt(intid); 338 339 /* Return success. */ 340 SMC_RET8(handle, FFA_SUCCESS_SMC32, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 341 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 342 FFA_PARAM_MBZ); 343 } 344 345 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 346 static int spmd_dynamic_map_mem(uintptr_t base_addr, size_t size, 347 unsigned int attr, uintptr_t *align_addr, 348 size_t *align_size) 349 { 350 uintptr_t base_addr_align; 351 size_t mapped_size_align; 352 int rc; 353 354 /* Page aligned address and size if necessary */ 355 base_addr_align = page_align(base_addr, DOWN); 356 mapped_size_align = page_align(size, UP); 357 358 if ((base_addr != base_addr_align) && 359 (size == mapped_size_align)) { 360 mapped_size_align += PAGE_SIZE; 361 } 362 363 /* 364 * Map dynamically given region with its aligned base address and 365 * size 366 */ 367 rc = mmap_add_dynamic_region((unsigned long long)base_addr_align, 368 base_addr_align, 369 mapped_size_align, 370 attr); 371 if (rc == 0) { 372 *align_addr = base_addr_align; 373 *align_size = mapped_size_align; 374 } 375 376 return rc; 377 } 378 379 static void spmd_do_sec_cpy(uintptr_t root_base_addr, uintptr_t sec_base_addr, 380 size_t size) 381 { 382 uintptr_t root_base_addr_align, sec_base_addr_align; 383 size_t root_mapped_size_align, sec_mapped_size_align; 384 int rc; 385 386 assert(root_base_addr != 0UL); 387 assert(sec_base_addr != 0UL); 388 assert(size != 0UL); 389 390 /* Map the memory with required attributes */ 391 rc = spmd_dynamic_map_mem(root_base_addr, size, MT_RO_DATA | MT_ROOT, 392 &root_base_addr_align, 393 &root_mapped_size_align); 394 if (rc != 0) { 395 ERROR("%s %s %lu (%d)\n", "Error while mapping", "root region", 396 root_base_addr, rc); 397 panic(); 398 } 399 400 rc = spmd_dynamic_map_mem(sec_base_addr, size, MT_RW_DATA | MT_SECURE, 401 &sec_base_addr_align, &sec_mapped_size_align); 402 if (rc != 0) { 403 ERROR("%s %s %lu (%d)\n", "Error while mapping", 404 "secure region", sec_base_addr, rc); 405 panic(); 406 } 407 408 /* Do copy operation */ 409 (void)memcpy((void *)sec_base_addr, (void *)root_base_addr, size); 410 411 /* Unmap root memory region */ 412 rc = mmap_remove_dynamic_region(root_base_addr_align, 413 root_mapped_size_align); 414 if (rc != 0) { 415 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 416 "root region", root_base_addr_align, rc); 417 panic(); 418 } 419 420 /* Unmap secure memory region */ 421 rc = mmap_remove_dynamic_region(sec_base_addr_align, 422 sec_mapped_size_align); 423 if (rc != 0) { 424 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 425 "secure region", sec_base_addr_align, rc); 426 panic(); 427 } 428 } 429 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 430 431 /******************************************************************************* 432 * Loads SPMC manifest and inits SPMC. 433 ******************************************************************************/ 434 static int spmd_spmc_init(void *pm_addr) 435 { 436 cpu_context_t *cpu_ctx; 437 unsigned int core_id; 438 uint32_t ep_attr, flags; 439 int rc; 440 const struct dyn_cfg_dtb_info_t *image_info __unused; 441 442 /* Load the SPM Core manifest */ 443 rc = plat_spm_core_manifest_load(&spmc_attrs, pm_addr); 444 if (rc != 0) { 445 WARN("No or invalid SPM Core manifest image provided by BL2\n"); 446 return rc; 447 } 448 449 /* 450 * Ensure that the SPM Core version is compatible with the SPM 451 * Dispatcher version. 452 */ 453 if ((spmc_attrs.major_version != FFA_VERSION_MAJOR) || 454 (spmc_attrs.minor_version > FFA_VERSION_MINOR)) { 455 WARN("Unsupported FFA version (%u.%u)\n", 456 spmc_attrs.major_version, spmc_attrs.minor_version); 457 return -EINVAL; 458 } 459 460 VERBOSE("FFA version (%u.%u)\n", spmc_attrs.major_version, 461 spmc_attrs.minor_version); 462 463 VERBOSE("SPM Core run time EL%x.\n", 464 SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1); 465 466 /* Validate the SPMC ID, Ensure high bit is set */ 467 if (((spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) & 468 SPMC_SECURE_ID_MASK) == 0U) { 469 WARN("Invalid ID (0x%x) for SPMC.\n", spmc_attrs.spmc_id); 470 return -EINVAL; 471 } 472 473 /* Validate the SPM Core execution state */ 474 if ((spmc_attrs.exec_state != MODE_RW_64) && 475 (spmc_attrs.exec_state != MODE_RW_32)) { 476 WARN("Unsupported %s%x.\n", "SPM Core execution state 0x", 477 spmc_attrs.exec_state); 478 return -EINVAL; 479 } 480 481 VERBOSE("%s%x.\n", "SPM Core execution state 0x", 482 spmc_attrs.exec_state); 483 484 #if SPMD_SPM_AT_SEL2 485 /* Ensure manifest has not requested AArch32 state in S-EL2 */ 486 if (spmc_attrs.exec_state == MODE_RW_32) { 487 WARN("AArch32 state at S-EL2 is not supported.\n"); 488 return -EINVAL; 489 } 490 491 /* 492 * Check if S-EL2 is supported on this system if S-EL2 493 * is required for SPM 494 */ 495 if (!is_feat_sel2_supported()) { 496 WARN("SPM Core run time S-EL2 is not supported.\n"); 497 return -EINVAL; 498 } 499 #endif /* SPMD_SPM_AT_SEL2 */ 500 501 /* Initialise an entrypoint to set up the CPU context */ 502 ep_attr = SECURE | EP_ST_ENABLE; 503 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0ULL) { 504 ep_attr |= EP_EE_BIG; 505 } 506 507 SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr); 508 509 /* 510 * Populate SPSR for SPM Core based upon validated parameters from the 511 * manifest. 512 */ 513 if (spmc_attrs.exec_state == MODE_RW_32) { 514 spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 515 SPSR_E_LITTLE, 516 DAIF_FIQ_BIT | 517 DAIF_IRQ_BIT | 518 DAIF_ABT_BIT); 519 } else { 520 521 #if SPMD_SPM_AT_SEL2 522 static const uint32_t runtime_el = MODE_EL2; 523 #else 524 static const uint32_t runtime_el = MODE_EL1; 525 #endif 526 spmc_ep_info->spsr = SPSR_64(runtime_el, 527 MODE_SP_ELX, 528 DISABLE_ALL_EXCEPTIONS); 529 } 530 531 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 532 image_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TOS_FW_CONFIG_ID); 533 assert(image_info != NULL); 534 535 if ((image_info->config_addr == 0UL) || 536 (image_info->secondary_config_addr == 0UL) || 537 (image_info->config_max_size == 0UL)) { 538 return -EINVAL; 539 } 540 541 /* Copy manifest from root->secure region */ 542 spmd_do_sec_cpy(image_info->config_addr, 543 image_info->secondary_config_addr, 544 image_info->config_max_size); 545 546 /* Update ep info of BL32 */ 547 assert(spmc_ep_info != NULL); 548 spmc_ep_info->args.arg0 = image_info->secondary_config_addr; 549 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 550 551 /* Set an initial SPMC context state for all cores. */ 552 for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) { 553 spm_core_context[core_id].state = SPMC_STATE_OFF; 554 555 /* Setup an initial cpu context for the SPMC. */ 556 cpu_ctx = &spm_core_context[core_id].cpu_ctx; 557 cm_setup_context(cpu_ctx, spmc_ep_info); 558 559 /* 560 * Pass the core linear ID to the SPMC through x4. 561 * (TF-A implementation defined behavior helping 562 * a legacy TOS migration to adopt FF-A). 563 */ 564 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); 565 } 566 567 /* Register power management hooks with PSCI */ 568 psci_register_spd_pm_hook(&spmd_pm); 569 570 /* Register init function for deferred init. */ 571 bl31_register_bl32_init(&spmd_init); 572 573 INFO("SPM Core setup done.\n"); 574 575 /* 576 * Register an interrupt handler routing secure interrupts to SPMD 577 * while the NWd is running. 578 */ 579 flags = 0; 580 set_interrupt_rm_flag(flags, NON_SECURE); 581 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 582 spmd_secure_interrupt_handler, 583 flags); 584 if (rc != 0) { 585 panic(); 586 } 587 588 /* 589 * Permit configurations where the SPM resides at S-EL1/2 and upon a 590 * Group0 interrupt triggering while the normal world runs, the 591 * interrupt is routed either through the EHF or directly to the SPMD: 592 * 593 * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD 594 * for handling by spmd_group0_interrupt_handler_nwd. 595 * 596 * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF. 597 * 598 */ 599 #if (EL3_EXCEPTION_HANDLING == 0) 600 /* 601 * If EL3 interrupts are supported by the platform, register an 602 * interrupt handler routing Group0 interrupts to SPMD while the NWd is 603 * running. 604 */ 605 if (plat_ic_has_interrupt_type(INTR_TYPE_EL3)) { 606 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 607 spmd_group0_interrupt_handler_nwd, 608 flags); 609 if (rc != 0) { 610 panic(); 611 } 612 } 613 #endif 614 615 return 0; 616 } 617 618 /******************************************************************************* 619 * Initialize context of SPM Core. 620 ******************************************************************************/ 621 int spmd_setup(void) 622 { 623 int rc; 624 void *spmc_manifest; 625 626 /* 627 * If the SPMC is at EL3, then just initialise it directly. The 628 * shenanigans of when it is at a lower EL are not needed. 629 */ 630 if (is_spmc_at_el3()) { 631 /* Allow the SPMC to populate its attributes directly. */ 632 spmc_populate_attrs(&spmc_attrs); 633 634 rc = spmc_setup(); 635 if (rc != 0) { 636 WARN("SPMC initialisation failed 0x%x.\n", rc); 637 } 638 return 0; 639 } 640 641 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 642 if (spmc_ep_info == NULL) { 643 WARN("No SPM Core image provided by BL2 boot loader.\n"); 644 return 0; 645 } 646 647 /* Under no circumstances will this parameter be 0 */ 648 assert(spmc_ep_info->pc != 0ULL); 649 650 /* 651 * Check if BL32 ep_info has a reference to 'tos_fw_config'. This will 652 * be used as a manifest for the SPM Core at the next lower EL/mode. 653 */ 654 spmc_manifest = (void *)spmc_ep_info->args.arg0; 655 if (spmc_manifest == NULL) { 656 WARN("Invalid or absent SPM Core manifest.\n"); 657 return 0; 658 } 659 660 /* Load manifest, init SPMC */ 661 rc = spmd_spmc_init(spmc_manifest); 662 if (rc != 0) { 663 WARN("Booting device without SPM initialization.\n"); 664 } 665 666 return 0; 667 } 668 669 /******************************************************************************* 670 * Forward FF-A SMCs to the other security state. 671 ******************************************************************************/ 672 uint64_t spmd_smc_switch_state(uint32_t smc_fid, 673 bool secure_origin, 674 uint64_t x1, 675 uint64_t x2, 676 uint64_t x3, 677 uint64_t x4, 678 void *handle, 679 uint64_t flags) 680 { 681 unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE; 682 unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE; 683 void *ctx_out; 684 685 #if SPMD_SPM_AT_SEL2 686 if ((secure_state_out == SECURE) && (is_sve_hint_set(flags) == true)) { 687 /* 688 * Set the SVE hint bit in x0 and pass to the lower secure EL, 689 * if it was set by the caller. 690 */ 691 smc_fid |= (FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT); 692 } 693 #endif 694 695 /* Save incoming security state */ 696 #if SPMD_SPM_AT_SEL2 697 cm_el2_sysregs_context_save(secure_state_in); 698 #else 699 cm_el1_sysregs_context_save(secure_state_in); 700 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 701 /* Forward the hint bit denoting the absence of SVE live state. */ 702 simd_ctx_save(secure_state_in, (!secure_origin && (is_sve_hint_set(flags) == true))); 703 #endif 704 #endif 705 706 /* Restore outgoing security state */ 707 #if SPMD_SPM_AT_SEL2 708 cm_el2_sysregs_context_restore(secure_state_out); 709 #else 710 cm_el1_sysregs_context_restore(secure_state_out); 711 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 712 simd_ctx_restore(secure_state_out); 713 #endif 714 #endif 715 cm_set_next_eret_context(secure_state_out); 716 717 ctx_out = cm_get_context(secure_state_out); 718 if (smc_fid == FFA_NORMAL_WORLD_RESUME) { 719 SMC_RET0(ctx_out); 720 } 721 722 #if SPMD_SPM_AT_SEL2 723 /* 724 * If SPMC is at SEL2, save additional registers x8-x17, which may 725 * be used in FF-A calls such as FFA_PARTITION_INFO_GET_REGS. 726 * Note that technically, all SPMCs can support this, but this code is 727 * under ifdef to minimize breakage in case other SPMCs do not save 728 * and restore x8-x17. 729 * We also need to pass through these registers since not all FF-A ABIs 730 * modify x8-x17, in which case, SMCCC requires that these registers be 731 * preserved, so the SPMD passes through these registers and expects the 732 * SPMC to save and restore (potentially also modify) them. 733 */ 734 SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4, 735 SMC_GET_GP(handle, CTX_GPREG_X5), 736 SMC_GET_GP(handle, CTX_GPREG_X6), 737 SMC_GET_GP(handle, CTX_GPREG_X7), 738 SMC_GET_GP(handle, CTX_GPREG_X8), 739 SMC_GET_GP(handle, CTX_GPREG_X9), 740 SMC_GET_GP(handle, CTX_GPREG_X10), 741 SMC_GET_GP(handle, CTX_GPREG_X11), 742 SMC_GET_GP(handle, CTX_GPREG_X12), 743 SMC_GET_GP(handle, CTX_GPREG_X13), 744 SMC_GET_GP(handle, CTX_GPREG_X14), 745 SMC_GET_GP(handle, CTX_GPREG_X15), 746 SMC_GET_GP(handle, CTX_GPREG_X16), 747 SMC_GET_GP(handle, CTX_GPREG_X17) 748 ); 749 750 #else 751 SMC_RET8(ctx_out, smc_fid, x1, x2, x3, x4, 752 SMC_GET_GP(handle, CTX_GPREG_X5), 753 SMC_GET_GP(handle, CTX_GPREG_X6), 754 SMC_GET_GP(handle, CTX_GPREG_X7)); 755 #endif 756 } 757 758 /******************************************************************************* 759 * Forward SMCs to the other security state. 760 ******************************************************************************/ 761 static uint64_t spmd_smc_forward(uint32_t smc_fid, 762 bool secure_origin, 763 uint64_t x1, 764 uint64_t x2, 765 uint64_t x3, 766 uint64_t x4, 767 void *cookie, 768 void *handle, 769 uint64_t flags) 770 { 771 if (is_spmc_at_el3() && !secure_origin) { 772 return spmc_smc_handler(smc_fid, secure_origin, x1, x2, x3, x4, 773 cookie, handle, flags); 774 } 775 776 return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2, x3, x4, 777 handle, flags); 778 779 } 780 781 /******************************************************************************* 782 * Return FFA_ERROR with specified error code 783 ******************************************************************************/ 784 uint64_t spmd_ffa_error_return(void *handle, int error_code) 785 { 786 SMC_RET8(handle, (uint32_t) FFA_ERROR, 787 FFA_TARGET_INFO_MBZ, (uint32_t)error_code, 788 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 789 FFA_PARAM_MBZ, FFA_PARAM_MBZ); 790 } 791 792 /******************************************************************************* 793 * spmd_check_address_in_binary_image 794 ******************************************************************************/ 795 bool spmd_check_address_in_binary_image(uint64_t address) 796 { 797 assert(!check_uptr_overflow(spmc_attrs.load_address, spmc_attrs.binary_size)); 798 799 return ((address >= spmc_attrs.load_address) && 800 (address < (spmc_attrs.load_address + spmc_attrs.binary_size))); 801 } 802 803 /****************************************************************************** 804 * spmd_is_spmc_message 805 *****************************************************************************/ 806 static bool spmd_is_spmc_message(unsigned int ep) 807 { 808 if (is_spmc_at_el3()) { 809 return false; 810 } 811 812 return ((ffa_endpoint_destination(ep) == SPMD_DIRECT_MSG_ENDPOINT_ID) 813 && (ffa_endpoint_source(ep) == spmc_attrs.spmc_id)); 814 } 815 816 /******************************************************************************* 817 * This function forwards FF-A SMCs to either the main SPMD handler or the 818 * SPMC at EL3, depending on the origin security state, if enabled. 819 ******************************************************************************/ 820 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid, 821 uint64_t x1, 822 uint64_t x2, 823 uint64_t x3, 824 uint64_t x4, 825 void *cookie, 826 void *handle, 827 uint64_t flags) 828 { 829 if (is_spmc_at_el3()) { 830 /* 831 * If we have an SPMC at EL3 allow handling of the SMC first. 832 * The SPMC will call back through to SPMD handler if required. 833 */ 834 if (is_caller_secure(flags)) { 835 return spmc_smc_handler(smc_fid, 836 is_caller_secure(flags), 837 x1, x2, x3, x4, cookie, 838 handle, flags); 839 } 840 } 841 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 842 handle, flags); 843 } 844 845 /******************************************************************************* 846 * This function handles all SMCs in the range reserved for FFA. Each call is 847 * either forwarded to the other security state or handled by the SPM dispatcher 848 ******************************************************************************/ 849 uint64_t spmd_smc_handler(uint32_t smc_fid, 850 uint64_t x1, 851 uint64_t x2, 852 uint64_t x3, 853 uint64_t x4, 854 void *cookie, 855 void *handle, 856 uint64_t flags) 857 { 858 spmd_spm_core_context_t *ctx = spmd_get_context(); 859 bool secure_origin; 860 int ret; 861 uint32_t input_version; 862 863 /* Determine which security state this SMC originated from */ 864 secure_origin = is_caller_secure(flags); 865 866 VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 867 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n", 868 plat_my_core_pos(), smc_fid, x1, x2, x3, x4, 869 SMC_GET_GP(handle, CTX_GPREG_X5), 870 SMC_GET_GP(handle, CTX_GPREG_X6), 871 SMC_GET_GP(handle, CTX_GPREG_X7)); 872 873 /* 874 * If there is an on-going info regs from EL3 SPMD LP, unconditionally 875 * return, we don't expect any other FF-A ABIs to be called between 876 * calls to FFA_PARTITION_INFO_GET_REGS. 877 */ 878 if (is_spmd_logical_sp_info_regs_req_in_progress(ctx)) { 879 assert(secure_origin); 880 spmd_spm_core_sync_exit(0ULL); 881 } 882 883 switch (smc_fid) { 884 case FFA_ERROR: 885 /* 886 * Check if this is the first invocation of this interface on 887 * this CPU. If so, then indicate that the SPM Core initialised 888 * unsuccessfully. 889 */ 890 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 891 spmd_spm_core_sync_exit(x2); 892 } 893 894 /* 895 * If there was an SPMD logical partition direct request on-going, 896 * return back to the SPMD logical partition so the error can be 897 * consumed. 898 */ 899 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 900 assert(secure_origin); 901 spmd_spm_core_sync_exit(0ULL); 902 } 903 904 return spmd_smc_forward(smc_fid, secure_origin, 905 x1, x2, x3, x4, cookie, 906 handle, flags); 907 break; /* not reached */ 908 909 case FFA_VERSION: 910 input_version = (uint32_t)(0xFFFFFFFF & x1); 911 /* 912 * If caller is secure and SPMC was initialized, 913 * return FFA_VERSION of SPMD. 914 * If caller is non secure and SPMC was initialized, 915 * forward to the EL3 SPMC if enabled, otherwise return 916 * the SPMC version if implemented at a lower EL. 917 * Sanity check to "input_version". 918 * If the EL3 SPMC is enabled, ignore the SPMC state as 919 * this is not used. 920 */ 921 if ((input_version & FFA_VERSION_BIT31_MASK) || 922 (!is_spmc_at_el3() && (ctx->state == SPMC_STATE_RESET))) { 923 ret = FFA_ERROR_NOT_SUPPORTED; 924 } else if (!secure_origin) { 925 if (is_spmc_at_el3()) { 926 /* 927 * Forward the call directly to the EL3 SPMC, if 928 * enabled, as we don't need to wrap the call in 929 * a direct request. 930 */ 931 return spmd_smc_forward(smc_fid, secure_origin, 932 x1, x2, x3, x4, cookie, 933 handle, flags); 934 } 935 936 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 937 uint64_t rc; 938 939 if (spmc_attrs.major_version == 1 && 940 spmc_attrs.minor_version == 0) { 941 ret = MAKE_FFA_VERSION(spmc_attrs.major_version, 942 spmc_attrs.minor_version); 943 SMC_RET8(handle, (uint32_t)ret, 944 FFA_TARGET_INFO_MBZ, 945 FFA_TARGET_INFO_MBZ, 946 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 947 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 948 FFA_PARAM_MBZ); 949 break; 950 } 951 /* Save non-secure system registers context */ 952 #if SPMD_SPM_AT_SEL2 953 cm_el2_sysregs_context_save(NON_SECURE); 954 #else 955 cm_el1_sysregs_context_save(NON_SECURE); 956 #endif 957 958 /* 959 * The incoming request has FFA_VERSION as X0 smc_fid 960 * and requested version in x1. Prepare a direct request 961 * from SPMD to SPMC with FFA_VERSION framework function 962 * identifier in X2 and requested version in X3. 963 */ 964 spmd_build_spmc_message(gpregs, 965 SPMD_FWK_MSG_FFA_VERSION_REQ, 966 input_version); 967 968 /* 969 * Ensure x8-x17 NS GP register values are untouched when returning 970 * from the SPMC. 971 */ 972 write_ctx_reg(gpregs, CTX_GPREG_X8, SMC_GET_GP(handle, CTX_GPREG_X8)); 973 write_ctx_reg(gpregs, CTX_GPREG_X9, SMC_GET_GP(handle, CTX_GPREG_X9)); 974 write_ctx_reg(gpregs, CTX_GPREG_X10, SMC_GET_GP(handle, CTX_GPREG_X10)); 975 write_ctx_reg(gpregs, CTX_GPREG_X11, SMC_GET_GP(handle, CTX_GPREG_X11)); 976 write_ctx_reg(gpregs, CTX_GPREG_X12, SMC_GET_GP(handle, CTX_GPREG_X12)); 977 write_ctx_reg(gpregs, CTX_GPREG_X13, SMC_GET_GP(handle, CTX_GPREG_X13)); 978 write_ctx_reg(gpregs, CTX_GPREG_X14, SMC_GET_GP(handle, CTX_GPREG_X14)); 979 write_ctx_reg(gpregs, CTX_GPREG_X15, SMC_GET_GP(handle, CTX_GPREG_X15)); 980 write_ctx_reg(gpregs, CTX_GPREG_X16, SMC_GET_GP(handle, CTX_GPREG_X16)); 981 write_ctx_reg(gpregs, CTX_GPREG_X17, SMC_GET_GP(handle, CTX_GPREG_X17)); 982 983 rc = spmd_spm_core_sync_entry(ctx); 984 985 if ((rc != 0ULL) || 986 (SMC_GET_GP(gpregs, CTX_GPREG_X0) != 987 FFA_MSG_SEND_DIRECT_RESP_SMC32) || 988 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != 989 (FFA_FWK_MSG_BIT | 990 SPMD_FWK_MSG_FFA_VERSION_RESP))) { 991 ERROR("Failed to forward FFA_VERSION\n"); 992 ret = FFA_ERROR_NOT_SUPPORTED; 993 } else { 994 ret = SMC_GET_GP(gpregs, CTX_GPREG_X3); 995 } 996 997 /* 998 * x0-x4 are updated by spmd_smc_forward below. 999 * Zero out x5-x7 in the FFA_VERSION response. 1000 */ 1001 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 1002 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 1003 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 1004 1005 /* 1006 * Return here after SPMC has handled FFA_VERSION. 1007 * The returned SPMC version is held in X3. 1008 * Forward this version in X0 to the non-secure caller. 1009 */ 1010 return spmd_smc_forward(ret, true, FFA_PARAM_MBZ, 1011 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1012 FFA_PARAM_MBZ, cookie, gpregs, 1013 flags); 1014 } else { 1015 ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR, 1016 FFA_VERSION_MINOR); 1017 } 1018 1019 SMC_RET8(handle, (uint32_t)ret, FFA_TARGET_INFO_MBZ, 1020 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1021 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ); 1022 break; /* not reached */ 1023 1024 case FFA_FEATURES: 1025 /* 1026 * This is an optional interface. Do the minimal checks and 1027 * forward to SPM Core which will handle it if implemented. 1028 */ 1029 1030 /* Forward SMC from Normal world to the SPM Core */ 1031 if (!secure_origin) { 1032 return spmd_smc_forward(smc_fid, secure_origin, 1033 x1, x2, x3, x4, cookie, 1034 handle, flags); 1035 } 1036 1037 /* 1038 * Return success if call was from secure world i.e. all 1039 * FFA functions are supported. This is essentially a 1040 * nop. 1041 */ 1042 SMC_RET8(handle, FFA_SUCCESS_SMC32, x1, x2, x3, x4, 1043 SMC_GET_GP(handle, CTX_GPREG_X5), 1044 SMC_GET_GP(handle, CTX_GPREG_X6), 1045 SMC_GET_GP(handle, CTX_GPREG_X7)); 1046 1047 break; /* not reached */ 1048 1049 case FFA_ID_GET: 1050 /* 1051 * Returns the ID of the calling FFA component. 1052 */ 1053 if (!secure_origin) { 1054 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1055 FFA_TARGET_INFO_MBZ, FFA_NS_ENDPOINT_ID, 1056 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1057 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1058 FFA_PARAM_MBZ); 1059 } 1060 1061 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1062 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1063 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1064 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1065 FFA_PARAM_MBZ); 1066 1067 break; /* not reached */ 1068 1069 case FFA_SECONDARY_EP_REGISTER_SMC64: 1070 if (secure_origin) { 1071 ret = spmd_pm_secondary_ep_register(x1); 1072 1073 if (ret < 0) { 1074 SMC_RET8(handle, FFA_ERROR_SMC64, 1075 FFA_TARGET_INFO_MBZ, ret, 1076 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1077 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1078 FFA_PARAM_MBZ); 1079 } else { 1080 SMC_RET8(handle, FFA_SUCCESS_SMC64, 1081 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, 1082 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1083 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1084 FFA_PARAM_MBZ); 1085 } 1086 } 1087 1088 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1089 break; /* Not reached */ 1090 1091 case FFA_SPM_ID_GET: 1092 if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) { 1093 return spmd_ffa_error_return(handle, 1094 FFA_ERROR_NOT_SUPPORTED); 1095 } 1096 /* 1097 * Returns the ID of the SPMC or SPMD depending on the FF-A 1098 * instance where this function is invoked 1099 */ 1100 if (!secure_origin) { 1101 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1102 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1103 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1104 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1105 FFA_PARAM_MBZ); 1106 } 1107 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1108 FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID, 1109 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1110 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1111 FFA_PARAM_MBZ); 1112 1113 break; /* not reached */ 1114 1115 case FFA_MSG_SEND_DIRECT_REQ_SMC32: 1116 case FFA_MSG_SEND_DIRECT_REQ_SMC64: 1117 case FFA_MSG_SEND_DIRECT_REQ2_SMC64: 1118 /* 1119 * Regardless of secure_origin, SPMD logical partitions cannot 1120 * handle direct messages. They can only initiate direct 1121 * messages and consume direct responses or errors. 1122 */ 1123 if (is_spmd_lp_id(ffa_endpoint_source(x1)) || 1124 is_spmd_lp_id(ffa_endpoint_destination(x1))) { 1125 return spmd_ffa_error_return(handle, 1126 FFA_ERROR_INVALID_PARAMETER 1127 ); 1128 } 1129 1130 /* 1131 * When there is an ongoing SPMD logical partition direct 1132 * request, there cannot be another direct request. Return 1133 * error in this case. Panic'ing is an option but that does 1134 * not provide the opportunity for caller to abort based on 1135 * error codes. 1136 */ 1137 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1138 assert(secure_origin); 1139 return spmd_ffa_error_return(handle, 1140 FFA_ERROR_DENIED); 1141 } 1142 1143 if (!secure_origin) { 1144 /* Validate source endpoint is non-secure for non-secure caller. */ 1145 if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { 1146 return spmd_ffa_error_return(handle, 1147 FFA_ERROR_INVALID_PARAMETER); 1148 } 1149 } 1150 if (secure_origin && spmd_is_spmc_message(x1)) { 1151 return spmd_ffa_error_return(handle, 1152 FFA_ERROR_DENIED); 1153 } else { 1154 /* Forward direct message to the other world */ 1155 return spmd_smc_forward(smc_fid, secure_origin, 1156 x1, x2, x3, x4, cookie, 1157 handle, flags); 1158 } 1159 break; /* Not reached */ 1160 1161 case FFA_MSG_SEND_DIRECT_RESP_SMC32: 1162 case FFA_MSG_SEND_DIRECT_RESP_SMC64: 1163 case FFA_MSG_SEND_DIRECT_RESP2_SMC64: 1164 if (secure_origin && (spmd_is_spmc_message(x1) || 1165 is_spmd_logical_sp_dir_req_in_progress(ctx))) { 1166 spmd_spm_core_sync_exit(0ULL); 1167 } else { 1168 /* Forward direct message to the other world */ 1169 return spmd_smc_forward(smc_fid, secure_origin, 1170 x1, x2, x3, x4, cookie, 1171 handle, flags); 1172 } 1173 break; /* Not reached */ 1174 case FFA_RX_RELEASE: 1175 case FFA_RXTX_MAP_SMC32: 1176 case FFA_RXTX_MAP_SMC64: 1177 case FFA_RXTX_UNMAP: 1178 case FFA_PARTITION_INFO_GET: 1179 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1180 case FFA_NOTIFICATION_BITMAP_CREATE: 1181 case FFA_NOTIFICATION_BITMAP_DESTROY: 1182 case FFA_NOTIFICATION_BIND: 1183 case FFA_NOTIFICATION_UNBIND: 1184 case FFA_NOTIFICATION_SET: 1185 case FFA_NOTIFICATION_GET: 1186 case FFA_NOTIFICATION_INFO_GET: 1187 case FFA_NOTIFICATION_INFO_GET_SMC64: 1188 case FFA_MSG_SEND2: 1189 case FFA_RX_ACQUIRE: 1190 #endif 1191 case FFA_MSG_RUN: 1192 /* 1193 * Above calls should be invoked only by the Normal world and 1194 * must not be forwarded from Secure world to Normal world. 1195 */ 1196 if (secure_origin) { 1197 return spmd_ffa_error_return(handle, 1198 FFA_ERROR_NOT_SUPPORTED); 1199 } 1200 1201 /* Forward the call to the other world */ 1202 /* fallthrough */ 1203 case FFA_MSG_SEND: 1204 case FFA_MEM_DONATE_SMC32: 1205 case FFA_MEM_DONATE_SMC64: 1206 case FFA_MEM_LEND_SMC32: 1207 case FFA_MEM_LEND_SMC64: 1208 case FFA_MEM_SHARE_SMC32: 1209 case FFA_MEM_SHARE_SMC64: 1210 case FFA_MEM_RETRIEVE_REQ_SMC32: 1211 case FFA_MEM_RETRIEVE_REQ_SMC64: 1212 case FFA_MEM_RETRIEVE_RESP: 1213 case FFA_MEM_RELINQUISH: 1214 case FFA_MEM_RECLAIM: 1215 case FFA_MEM_FRAG_TX: 1216 case FFA_MEM_FRAG_RX: 1217 case FFA_SUCCESS_SMC32: 1218 case FFA_SUCCESS_SMC64: 1219 /* 1220 * If there is an ongoing direct request from an SPMD logical 1221 * partition, return an error. 1222 */ 1223 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1224 assert(secure_origin); 1225 return spmd_ffa_error_return(handle, 1226 FFA_ERROR_DENIED); 1227 } 1228 1229 return spmd_smc_forward(smc_fid, secure_origin, 1230 x1, x2, x3, x4, cookie, 1231 handle, flags); 1232 break; /* not reached */ 1233 1234 case FFA_MSG_WAIT: 1235 /* 1236 * Check if this is the first invocation of this interface on 1237 * this CPU from the Secure world. If so, then indicate that the 1238 * SPM Core initialised successfully. 1239 */ 1240 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 1241 spmd_spm_core_sync_exit(0ULL); 1242 } 1243 1244 /* Forward the call to the other world */ 1245 /* fallthrough */ 1246 case FFA_INTERRUPT: 1247 case FFA_MSG_YIELD: 1248 /* This interface must be invoked only by the Secure world */ 1249 if (!secure_origin) { 1250 return spmd_ffa_error_return(handle, 1251 FFA_ERROR_NOT_SUPPORTED); 1252 } 1253 1254 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1255 assert(secure_origin); 1256 return spmd_ffa_error_return(handle, 1257 FFA_ERROR_DENIED); 1258 } 1259 1260 return spmd_smc_forward(smc_fid, secure_origin, 1261 x1, x2, x3, x4, cookie, 1262 handle, flags); 1263 break; /* not reached */ 1264 1265 case FFA_NORMAL_WORLD_RESUME: 1266 if (secure_origin && ctx->secure_interrupt_ongoing) { 1267 spmd_spm_core_sync_exit(0ULL); 1268 } else { 1269 return spmd_ffa_error_return(handle, FFA_ERROR_DENIED); 1270 } 1271 break; /* Not reached */ 1272 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1273 case FFA_PARTITION_INFO_GET_REGS_SMC64: 1274 if (secure_origin) { 1275 return spmd_el3_populate_logical_partition_info(handle, x1, 1276 x2, x3); 1277 } 1278 1279 /* Call only supported with SMCCC 1.2+ */ 1280 if (MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION) < 0x10002) { 1281 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1282 } 1283 1284 return spmd_smc_forward(smc_fid, secure_origin, 1285 x1, x2, x3, x4, cookie, 1286 handle, flags); 1287 break; /* Not reached */ 1288 #endif 1289 case FFA_CONSOLE_LOG_SMC32: 1290 case FFA_CONSOLE_LOG_SMC64: 1291 /* This interface must not be forwarded to other worlds. */ 1292 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1293 break; /* not reached */ 1294 1295 case FFA_EL3_INTR_HANDLE: 1296 if (secure_origin) { 1297 return spmd_handle_group0_intr_swd(handle); 1298 } else { 1299 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1300 } 1301 default: 1302 WARN("SPM: Unsupported call 0x%08x\n", smc_fid); 1303 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1304 } 1305 } 1306