1b61d94a1SMarc Bonnici /* 2*127bd5b1SLevi Yun * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 3b61d94a1SMarc Bonnici * 4b61d94a1SMarc Bonnici * SPDX-License-Identifier: BSD-3-Clause 5b61d94a1SMarc Bonnici */ 6b61d94a1SMarc Bonnici 7b61d94a1SMarc Bonnici #ifndef SPM_MM_PRIVATE_H 8b61d94a1SMarc Bonnici #define SPM_MM_PRIVATE_H 9b61d94a1SMarc Bonnici 10b61d94a1SMarc Bonnici #include <context.h> 11b61d94a1SMarc Bonnici #include "spm_common.h" 12b61d94a1SMarc Bonnici 13b61d94a1SMarc Bonnici /******************************************************************************* 14b61d94a1SMarc Bonnici * Constants that allow assembler code to preserve callee-saved registers of the 15b61d94a1SMarc Bonnici * C runtime context while performing a security state switch. 16b61d94a1SMarc Bonnici ******************************************************************************/ 17b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X19 0x0 18b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X20 0x8 19b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X21 0x10 20b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X22 0x18 21b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X23 0x20 22b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X24 0x28 23b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X25 0x30 24b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X26 0x38 25b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X27 0x40 26b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X28 0x48 27b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X29 0x50 28b61d94a1SMarc Bonnici #define SP_C_RT_CTX_X30 0x58 29b61d94a1SMarc Bonnici 30b61d94a1SMarc Bonnici #define SP_C_RT_CTX_SIZE 0x60 31b61d94a1SMarc Bonnici #define SP_C_RT_CTX_ENTRIES (SP_C_RT_CTX_SIZE >> DWORD_SHIFT) 32b61d94a1SMarc Bonnici 33b61d94a1SMarc Bonnici #ifndef __ASSEMBLER__ 34b61d94a1SMarc Bonnici 35b61d94a1SMarc Bonnici #include <stdint.h> 36b61d94a1SMarc Bonnici 37b61d94a1SMarc Bonnici #include <lib/spinlock.h> 38b61d94a1SMarc Bonnici #include <lib/xlat_tables/xlat_tables_v2.h> 39b61d94a1SMarc Bonnici 40b61d94a1SMarc Bonnici typedef enum sp_state { 41b61d94a1SMarc Bonnici SP_STATE_RESET = 0, 42b61d94a1SMarc Bonnici SP_STATE_IDLE, 43b61d94a1SMarc Bonnici SP_STATE_BUSY 44b61d94a1SMarc Bonnici } sp_state_t; 45b61d94a1SMarc Bonnici 46b61d94a1SMarc Bonnici typedef struct sp_context { 47b61d94a1SMarc Bonnici uint64_t c_rt_ctx; 48b61d94a1SMarc Bonnici cpu_context_t cpu_ctx; 49b61d94a1SMarc Bonnici xlat_ctx_t *xlat_ctx_handle; 50b61d94a1SMarc Bonnici 51b61d94a1SMarc Bonnici sp_state_t state; 52b61d94a1SMarc Bonnici spinlock_t state_lock; 53b61d94a1SMarc Bonnici } sp_context_t; 54b61d94a1SMarc Bonnici 55b61d94a1SMarc Bonnici 56b61d94a1SMarc Bonnici void spm_sp_setup(sp_context_t *sp_ctx); 57b61d94a1SMarc Bonnici 58b61d94a1SMarc Bonnici int32_t spm_memory_attributes_get_smc_handler(sp_context_t *sp_ctx, 59*127bd5b1SLevi Yun uintptr_t base_va, 60*127bd5b1SLevi Yun uint32_t *page_count, 61*127bd5b1SLevi Yun uint32_t *attr); 62b61d94a1SMarc Bonnici int spm_memory_attributes_set_smc_handler(sp_context_t *sp_ctx, 63b61d94a1SMarc Bonnici u_register_t page_address, 64b61d94a1SMarc Bonnici u_register_t pages_count, 65b61d94a1SMarc Bonnici u_register_t smc_attributes); 66b61d94a1SMarc Bonnici 67b61d94a1SMarc Bonnici #endif /* __ASSEMBLER__ */ 68b61d94a1SMarc Bonnici 69b61d94a1SMarc Bonnici #endif /* SPM_MM_PRIVATE_H */ 70