1*1132f068SNishant Sharma/* 2*1132f068SNishant Sharma * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3*1132f068SNishant Sharma * 4*1132f068SNishant Sharma * SPDX-License-Identifier: BSD-3-Clause 5*1132f068SNishant Sharma */ 6*1132f068SNishant Sharma 7*1132f068SNishant Sharma#include <arch.h> 8*1132f068SNishant Sharma#include <asm_macros.S> 9*1132f068SNishant Sharma#include <common/bl_common.h> 10*1132f068SNishant Sharma#include <context.h> 11*1132f068SNishant Sharma 12*1132f068SNishant Sharma/* ----------------------------------------------------------------------------- 13*1132f068SNishant Sharma * Very simple stackless exception handlers used by the spm shim layer. 14*1132f068SNishant Sharma * ----------------------------------------------------------------------------- 15*1132f068SNishant Sharma */ 16*1132f068SNishant Sharma .globl spm_shim_exceptions_ptr 17*1132f068SNishant Sharma 18*1132f068SNishant Sharmavector_base spm_shim_exceptions_ptr, .spm_shim_exceptions 19*1132f068SNishant Sharma 20*1132f068SNishant Sharma /* ----------------------------------------------------- 21*1132f068SNishant Sharma * Current EL with SP0 : 0x0 - 0x200 22*1132f068SNishant Sharma * ----------------------------------------------------- 23*1132f068SNishant Sharma */ 24*1132f068SNishant Sharmavector_entry SynchronousExceptionSP0, .spm_shim_exceptions 25*1132f068SNishant Sharma b . 26*1132f068SNishant Sharmaend_vector_entry SynchronousExceptionSP0 27*1132f068SNishant Sharma 28*1132f068SNishant Sharmavector_entry IrqSP0, .spm_shim_exceptions 29*1132f068SNishant Sharma b . 30*1132f068SNishant Sharmaend_vector_entry IrqSP0 31*1132f068SNishant Sharma 32*1132f068SNishant Sharmavector_entry FiqSP0, .spm_shim_exceptions 33*1132f068SNishant Sharma b . 34*1132f068SNishant Sharmaend_vector_entry FiqSP0 35*1132f068SNishant Sharma 36*1132f068SNishant Sharmavector_entry SErrorSP0, .spm_shim_exceptions 37*1132f068SNishant Sharma b . 38*1132f068SNishant Sharmaend_vector_entry SErrorSP0 39*1132f068SNishant Sharma 40*1132f068SNishant Sharma /* ----------------------------------------------------- 41*1132f068SNishant Sharma * Current EL with SPx: 0x200 - 0x400 42*1132f068SNishant Sharma * ----------------------------------------------------- 43*1132f068SNishant Sharma */ 44*1132f068SNishant Sharmavector_entry SynchronousExceptionSPx, .spm_shim_exceptions 45*1132f068SNishant Sharma b . 46*1132f068SNishant Sharmaend_vector_entry SynchronousExceptionSPx 47*1132f068SNishant Sharma 48*1132f068SNishant Sharmavector_entry IrqSPx, .spm_shim_exceptions 49*1132f068SNishant Sharma b . 50*1132f068SNishant Sharmaend_vector_entry IrqSPx 51*1132f068SNishant Sharma 52*1132f068SNishant Sharmavector_entry FiqSPx, .spm_shim_exceptions 53*1132f068SNishant Sharma b . 54*1132f068SNishant Sharmaend_vector_entry FiqSPx 55*1132f068SNishant Sharma 56*1132f068SNishant Sharmavector_entry SErrorSPx, .spm_shim_exceptions 57*1132f068SNishant Sharma b . 58*1132f068SNishant Sharmaend_vector_entry SErrorSPx 59*1132f068SNishant Sharma 60*1132f068SNishant Sharma /* ----------------------------------------------------- 61*1132f068SNishant Sharma * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 62*1132f068SNishant Sharma * are handled since secure_partition does not implement 63*1132f068SNishant Sharma * a lower EL 64*1132f068SNishant Sharma * ----------------------------------------------------- 65*1132f068SNishant Sharma */ 66*1132f068SNishant Sharmavector_entry SynchronousExceptionA64, .spm_shim_exceptions 67*1132f068SNishant Sharma msr tpidr_el1, x30 68*1132f068SNishant Sharma mrs x30, esr_el1 69*1132f068SNishant Sharma ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 70*1132f068SNishant Sharma 71*1132f068SNishant Sharma cmp x30, #EC_AARCH64_SVC 72*1132f068SNishant Sharma b.eq do_smc 73*1132f068SNishant Sharma 74*1132f068SNishant Sharma cmp x30, #EC_AARCH32_SVC 75*1132f068SNishant Sharma b.eq do_smc 76*1132f068SNishant Sharma 77*1132f068SNishant Sharma cmp x30, #EC_AARCH64_SYS 78*1132f068SNishant Sharma b.eq handle_sys_trap 79*1132f068SNishant Sharma 80*1132f068SNishant Sharma /* Fail in all the other cases */ 81*1132f068SNishant Sharma b panic 82*1132f068SNishant Sharma 83*1132f068SNishant Sharma /* --------------------------------------------- 84*1132f068SNishant Sharma * Tell SPM that we are done initialising 85*1132f068SNishant Sharma * --------------------------------------------- 86*1132f068SNishant Sharma */ 87*1132f068SNishant Sharmado_smc: 88*1132f068SNishant Sharma mrs x30, tpidr_el1 89*1132f068SNishant Sharma smc #0 90*1132f068SNishant Sharma exception_return 91*1132f068SNishant Sharma 92*1132f068SNishant Sharma /* AArch64 system instructions trap are handled as a panic for now */ 93*1132f068SNishant Sharmahandle_sys_trap: 94*1132f068SNishant Sharmapanic: 95*1132f068SNishant Sharma b panic 96*1132f068SNishant Sharmaend_vector_entry SynchronousExceptionA64 97*1132f068SNishant Sharma 98*1132f068SNishant Sharmavector_entry IrqA64, .spm_shim_exceptions 99*1132f068SNishant Sharma b . 100*1132f068SNishant Sharmaend_vector_entry IrqA64 101*1132f068SNishant Sharma 102*1132f068SNishant Sharmavector_entry FiqA64, .spm_shim_exceptions 103*1132f068SNishant Sharma b . 104*1132f068SNishant Sharmaend_vector_entry FiqA64 105*1132f068SNishant Sharma 106*1132f068SNishant Sharmavector_entry SErrorA64, .spm_shim_exceptions 107*1132f068SNishant Sharma b . 108*1132f068SNishant Sharmaend_vector_entry SErrorA64 109*1132f068SNishant Sharma 110*1132f068SNishant Sharma /* ----------------------------------------------------- 111*1132f068SNishant Sharma * Lower EL using AArch32 : 0x600 - 0x800 112*1132f068SNishant Sharma * ----------------------------------------------------- 113*1132f068SNishant Sharma */ 114*1132f068SNishant Sharmavector_entry SynchronousExceptionA32, .spm_shim_exceptions 115*1132f068SNishant Sharma b . 116*1132f068SNishant Sharmaend_vector_entry SynchronousExceptionA32 117*1132f068SNishant Sharma 118*1132f068SNishant Sharmavector_entry IrqA32, .spm_shim_exceptions 119*1132f068SNishant Sharma b . 120*1132f068SNishant Sharmaend_vector_entry IrqA32 121*1132f068SNishant Sharma 122*1132f068SNishant Sharmavector_entry FiqA32, .spm_shim_exceptions 123*1132f068SNishant Sharma b . 124*1132f068SNishant Sharmaend_vector_entry FiqA32 125*1132f068SNishant Sharma 126*1132f068SNishant Sharmavector_entry SErrorA32, .spm_shim_exceptions 127*1132f068SNishant Sharma b . 128*1132f068SNishant Sharmaend_vector_entry SErrorA32 129