1 /* 2 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch_features.h> 15 #include <bl31/bl31.h> 16 #include <common/debug.h> 17 #include <common/runtime_svc.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/cpu_data.h> 21 #include <lib/el3_runtime/pubsub.h> 22 #include <lib/extensions/pmuv3.h> 23 #include <lib/extensions/sys_reg_trace.h> 24 #include <lib/gpt_rme/gpt_rme.h> 25 26 #include <lib/spinlock.h> 27 #include <lib/utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/common_def.h> 30 #include <plat/common/platform.h> 31 #include <platform_def.h> 32 #include <services/rmmd_svc.h> 33 #include <smccc_helpers.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/sve.h> 36 #include "rmmd_initial_context.h" 37 #include "rmmd_private.h" 38 39 /******************************************************************************* 40 * RMM boot failure flag 41 ******************************************************************************/ 42 static bool rmm_boot_failed; 43 44 /******************************************************************************* 45 * RMM context information. 46 ******************************************************************************/ 47 rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT]; 48 49 /******************************************************************************* 50 * RMM entry point information. Discovered on the primary core and reused 51 * on secondary cores. 52 ******************************************************************************/ 53 static entry_point_info_t *rmm_ep_info; 54 55 /******************************************************************************* 56 * Static function declaration. 57 ******************************************************************************/ 58 static int32_t rmm_init(void); 59 60 /******************************************************************************* 61 * This function takes an RMM context pointer and performs a synchronous entry 62 * into it. 63 ******************************************************************************/ 64 uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *rmm_ctx) 65 { 66 uint64_t rc; 67 68 assert(rmm_ctx != NULL); 69 70 cm_set_context(&(rmm_ctx->cpu_ctx), REALM); 71 72 /* Restore the realm context assigned above */ 73 cm_el1_sysregs_context_restore(REALM); 74 cm_el2_sysregs_context_restore(REALM); 75 cm_set_next_eret_context(REALM); 76 77 /* Enter RMM */ 78 rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx); 79 80 /* 81 * Save realm context. EL1 and EL2 Non-secure 82 * contexts will be restored before exiting to 83 * Non-secure world, therefore there is no need 84 * to clear EL1 and EL2 context registers. 85 */ 86 cm_el1_sysregs_context_save(REALM); 87 cm_el2_sysregs_context_save(REALM); 88 89 return rc; 90 } 91 92 /******************************************************************************* 93 * This function returns to the place where rmmd_rmm_sync_entry() was 94 * called originally. 95 ******************************************************************************/ 96 __dead2 void rmmd_rmm_sync_exit(uint64_t rc) 97 { 98 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; 99 100 /* Get context of the RMM in use by this CPU. */ 101 assert(cm_get_context(REALM) == &(ctx->cpu_ctx)); 102 103 /* 104 * The RMMD must have initiated the original request through a 105 * synchronous entry into RMM. Jump back to the original C runtime 106 * context with the value of rc in x0; 107 */ 108 rmmd_rmm_exit(ctx->c_rt_ctx, rc); 109 110 panic(); 111 } 112 113 static void rmm_el2_context_init(el2_sysregs_t *regs) 114 { 115 regs->ctx_regs[CTX_SPSR_EL2 >> 3] = REALM_SPSR_EL2; 116 regs->ctx_regs[CTX_SCTLR_EL2 >> 3] = SCTLR_EL2_RES1; 117 } 118 119 /******************************************************************************* 120 * Enable architecture extensions on first entry to Realm world. 121 ******************************************************************************/ 122 123 static void manage_extensions_realm(cpu_context_t *ctx) 124 { 125 pmuv3_enable(ctx); 126 127 /* 128 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 129 */ 130 if (is_feat_sme_supported()) { 131 sme_enable(ctx); 132 } 133 } 134 135 static void manage_extensions_realm_per_world(void) 136 { 137 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 138 139 if (is_feat_sve_supported()) { 140 /* 141 * Enable SVE and FPU in realm context when it is enabled for NS. 142 * Realm manager must ensure that the SVE and FPU register 143 * contexts are properly managed. 144 */ 145 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 146 } 147 148 /* NS can access this but Realm shouldn't */ 149 if (is_feat_sys_reg_trace_supported()) { 150 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 151 } 152 153 /* 154 * If SME/SME2 is supported and enabled for NS world, then disable trapping 155 * of SME instructions for Realm world. RMM will save/restore required 156 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 157 */ 158 if (is_feat_sme_supported()) { 159 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 160 } 161 } 162 163 /******************************************************************************* 164 * Jump to the RMM for the first time. 165 ******************************************************************************/ 166 static int32_t rmm_init(void) 167 { 168 long rc; 169 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; 170 171 INFO("RMM init start.\n"); 172 173 /* Enable architecture extensions */ 174 manage_extensions_realm(&ctx->cpu_ctx); 175 176 manage_extensions_realm_per_world(); 177 178 /* Initialize RMM EL2 context. */ 179 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); 180 181 rc = rmmd_rmm_sync_entry(ctx); 182 if (rc != E_RMM_BOOT_SUCCESS) { 183 ERROR("RMM init failed: %ld\n", rc); 184 /* Mark the boot as failed for all the CPUs */ 185 rmm_boot_failed = true; 186 return 0; 187 } 188 189 INFO("RMM init end.\n"); 190 191 return 1; 192 } 193 194 /******************************************************************************* 195 * Load and read RMM manifest, setup RMM. 196 ******************************************************************************/ 197 int rmmd_setup(void) 198 { 199 size_t shared_buf_size __unused; 200 uintptr_t shared_buf_base; 201 uint32_t ep_attr; 202 unsigned int linear_id = plat_my_core_pos(); 203 rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id]; 204 struct rmm_manifest *manifest; 205 int rc; 206 207 /* Make sure RME is supported. */ 208 assert(get_armv9_2_feat_rme_support() != 0U); 209 210 rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM); 211 if (rmm_ep_info == NULL) { 212 WARN("No RMM image provided by BL2 boot loader, Booting " 213 "device without RMM initialization. SMCs destined for " 214 "RMM will return SMC_UNK\n"); 215 return -ENOENT; 216 } 217 218 /* Under no circumstances will this parameter be 0 */ 219 assert(rmm_ep_info->pc == RMM_BASE); 220 221 /* Initialise an entrypoint to set up the CPU context */ 222 ep_attr = EP_REALM; 223 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) { 224 ep_attr |= EP_EE_BIG; 225 } 226 227 SET_PARAM_HEAD(rmm_ep_info, PARAM_EP, VERSION_1, ep_attr); 228 rmm_ep_info->spsr = SPSR_64(MODE_EL2, 229 MODE_SP_ELX, 230 DISABLE_ALL_EXCEPTIONS); 231 232 shared_buf_size = 233 plat_rmmd_get_el3_rmm_shared_mem(&shared_buf_base); 234 235 assert((shared_buf_size == SZ_4K) && 236 ((void *)shared_buf_base != NULL)); 237 238 /* Load the boot manifest at the beginning of the shared area */ 239 manifest = (struct rmm_manifest *)shared_buf_base; 240 rc = plat_rmmd_load_manifest(manifest); 241 if (rc != 0) { 242 ERROR("Error loading RMM Boot Manifest (%i)\n", rc); 243 return rc; 244 } 245 flush_dcache_range((uintptr_t)shared_buf_base, shared_buf_size); 246 247 /* 248 * Prepare coldboot arguments for RMM: 249 * arg0: This CPUID (primary processor). 250 * arg1: Version for this Boot Interface. 251 * arg2: PLATFORM_CORE_COUNT. 252 * arg3: Base address for the EL3 <-> RMM shared area. The boot 253 * manifest will be stored at the beginning of this area. 254 */ 255 rmm_ep_info->args.arg0 = linear_id; 256 rmm_ep_info->args.arg1 = RMM_EL3_INTERFACE_VERSION; 257 rmm_ep_info->args.arg2 = PLATFORM_CORE_COUNT; 258 rmm_ep_info->args.arg3 = shared_buf_base; 259 260 /* Initialise RMM context with this entry point information */ 261 cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info); 262 263 INFO("RMM setup done.\n"); 264 265 /* Register init function for deferred init. */ 266 bl31_register_rmm_init(&rmm_init); 267 268 return 0; 269 } 270 271 /******************************************************************************* 272 * Forward SMC to the other security state 273 ******************************************************************************/ 274 static uint64_t rmmd_smc_forward(uint32_t src_sec_state, 275 uint32_t dst_sec_state, uint64_t x0, 276 uint64_t x1, uint64_t x2, uint64_t x3, 277 uint64_t x4, void *handle) 278 { 279 cpu_context_t *ctx = cm_get_context(dst_sec_state); 280 281 /* Save incoming security state */ 282 cm_el1_sysregs_context_save(src_sec_state); 283 cm_el2_sysregs_context_save(src_sec_state); 284 285 /* Restore outgoing security state */ 286 cm_el1_sysregs_context_restore(dst_sec_state); 287 cm_el2_sysregs_context_restore(dst_sec_state); 288 cm_set_next_eret_context(dst_sec_state); 289 290 /* 291 * As per SMCCCv1.2, we need to preserve x4 to x7 unless 292 * being used as return args. Hence we differentiate the 293 * onward and backward path. Support upto 8 args in the 294 * onward path and 4 args in return path. 295 * Register x4 will be preserved by RMM in case it is not 296 * used in return path. 297 */ 298 if (src_sec_state == NON_SECURE) { 299 SMC_RET8(ctx, x0, x1, x2, x3, x4, 300 SMC_GET_GP(handle, CTX_GPREG_X5), 301 SMC_GET_GP(handle, CTX_GPREG_X6), 302 SMC_GET_GP(handle, CTX_GPREG_X7)); 303 } 304 305 SMC_RET5(ctx, x0, x1, x2, x3, x4); 306 } 307 308 /******************************************************************************* 309 * This function handles all SMCs in the range reserved for RMI. Each call is 310 * either forwarded to the other security state or handled by the RMM dispatcher 311 ******************************************************************************/ 312 uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, 313 uint64_t x3, uint64_t x4, void *cookie, 314 void *handle, uint64_t flags) 315 { 316 uint32_t src_sec_state; 317 318 /* If RMM failed to boot, treat any RMI SMC as unknown */ 319 if (rmm_boot_failed) { 320 WARN("RMMD: Failed to boot up RMM. Ignoring RMI call\n"); 321 SMC_RET1(handle, SMC_UNK); 322 } 323 324 /* Determine which security state this SMC originated from */ 325 src_sec_state = caller_sec_state(flags); 326 327 /* RMI must not be invoked by the Secure world */ 328 if (src_sec_state == SMC_FROM_SECURE) { 329 WARN("RMMD: RMI invoked by secure world.\n"); 330 SMC_RET1(handle, SMC_UNK); 331 } 332 333 /* 334 * Forward an RMI call from the Normal world to the Realm world as it 335 * is. 336 */ 337 if (src_sec_state == SMC_FROM_NON_SECURE) { 338 /* 339 * If SVE hint bit is set in the flags then update the SMC 340 * function id and pass it on to the lower EL. 341 */ 342 if (is_sve_hint_set(flags)) { 343 smc_fid |= (FUNCID_SVE_HINT_MASK << 344 FUNCID_SVE_HINT_SHIFT); 345 } 346 VERBOSE("RMMD: RMI call from non-secure world.\n"); 347 return rmmd_smc_forward(NON_SECURE, REALM, smc_fid, 348 x1, x2, x3, x4, handle); 349 } 350 351 if (src_sec_state != SMC_FROM_REALM) { 352 SMC_RET1(handle, SMC_UNK); 353 } 354 355 switch (smc_fid) { 356 case RMM_RMI_REQ_COMPLETE: { 357 uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 358 359 return rmmd_smc_forward(REALM, NON_SECURE, x1, 360 x2, x3, x4, x5, handle); 361 } 362 default: 363 WARN("RMMD: Unsupported RMM call 0x%08x\n", smc_fid); 364 SMC_RET1(handle, SMC_UNK); 365 } 366 } 367 368 /******************************************************************************* 369 * This cpu has been turned on. Enter RMM to initialise R-EL2. Entry into RMM 370 * is done after initialising minimal architectural state that guarantees safe 371 * execution. 372 ******************************************************************************/ 373 static void *rmmd_cpu_on_finish_handler(const void *arg) 374 { 375 long rc; 376 uint32_t linear_id = plat_my_core_pos(); 377 rmmd_rmm_context_t *ctx = &rmm_context[linear_id]; 378 379 if (rmm_boot_failed) { 380 /* RMM Boot failed on a previous CPU. Abort. */ 381 ERROR("RMM Failed to initialize. Ignoring for CPU%d\n", 382 linear_id); 383 return NULL; 384 } 385 386 /* 387 * Prepare warmboot arguments for RMM: 388 * arg0: This CPUID. 389 * arg1 to arg3: Not used. 390 */ 391 rmm_ep_info->args.arg0 = linear_id; 392 rmm_ep_info->args.arg1 = 0ULL; 393 rmm_ep_info->args.arg2 = 0ULL; 394 rmm_ep_info->args.arg3 = 0ULL; 395 396 /* Initialise RMM context with this entry point information */ 397 cm_setup_context(&ctx->cpu_ctx, rmm_ep_info); 398 399 /* Enable architecture extensions */ 400 manage_extensions_realm(&ctx->cpu_ctx); 401 402 /* Initialize RMM EL2 context. */ 403 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); 404 405 rc = rmmd_rmm_sync_entry(ctx); 406 407 if (rc != E_RMM_BOOT_SUCCESS) { 408 ERROR("RMM init failed on CPU%d: %ld\n", linear_id, rc); 409 /* Mark the boot as failed for any other booting CPU */ 410 rmm_boot_failed = true; 411 } 412 413 return NULL; 414 } 415 416 /* Subscribe to PSCI CPU on to initialize RMM on secondary */ 417 SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, rmmd_cpu_on_finish_handler); 418 419 /* Convert GPT lib error to RMMD GTS error */ 420 static int gpt_to_gts_error(int error, uint32_t smc_fid, uint64_t address) 421 { 422 int ret; 423 424 if (error == 0) { 425 return E_RMM_OK; 426 } 427 428 if (error == -EINVAL) { 429 ret = E_RMM_BAD_ADDR; 430 } else { 431 /* This is the only other error code we expect */ 432 assert(error == -EPERM); 433 ret = E_RMM_BAD_PAS; 434 } 435 436 ERROR("RMMD: PAS Transition failed. GPT ret = %d, PA: 0x%"PRIx64 ", FID = 0x%x\n", 437 error, address, smc_fid); 438 return ret; 439 } 440 441 /******************************************************************************* 442 * This function handles RMM-EL3 interface SMCs 443 ******************************************************************************/ 444 uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, 445 uint64_t x3, uint64_t x4, void *cookie, 446 void *handle, uint64_t flags) 447 { 448 uint32_t src_sec_state; 449 int ret; 450 451 /* If RMM failed to boot, treat any RMM-EL3 interface SMC as unknown */ 452 if (rmm_boot_failed) { 453 WARN("RMMD: Failed to boot up RMM. Ignoring RMM-EL3 call\n"); 454 SMC_RET1(handle, SMC_UNK); 455 } 456 457 /* Determine which security state this SMC originated from */ 458 src_sec_state = caller_sec_state(flags); 459 460 if (src_sec_state != SMC_FROM_REALM) { 461 WARN("RMMD: RMM-EL3 call originated from secure or normal world\n"); 462 SMC_RET1(handle, SMC_UNK); 463 } 464 465 switch (smc_fid) { 466 case RMM_GTSI_DELEGATE: 467 ret = gpt_delegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); 468 SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); 469 case RMM_GTSI_UNDELEGATE: 470 ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); 471 SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); 472 case RMM_ATTEST_GET_PLAT_TOKEN: 473 ret = rmmd_attest_get_platform_token(x1, &x2, x3); 474 SMC_RET2(handle, ret, x2); 475 case RMM_ATTEST_GET_REALM_KEY: 476 ret = rmmd_attest_get_signing_key(x1, &x2, x3); 477 SMC_RET2(handle, ret, x2); 478 479 case RMM_BOOT_COMPLETE: 480 VERBOSE("RMMD: running rmmd_rmm_sync_exit\n"); 481 rmmd_rmm_sync_exit(x1); 482 483 default: 484 WARN("RMMD: Unsupported RMM-EL3 call 0x%08x\n", smc_fid); 485 SMC_RET1(handle, SMC_UNK); 486 } 487 } 488