1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TSPD_PRIVATE_H__ 32 #define __TSPD_PRIVATE_H__ 33 34 #include <arch.h> 35 #include <context.h> 36 #include <platform.h> 37 #include <psci.h> 38 39 /******************************************************************************* 40 * Secure Payload PM state information e.g. SP is suspended, uninitialised etc 41 * and macros to access the state information in the per-cpu 'state' flags 42 ******************************************************************************/ 43 #define TSP_PSTATE_OFF 0 44 #define TSP_PSTATE_ON 1 45 #define TSP_PSTATE_SUSPEND 2 46 #define TSP_PSTATE_SHIFT 0 47 #define TSP_PSTATE_MASK 0x3 48 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) 49 #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ 50 << TSP_PSTATE_SHIFT)) 51 #define set_tsp_pstate(st, pst) do { \ 52 clr_tsp_pstate(st); \ 53 st |= (pst & TSP_PSTATE_MASK) << \ 54 TSP_PSTATE_SHIFT; \ 55 } while (0); 56 57 58 /* 59 * This flag is used by the TSPD to determine if the TSP is servicing a standard 60 * SMC request prior to programming the next entry into the TSP e.g. if TSP 61 * execution is preempted by a non-secure interrupt and handed control to the 62 * normal world. If another request which is distinct from what the TSP was 63 * previously doing arrives, then this flag will be help the TSPD to either 64 * reject the new request or service it while ensuring that the previous context 65 * is not corrupted. 66 */ 67 #define STD_SMC_ACTIVE_FLAG_SHIFT 2 68 #define STD_SMC_ACTIVE_FLAG_MASK 1 69 #define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ 70 & STD_SMC_ACTIVE_FLAG_MASK) 71 #define set_std_smc_active_flag(state) (state |= \ 72 1 << STD_SMC_ACTIVE_FLAG_SHIFT) 73 #define clr_std_smc_active_flag(state) (state &= \ 74 ~(STD_SMC_ACTIVE_FLAG_MASK \ 75 << STD_SMC_ACTIVE_FLAG_SHIFT)) 76 77 /******************************************************************************* 78 * Secure Payload execution state information i.e. aarch32 or aarch64 79 ******************************************************************************/ 80 #define TSP_AARCH32 MODE_RW_32 81 #define TSP_AARCH64 MODE_RW_64 82 83 /******************************************************************************* 84 * The SPD should know the type of Secure Payload. 85 ******************************************************************************/ 86 #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP 87 #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP 88 #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP 89 90 /******************************************************************************* 91 * Secure Payload migrate type information as known to the SPD. We assume that 92 * the SPD is dealing with an MP Secure Payload. 93 ******************************************************************************/ 94 #define TSP_MIGRATE_INFO TSP_TYPE_MP 95 96 /******************************************************************************* 97 * Number of cpus that the present on this platform. TODO: Rely on a topology 98 * tree to determine this in the future to avoid assumptions about mpidr 99 * allocation 100 ******************************************************************************/ 101 #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT 102 103 /******************************************************************************* 104 * Constants that allow assembler code to preserve callee-saved registers of the 105 * C runtime context while performing a security state switch. 106 ******************************************************************************/ 107 #define TSPD_C_RT_CTX_X19 0x0 108 #define TSPD_C_RT_CTX_X20 0x8 109 #define TSPD_C_RT_CTX_X21 0x10 110 #define TSPD_C_RT_CTX_X22 0x18 111 #define TSPD_C_RT_CTX_X23 0x20 112 #define TSPD_C_RT_CTX_X24 0x28 113 #define TSPD_C_RT_CTX_X25 0x30 114 #define TSPD_C_RT_CTX_X26 0x38 115 #define TSPD_C_RT_CTX_X27 0x40 116 #define TSPD_C_RT_CTX_X28 0x48 117 #define TSPD_C_RT_CTX_X29 0x50 118 #define TSPD_C_RT_CTX_X30 0x58 119 #define TSPD_C_RT_CTX_SIZE 0x60 120 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) 121 122 #ifndef __ASSEMBLY__ 123 124 #include <cassert.h> 125 #include <stdint.h> 126 127 /* AArch64 callee saved general purpose register context structure. */ 128 DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); 129 130 /* 131 * Compile time assertion to ensure that both the compiler and linker 132 * have the same double word aligned view of the size of the C runtime 133 * register context. 134 */ 135 CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 136 assert_spd_c_rt_regs_size_mismatch); 137 138 /******************************************************************************* 139 * Structure which helps the SPD to maintain the per-cpu state of the SP. 140 * 'state' - collection of flags to track SP state e.g. on/off 141 * 'mpidr' - mpidr to associate a context with a cpu 142 * 'c_rt_ctx' - stack address to restore C runtime context from after returning 143 * from a synchronous entry into the SP. 144 * 'cpu_ctx' - space to maintain SP architectural state 145 ******************************************************************************/ 146 typedef struct tsp_context { 147 uint32_t state; 148 uint64_t mpidr; 149 uint64_t c_rt_ctx; 150 cpu_context_t cpu_ctx; 151 } tsp_context_t; 152 153 /* TSPD power management handlers */ 154 extern const spd_pm_ops_t tspd_pm; 155 156 /******************************************************************************* 157 * Forward declarations 158 ******************************************************************************/ 159 struct entry_info; 160 161 /******************************************************************************* 162 * Function & Data prototypes 163 ******************************************************************************/ 164 extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); 165 extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 166 extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); 167 extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); 168 extern int32_t tspd_init_secure_context(uint64_t entrypoint, 169 uint32_t rw, 170 uint64_t mpidr, 171 tsp_context_t *tsp_ctx); 172 extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 173 extern struct entry_info *tsp_entry_info; 174 #endif /*__ASSEMBLY__*/ 175 176 #endif /* __TSPD_PRIVATE_H__ */ 177