1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TSPD_PRIVATE_H__ 32 #define __TSPD_PRIVATE_H__ 33 34 #include <arch.h> 35 #include <context.h> 36 #include <platform.h> 37 #include <psci.h> 38 39 /******************************************************************************* 40 * Secure Payload PM state information e.g. SP is suspended, uninitialised etc 41 ******************************************************************************/ 42 #define TSP_STATE_OFF 0 43 #define TSP_STATE_ON 1 44 #define TSP_STATE_SUSPEND 2 45 46 /******************************************************************************* 47 * Secure Payload execution state information i.e. aarch32 or aarch64 48 ******************************************************************************/ 49 #define TSP_AARCH32 MODE_RW_32 50 #define TSP_AARCH64 MODE_RW_64 51 52 /******************************************************************************* 53 * The SPD should know the type of Secure Payload. 54 ******************************************************************************/ 55 #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP 56 #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP 57 #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP 58 59 /******************************************************************************* 60 * Secure Payload migrate type information as known to the SPD. We assume that 61 * the SPD is dealing with an MP Secure Payload. 62 ******************************************************************************/ 63 #define TSP_MIGRATE_INFO TSP_TYPE_MP 64 65 /******************************************************************************* 66 * Number of cpus that the present on this platform. TODO: Rely on a topology 67 * tree to determine this in the future to avoid assumptions about mpidr 68 * allocation 69 ******************************************************************************/ 70 #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT 71 72 /******************************************************************************* 73 * Constants that allow assembler code to preserve callee-saved registers of the 74 * C runtime context while performing a security state switch. 75 ******************************************************************************/ 76 #define TSPD_C_RT_CTX_X19 0x0 77 #define TSPD_C_RT_CTX_X20 0x8 78 #define TSPD_C_RT_CTX_X21 0x10 79 #define TSPD_C_RT_CTX_X22 0x18 80 #define TSPD_C_RT_CTX_X23 0x20 81 #define TSPD_C_RT_CTX_X24 0x28 82 #define TSPD_C_RT_CTX_X25 0x30 83 #define TSPD_C_RT_CTX_X26 0x38 84 #define TSPD_C_RT_CTX_X27 0x40 85 #define TSPD_C_RT_CTX_X28 0x48 86 #define TSPD_C_RT_CTX_X29 0x50 87 #define TSPD_C_RT_CTX_X30 0x58 88 #define TSPD_C_RT_CTX_SIZE 0x60 89 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) 90 91 #ifndef __ASSEMBLY__ 92 93 #include <cassert.h> 94 #include <stdint.h> 95 96 /* AArch64 callee saved general purpose register context structure. */ 97 DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); 98 99 /* 100 * Compile time assertion to ensure that both the compiler and linker 101 * have the same double word aligned view of the size of the C runtime 102 * register context. 103 */ 104 CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 105 assert_spd_c_rt_regs_size_mismatch); 106 107 /******************************************************************************* 108 * Structure which helps the SPD to maintain the per-cpu state of the SP. 109 * 'state' - collection of flags to track SP state e.g. on/off 110 * 'mpidr' - mpidr to associate a context with a cpu 111 * 'c_rt_ctx' - stack address to restore C runtime context from after returning 112 * from a synchronous entry into the SP. 113 * 'cpu_ctx' - space to maintain SP architectural state 114 ******************************************************************************/ 115 typedef struct tsp_context { 116 uint32_t state; 117 uint64_t mpidr; 118 uint64_t c_rt_ctx; 119 cpu_context_t cpu_ctx; 120 } tsp_context_t; 121 122 /* TSPD power management handlers */ 123 extern const spd_pm_ops_t tspd_pm; 124 125 /******************************************************************************* 126 * Forward declarations 127 ******************************************************************************/ 128 struct entry_info; 129 130 /******************************************************************************* 131 * Function & Data prototypes 132 ******************************************************************************/ 133 extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); 134 extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 135 extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); 136 extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); 137 extern int32_t tspd_init_secure_context(uint64_t entrypoint, 138 uint32_t rw, 139 uint64_t mpidr, 140 tsp_context_t *tsp_ctx); 141 extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 142 extern struct entry_info *tsp_entry_info; 143 #endif /*__ASSEMBLY__*/ 144 145 #endif /* __TSPD_PRIVATE_H__ */ 146