xref: /rk3399_ARM-atf/services/spd/tspd/tspd_private.h (revision 5f0cdb059d7d5c3a8a834074a7f236b85d014dde)
1375f538aSAchin Gupta /*
2375f538aSAchin Gupta  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3375f538aSAchin Gupta  *
4375f538aSAchin Gupta  * Redistribution and use in source and binary forms, with or without
5375f538aSAchin Gupta  * modification, are permitted provided that the following conditions are met:
6375f538aSAchin Gupta  *
7375f538aSAchin Gupta  * Redistributions of source code must retain the above copyright notice, this
8375f538aSAchin Gupta  * list of conditions and the following disclaimer.
9375f538aSAchin Gupta  *
10375f538aSAchin Gupta  * Redistributions in binary form must reproduce the above copyright notice,
11375f538aSAchin Gupta  * this list of conditions and the following disclaimer in the documentation
12375f538aSAchin Gupta  * and/or other materials provided with the distribution.
13375f538aSAchin Gupta  *
14375f538aSAchin Gupta  * Neither the name of ARM nor the names of its contributors may be used
15375f538aSAchin Gupta  * to endorse or promote products derived from this software without specific
16375f538aSAchin Gupta  * prior written permission.
17375f538aSAchin Gupta  *
18375f538aSAchin Gupta  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19375f538aSAchin Gupta  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20375f538aSAchin Gupta  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21375f538aSAchin Gupta  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22375f538aSAchin Gupta  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23375f538aSAchin Gupta  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24375f538aSAchin Gupta  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25375f538aSAchin Gupta  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26375f538aSAchin Gupta  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27375f538aSAchin Gupta  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28375f538aSAchin Gupta  * POSSIBILITY OF SUCH DAMAGE.
29375f538aSAchin Gupta  */
30375f538aSAchin Gupta 
3197043ac9SDan Handley #ifndef __TSPD_PRIVATE_H__
3297043ac9SDan Handley #define __TSPD_PRIVATE_H__
33375f538aSAchin Gupta 
34375f538aSAchin Gupta #include <arch.h>
3597043ac9SDan Handley #include <context.h>
36b44a4435SAchin Gupta #include <interrupt_mgmt.h>
37*5f0cdb05SDan Handley #include <platform_def.h>
38375f538aSAchin Gupta #include <psci.h>
39375f538aSAchin Gupta 
40375f538aSAchin Gupta /*******************************************************************************
41375f538aSAchin Gupta  * Secure Payload PM state information e.g. SP is suspended, uninitialised etc
423ee8a164SAchin Gupta  * and macros to access the state information in the per-cpu 'state' flags
43375f538aSAchin Gupta  ******************************************************************************/
443ee8a164SAchin Gupta #define TSP_PSTATE_OFF		0
453ee8a164SAchin Gupta #define TSP_PSTATE_ON		1
463ee8a164SAchin Gupta #define TSP_PSTATE_SUSPEND	2
473ee8a164SAchin Gupta #define TSP_PSTATE_SHIFT	0
483ee8a164SAchin Gupta #define TSP_PSTATE_MASK	0x3
493ee8a164SAchin Gupta #define get_tsp_pstate(state)	((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK)
503ee8a164SAchin Gupta #define clr_tsp_pstate(state)	(state &= ~(TSP_PSTATE_MASK \
513ee8a164SAchin Gupta 					    << TSP_PSTATE_SHIFT))
523ee8a164SAchin Gupta #define set_tsp_pstate(st, pst)	do {					       \
533ee8a164SAchin Gupta 					clr_tsp_pstate(st);		       \
543ee8a164SAchin Gupta 					st |= (pst & TSP_PSTATE_MASK) <<       \
553ee8a164SAchin Gupta 						TSP_PSTATE_SHIFT;	       \
563ee8a164SAchin Gupta 				} while (0);
573ee8a164SAchin Gupta 
583ee8a164SAchin Gupta 
593ee8a164SAchin Gupta /*
603ee8a164SAchin Gupta  * This flag is used by the TSPD to determine if the TSP is servicing a standard
613ee8a164SAchin Gupta  * SMC request prior to programming the next entry into the TSP e.g. if TSP
623ee8a164SAchin Gupta  * execution is preempted by a non-secure interrupt and handed control to the
633ee8a164SAchin Gupta  * normal world. If another request which is distinct from what the TSP was
643ee8a164SAchin Gupta  * previously doing arrives, then this flag will be help the TSPD to either
653ee8a164SAchin Gupta  * reject the new request or service it while ensuring that the previous context
663ee8a164SAchin Gupta  * is not corrupted.
673ee8a164SAchin Gupta  */
683ee8a164SAchin Gupta #define STD_SMC_ACTIVE_FLAG_SHIFT	2
693ee8a164SAchin Gupta #define STD_SMC_ACTIVE_FLAG_MASK	1
703ee8a164SAchin Gupta #define get_std_smc_active_flag(state)	((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \
713ee8a164SAchin Gupta 					 & STD_SMC_ACTIVE_FLAG_MASK)
723ee8a164SAchin Gupta #define set_std_smc_active_flag(state)	(state |=                             \
733ee8a164SAchin Gupta 					 1 << STD_SMC_ACTIVE_FLAG_SHIFT)
743ee8a164SAchin Gupta #define clr_std_smc_active_flag(state)	(state &=                             \
753ee8a164SAchin Gupta 					 ~(STD_SMC_ACTIVE_FLAG_MASK           \
763ee8a164SAchin Gupta 					   << STD_SMC_ACTIVE_FLAG_SHIFT))
77375f538aSAchin Gupta 
78375f538aSAchin Gupta /*******************************************************************************
79375f538aSAchin Gupta  * Secure Payload execution state information i.e. aarch32 or aarch64
80375f538aSAchin Gupta  ******************************************************************************/
81375f538aSAchin Gupta #define TSP_AARCH32		MODE_RW_32
82375f538aSAchin Gupta #define TSP_AARCH64		MODE_RW_64
83375f538aSAchin Gupta 
84375f538aSAchin Gupta /*******************************************************************************
85375f538aSAchin Gupta  * The SPD should know the type of Secure Payload.
86375f538aSAchin Gupta  ******************************************************************************/
87375f538aSAchin Gupta #define TSP_TYPE_UP		PSCI_TOS_NOT_UP_MIG_CAP
88375f538aSAchin Gupta #define TSP_TYPE_UPM		PSCI_TOS_UP_MIG_CAP
89375f538aSAchin Gupta #define TSP_TYPE_MP		PSCI_TOS_NOT_PRESENT_MP
90375f538aSAchin Gupta 
91375f538aSAchin Gupta /*******************************************************************************
92375f538aSAchin Gupta  * Secure Payload migrate type information as known to the SPD. We assume that
93375f538aSAchin Gupta  * the SPD is dealing with an MP Secure Payload.
94375f538aSAchin Gupta  ******************************************************************************/
95375f538aSAchin Gupta #define TSP_MIGRATE_INFO		TSP_TYPE_MP
96375f538aSAchin Gupta 
97375f538aSAchin Gupta /*******************************************************************************
98375f538aSAchin Gupta  * Number of cpus that the present on this platform. TODO: Rely on a topology
99375f538aSAchin Gupta  * tree to determine this in the future to avoid assumptions about mpidr
100375f538aSAchin Gupta  * allocation
101375f538aSAchin Gupta  ******************************************************************************/
102375f538aSAchin Gupta #define TSPD_CORE_COUNT		PLATFORM_CORE_COUNT
103375f538aSAchin Gupta 
104375f538aSAchin Gupta /*******************************************************************************
105375f538aSAchin Gupta  * Constants that allow assembler code to preserve callee-saved registers of the
106375f538aSAchin Gupta  * C runtime context while performing a security state switch.
107375f538aSAchin Gupta  ******************************************************************************/
108375f538aSAchin Gupta #define TSPD_C_RT_CTX_X19		0x0
109375f538aSAchin Gupta #define TSPD_C_RT_CTX_X20		0x8
110375f538aSAchin Gupta #define TSPD_C_RT_CTX_X21		0x10
111375f538aSAchin Gupta #define TSPD_C_RT_CTX_X22		0x18
112375f538aSAchin Gupta #define TSPD_C_RT_CTX_X23		0x20
113375f538aSAchin Gupta #define TSPD_C_RT_CTX_X24		0x28
114375f538aSAchin Gupta #define TSPD_C_RT_CTX_X25		0x30
115375f538aSAchin Gupta #define TSPD_C_RT_CTX_X26		0x38
116375f538aSAchin Gupta #define TSPD_C_RT_CTX_X27		0x40
117375f538aSAchin Gupta #define TSPD_C_RT_CTX_X28		0x48
118375f538aSAchin Gupta #define TSPD_C_RT_CTX_X29		0x50
119375f538aSAchin Gupta #define TSPD_C_RT_CTX_X30		0x58
120375f538aSAchin Gupta #define TSPD_C_RT_CTX_SIZE		0x60
121375f538aSAchin Gupta #define TSPD_C_RT_CTX_ENTRIES		(TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT)
122375f538aSAchin Gupta 
123375f538aSAchin Gupta #ifndef __ASSEMBLY__
124375f538aSAchin Gupta 
12597043ac9SDan Handley #include <cassert.h>
12697043ac9SDan Handley #include <stdint.h>
12797043ac9SDan Handley 
128239b04faSSoby Mathew /*
129239b04faSSoby Mathew  * The number of arguments to save during a SMC call for TSP.
130239b04faSSoby Mathew  * Currently only x1 and x2 are used by TSP.
131239b04faSSoby Mathew  */
132239b04faSSoby Mathew #define TSP_NUM_ARGS	0x2
133239b04faSSoby Mathew 
134375f538aSAchin Gupta /* AArch64 callee saved general purpose register context structure. */
135375f538aSAchin Gupta DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
136375f538aSAchin Gupta 
137375f538aSAchin Gupta /*
138375f538aSAchin Gupta  * Compile time assertion to ensure that both the compiler and linker
139375f538aSAchin Gupta  * have the same double word aligned view of the size of the C runtime
140375f538aSAchin Gupta  * register context.
141375f538aSAchin Gupta  */
142fb037bfbSDan Handley CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),	\
143375f538aSAchin Gupta 	assert_spd_c_rt_regs_size_mismatch);
144375f538aSAchin Gupta 
145375f538aSAchin Gupta /*******************************************************************************
146375f538aSAchin Gupta  * Structure which helps the SPD to maintain the per-cpu state of the SP.
147b44a4435SAchin Gupta  * 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been
148b44a4435SAchin Gupta  *                    preempted.
149b44a4435SAchin Gupta  * 'saved_elr_el3'  - temporary copy to allow FIQ handling when the TSP has been
150b44a4435SAchin Gupta  *                    preempted.
151375f538aSAchin Gupta  * 'state'          - collection of flags to track SP state e.g. on/off
152375f538aSAchin Gupta  * 'mpidr'          - mpidr to associate a context with a cpu
153b44a4435SAchin Gupta  * 'c_rt_ctx'       - stack address to restore C runtime context from after
154b44a4435SAchin Gupta  *                    returning from a synchronous entry into the SP.
155375f538aSAchin Gupta  * 'cpu_ctx'        - space to maintain SP architectural state
156239b04faSSoby Mathew  * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations
157239b04faSSoby Mathew  *                    which will queried using the TSP_GET_ARGS SMC by TSP.
158375f538aSAchin Gupta  ******************************************************************************/
159fb037bfbSDan Handley typedef struct tsp_context {
160b44a4435SAchin Gupta 	uint64_t saved_elr_el3;
161b44a4435SAchin Gupta 	uint32_t saved_spsr_el3;
162375f538aSAchin Gupta 	uint32_t state;
163375f538aSAchin Gupta 	uint64_t mpidr;
164375f538aSAchin Gupta 	uint64_t c_rt_ctx;
165fb037bfbSDan Handley 	cpu_context_t cpu_ctx;
166239b04faSSoby Mathew 	uint64_t saved_tsp_args[TSP_NUM_ARGS];
167fb037bfbSDan Handley } tsp_context_t;
168375f538aSAchin Gupta 
169239b04faSSoby Mathew /* Helper macros to store and retrieve tsp args from tsp_context */
170239b04faSSoby Mathew #define store_tsp_args(tsp_ctx, x1, x2)		do {\
171239b04faSSoby Mathew 				tsp_ctx->saved_tsp_args[0] = x1;\
172239b04faSSoby Mathew 				tsp_ctx->saved_tsp_args[1] = x2;\
173239b04faSSoby Mathew 			} while (0)
174239b04faSSoby Mathew 
175239b04faSSoby Mathew #define get_tsp_args(tsp_ctx, x1, x2)	do {\
176239b04faSSoby Mathew 				x1 = tsp_ctx->saved_tsp_args[0];\
177239b04faSSoby Mathew 				x2 = tsp_ctx->saved_tsp_args[1];\
178239b04faSSoby Mathew 			} while (0)
179239b04faSSoby Mathew 
1807f366605SJeenu Viswambharan /* TSPD power management handlers */
181fb037bfbSDan Handley extern const spd_pm_ops_t tspd_pm;
1827f366605SJeenu Viswambharan 
183375f538aSAchin Gupta /*******************************************************************************
18497043ac9SDan Handley  * Forward declarations
18597043ac9SDan Handley  ******************************************************************************/
186399fb08fSAndrew Thoelke struct tsp_vectors;
18797043ac9SDan Handley 
18897043ac9SDan Handley /*******************************************************************************
189375f538aSAchin Gupta  * Function & Data prototypes
190375f538aSAchin Gupta  ******************************************************************************/
191c6bc0710SDan Handley uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
192c6bc0710SDan Handley void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
193c6bc0710SDan Handley uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
194c6bc0710SDan Handley void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
195c6bc0710SDan Handley int32_t tspd_init_secure_context(uint64_t entrypoint,
196375f538aSAchin Gupta 					uint32_t rw,
197375f538aSAchin Gupta 					uint64_t mpidr,
198fb037bfbSDan Handley 					tsp_context_t *tsp_ctx);
199fb037bfbSDan Handley extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
200399fb08fSAndrew Thoelke extern struct tsp_vectors *tsp_vectors;
201375f538aSAchin Gupta #endif /*__ASSEMBLY__*/
202375f538aSAchin Gupta 
20397043ac9SDan Handley #endif /* __TSPD_PRIVATE_H__ */
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