1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context_mgmt.h> 35 #include <debug.h> 36 #include <platform.h> 37 #include <tsp.h> 38 #include "tspd_private.h" 39 40 /******************************************************************************* 41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions 42 * needed. Nothing at the moment. 43 ******************************************************************************/ 44 static void tspd_cpu_on_handler(uint64_t target_cpu) 45 { 46 } 47 48 /******************************************************************************* 49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions 50 * needed 51 ******************************************************************************/ 52 static int32_t tspd_cpu_off_handler(uint64_t cookie) 53 { 54 int32_t rc = 0; 55 uint64_t mpidr = read_mpidr(); 56 uint32_t linear_id = platform_get_core_pos(mpidr); 57 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 58 59 assert(tsp_vectors); 60 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 61 62 /* Program the entry point and enter the TSP */ 63 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); 64 rc = tspd_synchronous_sp_entry(tsp_ctx); 65 66 /* 67 * Read the response from the TSP. A non-zero return means that 68 * something went wrong while communicating with the TSP. 69 */ 70 if (rc != 0) 71 panic(); 72 73 /* 74 * Reset TSP's context for a fresh start when this cpu is turned on 75 * subsequently. 76 */ 77 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 78 79 return 0; 80 } 81 82 /******************************************************************************* 83 * This cpu is being suspended. S-EL1 state must have been saved in the 84 * resident cpu (mpidr format) if it is a UP/UP migratable TSP. 85 ******************************************************************************/ 86 static void tspd_cpu_suspend_handler(uint64_t power_state) 87 { 88 int32_t rc = 0; 89 uint64_t mpidr = read_mpidr(); 90 uint32_t linear_id = platform_get_core_pos(mpidr); 91 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 92 93 assert(tsp_vectors); 94 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 95 96 /* Program the entry point, power_state parameter and enter the TSP */ 97 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 98 CTX_GPREG_X0, 99 power_state); 100 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); 101 rc = tspd_synchronous_sp_entry(tsp_ctx); 102 103 /* 104 * Read the response from the TSP. A non-zero return means that 105 * something went wrong while communicating with the TSP. 106 */ 107 if (rc != 0) 108 panic(); 109 110 /* Update its context to reflect the state the TSP is in */ 111 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); 112 } 113 114 /******************************************************************************* 115 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits 116 * before passing control back to the Secure Monitor. Entry in S-El1 is done 117 * after initialising minimal architectural state that guarantees safe 118 * execution. 119 ******************************************************************************/ 120 static void tspd_cpu_on_finish_handler(uint64_t cookie) 121 { 122 int32_t rc = 0; 123 uint64_t mpidr = read_mpidr(); 124 uint32_t linear_id = platform_get_core_pos(mpidr); 125 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 126 entry_point_info_t tsp_on_entrypoint; 127 128 assert(tsp_vectors); 129 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); 130 131 tspd_init_tsp_ep_state(&tsp_on_entrypoint, 132 TSP_AARCH64, 133 (uint64_t) &tsp_vectors->cpu_on_entry, 134 tsp_ctx); 135 136 /* Initialise this cpu's secure context */ 137 cm_init_context(mpidr, &tsp_on_entrypoint); 138 139 /* Enter the TSP */ 140 rc = tspd_synchronous_sp_entry(tsp_ctx); 141 142 /* 143 * Read the response from the TSP. A non-zero return means that 144 * something went wrong while communicating with the SP. 145 */ 146 if (rc != 0) 147 panic(); 148 149 /* Update its context to reflect the state the SP is in */ 150 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 151 } 152 153 /******************************************************************************* 154 * This cpu has resumed from suspend. The SPD saved the TSP context when it 155 * completed the preceding suspend call. Use that context to program an entry 156 * into the TSP to allow it to do any remaining book keeping 157 ******************************************************************************/ 158 static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level) 159 { 160 int32_t rc = 0; 161 uint64_t mpidr = read_mpidr(); 162 uint32_t linear_id = platform_get_core_pos(mpidr); 163 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 164 165 assert(tsp_vectors); 166 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); 167 168 /* Program the entry point, suspend_level and enter the SP */ 169 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 170 CTX_GPREG_X0, 171 suspend_level); 172 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); 173 rc = tspd_synchronous_sp_entry(tsp_ctx); 174 175 /* 176 * Read the response from the TSP. A non-zero return means that 177 * something went wrong while communicating with the TSP. 178 */ 179 if (rc != 0) 180 panic(); 181 182 /* Update its context to reflect the state the SP is in */ 183 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 184 } 185 186 /******************************************************************************* 187 * Return the type of TSP the TSPD is dealing with. Report the current resident 188 * cpu (mpidr format) if it is a UP/UP migratable TSP. 189 ******************************************************************************/ 190 static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) 191 { 192 return TSP_MIGRATE_INFO; 193 } 194 195 /******************************************************************************* 196 * Structure populated by the TSP Dispatcher to be given a chance to perform any 197 * TSP bookkeeping before PSCI executes a power mgmt. operation. 198 ******************************************************************************/ 199 const spd_pm_ops_t tspd_pm = { 200 tspd_cpu_on_handler, 201 tspd_cpu_off_handler, 202 tspd_cpu_suspend_handler, 203 tspd_cpu_on_finish_handler, 204 tspd_cpu_suspend_finish_handler, 205 NULL, 206 tspd_cpu_migrate_info 207 }; 208 209