1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl32/tsp/tsp.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <lib/el3_runtime/context_mgmt.h> 14 #include <plat/common/platform.h> 15 16 #include "tspd_private.h" 17 18 /******************************************************************************* 19 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions 20 * needed. Nothing at the moment. 21 ******************************************************************************/ 22 static void tspd_cpu_on_handler(u_register_t target_cpu) 23 { 24 } 25 26 /******************************************************************************* 27 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions 28 * needed 29 ******************************************************************************/ 30 static int32_t tspd_cpu_off_handler(u_register_t unused) 31 { 32 int32_t rc = 0; 33 uint32_t linear_id = plat_my_core_pos(); 34 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 35 36 assert(tsp_vectors); 37 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 38 39 /* 40 * Abort any preempted SMC request before overwriting the SECURE 41 * context. 42 */ 43 tspd_abort_preempted_smc(tsp_ctx); 44 45 /* Program the entry point and enter the TSP */ 46 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); 47 rc = tspd_synchronous_sp_entry(tsp_ctx); 48 49 /* 50 * Read the response from the TSP. A non-zero return means that 51 * something went wrong while communicating with the TSP. 52 */ 53 if (rc != 0) 54 panic(); 55 56 /* 57 * Reset TSP's context for a fresh start when this cpu is turned on 58 * subsequently. 59 */ 60 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 61 62 return 0; 63 } 64 65 /******************************************************************************* 66 * This cpu is being suspended. S-EL1 state must have been saved in the 67 * resident cpu (mpidr format) if it is a UP/UP migratable TSP. 68 ******************************************************************************/ 69 static void tspd_cpu_suspend_handler(u_register_t max_off_pwrlvl) 70 { 71 int32_t rc = 0; 72 uint32_t linear_id = plat_my_core_pos(); 73 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 74 75 assert(tsp_vectors); 76 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 77 78 /* 79 * Abort any preempted SMC request before overwriting the SECURE 80 * context. 81 */ 82 tspd_abort_preempted_smc(tsp_ctx); 83 84 /* Program the entry point and enter the TSP */ 85 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); 86 rc = tspd_synchronous_sp_entry(tsp_ctx); 87 88 /* 89 * Read the response from the TSP. A non-zero return means that 90 * something went wrong while communicating with the TSP. 91 */ 92 if (rc) 93 panic(); 94 95 /* Update its context to reflect the state the TSP is in */ 96 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); 97 } 98 99 /******************************************************************************* 100 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits 101 * before passing control back to the Secure Monitor. Entry in S-EL1 is done 102 * after initialising minimal architectural state that guarantees safe 103 * execution. 104 ******************************************************************************/ 105 static void tspd_cpu_on_finish_handler(u_register_t unused) 106 { 107 int32_t rc = 0; 108 uint32_t linear_id = plat_my_core_pos(); 109 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 110 entry_point_info_t tsp_on_entrypoint; 111 112 assert(tsp_vectors); 113 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); 114 115 tspd_init_tsp_ep_state(&tsp_on_entrypoint, 116 TSP_AARCH64, 117 (uint64_t) &tsp_vectors->cpu_on_entry, 118 tsp_ctx); 119 120 /* Initialise this cpu's secure context */ 121 cm_init_my_context(&tsp_on_entrypoint); 122 123 #if TSP_NS_INTR_ASYNC_PREEMPT 124 /* 125 * Disable the NS interrupt locally since it will be enabled globally 126 * within cm_init_my_context. 127 */ 128 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 129 #endif 130 131 /* Enter the TSP */ 132 rc = tspd_synchronous_sp_entry(tsp_ctx); 133 134 /* 135 * Read the response from the TSP. A non-zero return means that 136 * something went wrong while communicating with the SP. 137 */ 138 if (rc != 0) 139 panic(); 140 141 /* Update its context to reflect the state the SP is in */ 142 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 143 } 144 145 /******************************************************************************* 146 * This cpu has resumed from suspend. The SPD saved the TSP context when it 147 * completed the preceding suspend call. Use that context to program an entry 148 * into the TSP to allow it to do any remaining book keeping 149 ******************************************************************************/ 150 static void tspd_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl) 151 { 152 int32_t rc = 0; 153 uint32_t linear_id = plat_my_core_pos(); 154 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 155 156 assert(tsp_vectors); 157 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); 158 159 /* Program the entry point, max_off_pwrlvl and enter the SP */ 160 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 161 CTX_GPREG_X0, 162 max_off_pwrlvl); 163 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); 164 rc = tspd_synchronous_sp_entry(tsp_ctx); 165 166 /* 167 * Read the response from the TSP. A non-zero return means that 168 * something went wrong while communicating with the TSP. 169 */ 170 if (rc != 0) 171 panic(); 172 173 /* Update its context to reflect the state the SP is in */ 174 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 175 } 176 177 /******************************************************************************* 178 * Return the type of TSP the TSPD is dealing with. Report the current resident 179 * cpu (mpidr format) if it is a UP/UP migratable TSP. 180 ******************************************************************************/ 181 static int32_t tspd_cpu_migrate_info(u_register_t *resident_cpu) 182 { 183 return TSP_MIGRATE_INFO; 184 } 185 186 /******************************************************************************* 187 * System is about to be switched off. Allow the TSPD/TSP to perform 188 * any actions needed. 189 ******************************************************************************/ 190 static void tspd_system_off(void) 191 { 192 uint32_t linear_id = plat_my_core_pos(); 193 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 194 195 assert(tsp_vectors); 196 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 197 198 /* 199 * Abort any preempted SMC request before overwriting the SECURE 200 * context. 201 */ 202 tspd_abort_preempted_smc(tsp_ctx); 203 204 /* Program the entry point */ 205 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); 206 207 /* Enter the TSP. We do not care about the return value because we 208 * must continue the shutdown anyway */ 209 tspd_synchronous_sp_entry(tsp_ctx); 210 } 211 212 /******************************************************************************* 213 * System is about to be reset. Allow the TSPD/TSP to perform 214 * any actions needed. 215 ******************************************************************************/ 216 static void tspd_system_reset(void) 217 { 218 uint32_t linear_id = plat_my_core_pos(); 219 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 220 221 assert(tsp_vectors); 222 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 223 224 /* 225 * Abort any preempted SMC request before overwriting the SECURE 226 * context. 227 */ 228 tspd_abort_preempted_smc(tsp_ctx); 229 230 /* Program the entry point */ 231 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); 232 233 /* 234 * Enter the TSP. We do not care about the return value because we 235 * must continue the reset anyway 236 */ 237 tspd_synchronous_sp_entry(tsp_ctx); 238 } 239 240 /******************************************************************************* 241 * Structure populated by the TSP Dispatcher to be given a chance to perform any 242 * TSP bookkeeping before PSCI executes a power mgmt. operation. 243 ******************************************************************************/ 244 const spd_pm_ops_t tspd_pm = { 245 .svc_on = tspd_cpu_on_handler, 246 .svc_off = tspd_cpu_off_handler, 247 .svc_suspend = tspd_cpu_suspend_handler, 248 .svc_on_finish = tspd_cpu_on_finish_handler, 249 .svc_suspend_finish = tspd_cpu_suspend_finish_handler, 250 .svc_migrate = NULL, 251 .svc_migrate_info = tspd_cpu_migrate_info, 252 .svc_system_off = tspd_system_off, 253 .svc_system_reset = tspd_system_reset 254 }; 255