1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context_mgmt.h> 35 #include <debug.h> 36 #include <platform.h> 37 #include <tsp.h> 38 #include "tspd_private.h" 39 40 /******************************************************************************* 41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions 42 * needed. Nothing at the moment. 43 ******************************************************************************/ 44 static void tspd_cpu_on_handler(uint64_t target_cpu) 45 { 46 } 47 48 /******************************************************************************* 49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions 50 * needed 51 ******************************************************************************/ 52 static int32_t tspd_cpu_off_handler(uint64_t unused) 53 { 54 int32_t rc = 0; 55 uint32_t linear_id = plat_my_core_pos(); 56 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 57 58 assert(tsp_vectors); 59 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 60 61 /* 62 * Abort any preempted SMC request before overwriting the SECURE 63 * context. 64 */ 65 tspd_abort_preempted_smc(tsp_ctx); 66 67 /* Program the entry point and enter the TSP */ 68 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); 69 rc = tspd_synchronous_sp_entry(tsp_ctx); 70 71 /* 72 * Read the response from the TSP. A non-zero return means that 73 * something went wrong while communicating with the TSP. 74 */ 75 if (rc != 0) 76 panic(); 77 78 /* 79 * Reset TSP's context for a fresh start when this cpu is turned on 80 * subsequently. 81 */ 82 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 83 84 return 0; 85 } 86 87 /******************************************************************************* 88 * This cpu is being suspended. S-EL1 state must have been saved in the 89 * resident cpu (mpidr format) if it is a UP/UP migratable TSP. 90 ******************************************************************************/ 91 static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl) 92 { 93 int32_t rc = 0; 94 uint32_t linear_id = plat_my_core_pos(); 95 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 96 97 assert(tsp_vectors); 98 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 99 100 /* 101 * Abort any preempted SMC request before overwriting the SECURE 102 * context. 103 */ 104 tspd_abort_preempted_smc(tsp_ctx); 105 106 /* Program the entry point and enter the TSP */ 107 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); 108 rc = tspd_synchronous_sp_entry(tsp_ctx); 109 110 /* 111 * Read the response from the TSP. A non-zero return means that 112 * something went wrong while communicating with the TSP. 113 */ 114 if (rc) 115 panic(); 116 117 /* Update its context to reflect the state the TSP is in */ 118 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); 119 } 120 121 /******************************************************************************* 122 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits 123 * before passing control back to the Secure Monitor. Entry in S-EL1 is done 124 * after initialising minimal architectural state that guarantees safe 125 * execution. 126 ******************************************************************************/ 127 static void tspd_cpu_on_finish_handler(uint64_t unused) 128 { 129 int32_t rc = 0; 130 uint32_t linear_id = plat_my_core_pos(); 131 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 132 entry_point_info_t tsp_on_entrypoint; 133 134 assert(tsp_vectors); 135 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); 136 137 tspd_init_tsp_ep_state(&tsp_on_entrypoint, 138 TSP_AARCH64, 139 (uint64_t) &tsp_vectors->cpu_on_entry, 140 tsp_ctx); 141 142 /* Initialise this cpu's secure context */ 143 cm_init_my_context(&tsp_on_entrypoint); 144 145 #if TSP_NS_INTR_ASYNC_PREEMPT 146 /* 147 * Disable the NS interrupt locally since it will be enabled globally 148 * within cm_init_my_context. 149 */ 150 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 151 #endif 152 153 /* Enter the TSP */ 154 rc = tspd_synchronous_sp_entry(tsp_ctx); 155 156 /* 157 * Read the response from the TSP. A non-zero return means that 158 * something went wrong while communicating with the SP. 159 */ 160 if (rc != 0) 161 panic(); 162 163 /* Update its context to reflect the state the SP is in */ 164 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 165 } 166 167 /******************************************************************************* 168 * This cpu has resumed from suspend. The SPD saved the TSP context when it 169 * completed the preceding suspend call. Use that context to program an entry 170 * into the TSP to allow it to do any remaining book keeping 171 ******************************************************************************/ 172 static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) 173 { 174 int32_t rc = 0; 175 uint32_t linear_id = plat_my_core_pos(); 176 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 177 178 assert(tsp_vectors); 179 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); 180 181 /* Program the entry point, max_off_pwrlvl and enter the SP */ 182 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 183 CTX_GPREG_X0, 184 max_off_pwrlvl); 185 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); 186 rc = tspd_synchronous_sp_entry(tsp_ctx); 187 188 /* 189 * Read the response from the TSP. A non-zero return means that 190 * something went wrong while communicating with the TSP. 191 */ 192 if (rc != 0) 193 panic(); 194 195 /* Update its context to reflect the state the SP is in */ 196 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 197 } 198 199 /******************************************************************************* 200 * Return the type of TSP the TSPD is dealing with. Report the current resident 201 * cpu (mpidr format) if it is a UP/UP migratable TSP. 202 ******************************************************************************/ 203 static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) 204 { 205 return TSP_MIGRATE_INFO; 206 } 207 208 /******************************************************************************* 209 * System is about to be switched off. Allow the TSPD/TSP to perform 210 * any actions needed. 211 ******************************************************************************/ 212 static void tspd_system_off(void) 213 { 214 uint32_t linear_id = plat_my_core_pos(); 215 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 216 217 assert(tsp_vectors); 218 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 219 220 /* 221 * Abort any preempted SMC request before overwriting the SECURE 222 * context. 223 */ 224 tspd_abort_preempted_smc(tsp_ctx); 225 226 /* Program the entry point */ 227 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); 228 229 /* Enter the TSP. We do not care about the return value because we 230 * must continue the shutdown anyway */ 231 tspd_synchronous_sp_entry(tsp_ctx); 232 } 233 234 /******************************************************************************* 235 * System is about to be reset. Allow the TSPD/TSP to perform 236 * any actions needed. 237 ******************************************************************************/ 238 static void tspd_system_reset(void) 239 { 240 uint32_t linear_id = plat_my_core_pos(); 241 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 242 243 assert(tsp_vectors); 244 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 245 246 /* 247 * Abort any preempted SMC request before overwriting the SECURE 248 * context. 249 */ 250 tspd_abort_preempted_smc(tsp_ctx); 251 252 /* Program the entry point */ 253 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); 254 255 /* 256 * Enter the TSP. We do not care about the return value because we 257 * must continue the reset anyway 258 */ 259 tspd_synchronous_sp_entry(tsp_ctx); 260 } 261 262 /******************************************************************************* 263 * Structure populated by the TSP Dispatcher to be given a chance to perform any 264 * TSP bookkeeping before PSCI executes a power mgmt. operation. 265 ******************************************************************************/ 266 const spd_pm_ops_t tspd_pm = { 267 .svc_on = tspd_cpu_on_handler, 268 .svc_off = tspd_cpu_off_handler, 269 .svc_suspend = tspd_cpu_suspend_handler, 270 .svc_on_finish = tspd_cpu_on_finish_handler, 271 .svc_suspend_finish = tspd_cpu_suspend_finish_handler, 272 .svc_migrate = NULL, 273 .svc_migrate_info = tspd_cpu_migrate_info, 274 .svc_system_off = tspd_system_off, 275 .svc_system_reset = tspd_system_reset 276 }; 277