1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context_mgmt.h> 35 #include <debug.h> 36 #include <platform.h> 37 #include <tsp.h> 38 #include "tspd_private.h" 39 40 /******************************************************************************* 41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions 42 * needed. Nothing at the moment. 43 ******************************************************************************/ 44 static void tspd_cpu_on_handler(uint64_t target_cpu) 45 { 46 } 47 48 /******************************************************************************* 49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions 50 * needed 51 ******************************************************************************/ 52 static int32_t tspd_cpu_off_handler(uint64_t unused) 53 { 54 int32_t rc = 0; 55 uint32_t linear_id = plat_my_core_pos(); 56 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 57 58 assert(tsp_vectors); 59 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 60 61 /* Program the entry point and enter the TSP */ 62 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); 63 rc = tspd_synchronous_sp_entry(tsp_ctx); 64 65 /* 66 * Read the response from the TSP. A non-zero return means that 67 * something went wrong while communicating with the TSP. 68 */ 69 if (rc != 0) 70 panic(); 71 72 /* 73 * Reset TSP's context for a fresh start when this cpu is turned on 74 * subsequently. 75 */ 76 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 77 78 return 0; 79 } 80 81 /******************************************************************************* 82 * This cpu is being suspended. S-EL1 state must have been saved in the 83 * resident cpu (mpidr format) if it is a UP/UP migratable TSP. 84 ******************************************************************************/ 85 static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl) 86 { 87 int32_t rc = 0; 88 uint32_t linear_id = plat_my_core_pos(); 89 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 90 91 assert(tsp_vectors); 92 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 93 94 /* Program the entry point and enter the TSP */ 95 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); 96 rc = tspd_synchronous_sp_entry(tsp_ctx); 97 98 /* 99 * Read the response from the TSP. A non-zero return means that 100 * something went wrong while communicating with the TSP. 101 */ 102 if (rc != 0) 103 panic(); 104 105 /* Update its context to reflect the state the TSP is in */ 106 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); 107 } 108 109 /******************************************************************************* 110 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits 111 * before passing control back to the Secure Monitor. Entry in S-El1 is done 112 * after initialising minimal architectural state that guarantees safe 113 * execution. 114 ******************************************************************************/ 115 static void tspd_cpu_on_finish_handler(uint64_t unused) 116 { 117 int32_t rc = 0; 118 uint32_t linear_id = plat_my_core_pos(); 119 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 120 entry_point_info_t tsp_on_entrypoint; 121 122 assert(tsp_vectors); 123 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); 124 125 tspd_init_tsp_ep_state(&tsp_on_entrypoint, 126 TSP_AARCH64, 127 (uint64_t) &tsp_vectors->cpu_on_entry, 128 tsp_ctx); 129 130 /* Initialise this cpu's secure context */ 131 cm_init_my_context(&tsp_on_entrypoint); 132 133 #if TSP_NS_INTR_ASYNC_PREEMPT 134 /* 135 * Disable the NS interrupt locally since it will be enabled globally 136 * within cm_init_my_context. 137 */ 138 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 139 #endif 140 141 /* Enter the TSP */ 142 rc = tspd_synchronous_sp_entry(tsp_ctx); 143 144 /* 145 * Read the response from the TSP. A non-zero return means that 146 * something went wrong while communicating with the SP. 147 */ 148 if (rc != 0) 149 panic(); 150 151 /* Update its context to reflect the state the SP is in */ 152 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 153 } 154 155 /******************************************************************************* 156 * This cpu has resumed from suspend. The SPD saved the TSP context when it 157 * completed the preceding suspend call. Use that context to program an entry 158 * into the TSP to allow it to do any remaining book keeping 159 ******************************************************************************/ 160 static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) 161 { 162 int32_t rc = 0; 163 uint32_t linear_id = plat_my_core_pos(); 164 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 165 166 assert(tsp_vectors); 167 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); 168 169 /* Program the entry point, max_off_pwrlvl and enter the SP */ 170 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), 171 CTX_GPREG_X0, 172 max_off_pwrlvl); 173 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); 174 rc = tspd_synchronous_sp_entry(tsp_ctx); 175 176 /* 177 * Read the response from the TSP. A non-zero return means that 178 * something went wrong while communicating with the TSP. 179 */ 180 if (rc != 0) 181 panic(); 182 183 /* Update its context to reflect the state the SP is in */ 184 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 185 } 186 187 /******************************************************************************* 188 * Return the type of TSP the TSPD is dealing with. Report the current resident 189 * cpu (mpidr format) if it is a UP/UP migratable TSP. 190 ******************************************************************************/ 191 static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) 192 { 193 return TSP_MIGRATE_INFO; 194 } 195 196 /******************************************************************************* 197 * System is about to be switched off. Allow the TSPD/TSP to perform 198 * any actions needed. 199 ******************************************************************************/ 200 static void tspd_system_off(void) 201 { 202 uint32_t linear_id = plat_my_core_pos(); 203 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 204 205 assert(tsp_vectors); 206 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 207 208 /* Program the entry point */ 209 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); 210 211 /* Enter the TSP. We do not care about the return value because we 212 * must continue the shutdown anyway */ 213 tspd_synchronous_sp_entry(tsp_ctx); 214 } 215 216 /******************************************************************************* 217 * System is about to be reset. Allow the TSPD/TSP to perform 218 * any actions needed. 219 ******************************************************************************/ 220 static void tspd_system_reset(void) 221 { 222 uint32_t linear_id = plat_my_core_pos(); 223 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 224 225 assert(tsp_vectors); 226 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); 227 228 /* Program the entry point */ 229 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); 230 231 /* Enter the TSP. We do not care about the return value because we 232 * must continue the reset anyway */ 233 tspd_synchronous_sp_entry(tsp_ctx); 234 } 235 236 /******************************************************************************* 237 * Structure populated by the TSP Dispatcher to be given a chance to perform any 238 * TSP bookkeeping before PSCI executes a power mgmt. operation. 239 ******************************************************************************/ 240 const spd_pm_ops_t tspd_pm = { 241 .svc_on = tspd_cpu_on_handler, 242 .svc_off = tspd_cpu_off_handler, 243 .svc_suspend = tspd_cpu_suspend_handler, 244 .svc_on_finish = tspd_cpu_on_finish_handler, 245 .svc_suspend_finish = tspd_cpu_suspend_finish_handler, 246 .svc_migrate = NULL, 247 .svc_migrate_info = tspd_cpu_migrate_info, 248 .svc_system_off = tspd_system_off, 249 .svc_system_reset = tspd_system_reset 250 }; 251