1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <string.h> 52 #include <tsp.h> 53 #include <uuid.h> 54 #include "tspd_private.h" 55 56 /******************************************************************************* 57 * Address of the entrypoint vector table in the Secure Payload. It is 58 * initialised once on the primary core after a cold boot. 59 ******************************************************************************/ 60 tsp_vectors_t *tsp_vectors; 61 62 /******************************************************************************* 63 * Array to keep track of per-cpu Secure Payload state 64 ******************************************************************************/ 65 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 66 67 68 /* TSP UID */ 69 DEFINE_SVC_UUID(tsp_uuid, 70 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 71 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); 72 73 int32_t tspd_init(void); 74 75 uint64_t tspd_handle_sp_preemption(void *handle) 76 { 77 cpu_context_t *ns_cpu_context; 78 assert(handle == cm_get_context(SECURE)); 79 cm_el1_sysregs_context_save(SECURE); 80 /* Get a reference to the non-secure context */ 81 ns_cpu_context = cm_get_context(NON_SECURE); 82 assert(ns_cpu_context); 83 84 /* 85 * Restore non-secure state. The secure system 86 * register context will be saved when required. 87 */ 88 cm_el1_sysregs_context_restore(NON_SECURE); 89 cm_set_next_eret_context(NON_SECURE); 90 91 SMC_RET1(ns_cpu_context, SMC_PREEMPTED); 92 } 93 /******************************************************************************* 94 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 95 * validates the interrupt and upon success arranges entry into the TSP at 96 * 'tsp_fiq_entry()' for handling the interrupt. 97 ******************************************************************************/ 98 static uint64_t tspd_sel1_interrupt_handler(uint32_t id, 99 uint32_t flags, 100 void *handle, 101 void *cookie) 102 { 103 uint32_t linear_id; 104 tsp_context_t *tsp_ctx; 105 106 /* Check the security state when the exception was generated */ 107 assert(get_interrupt_src_ss(flags) == NON_SECURE); 108 109 #if IMF_READ_INTERRUPT_ID 110 /* Check the security status of the interrupt */ 111 assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); 112 #endif 113 114 /* Sanity check the pointer to this cpu's context */ 115 assert(handle == cm_get_context(NON_SECURE)); 116 117 /* Save the non-secure context before entering the TSP */ 118 cm_el1_sysregs_context_save(NON_SECURE); 119 120 /* Get a reference to this cpu's TSP context */ 121 linear_id = plat_my_core_pos(); 122 tsp_ctx = &tspd_sp_context[linear_id]; 123 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 124 125 /* 126 * Determine if the TSP was previously preempted. Its last known 127 * context has to be preserved in this case. 128 * The TSP should return control to the TSPD after handling this 129 * FIQ. Preserve essential EL3 context to allow entry into the 130 * TSP at the FIQ entry point using the 'cpu_context' structure. 131 * There is no need to save the secure system register context 132 * since the TSP is supposed to preserve it during S-EL1 interrupt 133 * handling. 134 */ 135 if (get_std_smc_active_flag(tsp_ctx->state)) { 136 tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 137 CTX_SPSR_EL3); 138 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 139 CTX_ELR_EL3); 140 #if TSPD_ROUTE_IRQ_TO_EL3 141 /*Need to save the previously interrupted secure context */ 142 memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE); 143 #endif 144 } 145 146 cm_el1_sysregs_context_restore(SECURE); 147 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry, 148 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); 149 150 cm_set_next_eret_context(SECURE); 151 152 /* 153 * Tell the TSP that it has to handle an FIQ synchronously. Also the 154 * instruction in normal world where the interrupt was generated is 155 * passed for debugging purposes. It is safe to retrieve this address 156 * from ELR_EL3 as the secure context will not take effect until 157 * el3_exit(). 158 */ 159 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); 160 } 161 162 #if TSPD_ROUTE_IRQ_TO_EL3 163 /******************************************************************************* 164 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 165 * validates the interrupt and upon success arranges entry into the TSP at 166 * 'tsp_fiq_entry()' for handling the interrupt. 167 ******************************************************************************/ 168 static uint64_t tspd_ns_interrupt_handler(uint32_t id, 169 uint32_t flags, 170 void *handle, 171 void *cookie) 172 { 173 /* Check the security state when the exception was generated */ 174 assert(get_interrupt_src_ss(flags) == SECURE); 175 176 #if IMF_READ_INTERRUPT_ID 177 /* Check the security status of the interrupt */ 178 assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_NS); 179 #endif 180 /* 181 * Disable the routing of NS interrupts from secure world to EL3 while 182 * interrupted on this core. 183 */ 184 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 185 186 return tspd_handle_sp_preemption(handle); 187 } 188 #endif 189 190 /******************************************************************************* 191 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type 192 * (aarch32/aarch64) if not already known and initialises the context for entry 193 * into the SP for its initialisation. 194 ******************************************************************************/ 195 int32_t tspd_setup(void) 196 { 197 entry_point_info_t *tsp_ep_info; 198 uint32_t linear_id; 199 200 linear_id = plat_my_core_pos(); 201 202 /* 203 * Get information about the Secure Payload (BL32) image. Its 204 * absence is a critical failure. TODO: Add support to 205 * conditionally include the SPD service 206 */ 207 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 208 if (!tsp_ep_info) { 209 WARN("No TSP provided by BL2 boot loader, Booting device" 210 " without TSP initialization. SMC`s destined for TSP" 211 " will return SMC_UNK\n"); 212 return 1; 213 } 214 215 /* 216 * If there's no valid entry point for SP, we return a non-zero value 217 * signalling failure initializing the service. We bail out without 218 * registering any handlers 219 */ 220 if (!tsp_ep_info->pc) 221 return 1; 222 223 /* 224 * We could inspect the SP image and determine it's execution 225 * state i.e whether AArch32 or AArch64. Assuming it's AArch64 226 * for the time being. 227 */ 228 tspd_init_tsp_ep_state(tsp_ep_info, 229 TSP_AARCH64, 230 tsp_ep_info->pc, 231 &tspd_sp_context[linear_id]); 232 233 #if TSP_INIT_ASYNC 234 bl31_set_next_image_type(SECURE); 235 #else 236 /* 237 * All TSPD initialization done. Now register our init function with 238 * BL31 for deferred invocation 239 */ 240 bl31_register_bl32_init(&tspd_init); 241 #endif 242 return 0; 243 } 244 245 /******************************************************************************* 246 * This function passes control to the Secure Payload image (BL32) for the first 247 * time on the primary cpu after a cold boot. It assumes that a valid secure 248 * context has already been created by tspd_setup() which can be directly used. 249 * It also assumes that a valid non-secure context has been initialised by PSCI 250 * so it does not need to save and restore any non-secure state. This function 251 * performs a synchronous entry into the Secure payload. The SP passes control 252 * back to this routine through a SMC. 253 ******************************************************************************/ 254 int32_t tspd_init(void) 255 { 256 uint32_t linear_id = plat_my_core_pos(); 257 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 258 entry_point_info_t *tsp_entry_point; 259 uint64_t rc; 260 261 /* 262 * Get information about the Secure Payload (BL32) image. Its 263 * absence is a critical failure. 264 */ 265 tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); 266 assert(tsp_entry_point); 267 268 cm_init_my_context(tsp_entry_point); 269 270 /* 271 * Arrange for an entry into the test secure payload. It will be 272 * returned via TSP_ENTRY_DONE case 273 */ 274 rc = tspd_synchronous_sp_entry(tsp_ctx); 275 assert(rc != 0); 276 277 return rc; 278 } 279 280 281 /******************************************************************************* 282 * This function is responsible for handling all SMCs in the Trusted OS/App 283 * range from the non-secure state as defined in the SMC Calling Convention 284 * Document. It is also responsible for communicating with the Secure payload 285 * to delegate work and return results back to the non-secure state. Lastly it 286 * will also return any information that the secure payload needs to do the 287 * work assigned to it. 288 ******************************************************************************/ 289 uint64_t tspd_smc_handler(uint32_t smc_fid, 290 uint64_t x1, 291 uint64_t x2, 292 uint64_t x3, 293 uint64_t x4, 294 void *cookie, 295 void *handle, 296 uint64_t flags) 297 { 298 cpu_context_t *ns_cpu_context; 299 uint32_t linear_id = plat_my_core_pos(), ns; 300 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 301 uint64_t rc; 302 #if TSP_INIT_ASYNC 303 entry_point_info_t *next_image_info; 304 #endif 305 306 /* Determine which security state this SMC originated from */ 307 ns = is_caller_non_secure(flags); 308 309 switch (smc_fid) { 310 311 /* 312 * This function ID is used by TSP to indicate that it was 313 * preempted by a normal world IRQ. 314 * 315 */ 316 case TSP_PREEMPTED: 317 if (ns) 318 SMC_RET1(handle, SMC_UNK); 319 320 return tspd_handle_sp_preemption(handle); 321 322 /* 323 * This function ID is used only by the TSP to indicate that it has 324 * finished handling a S-EL1 FIQ interrupt. Execution should resume 325 * in the normal world. 326 */ 327 case TSP_HANDLED_S_EL1_FIQ: 328 if (ns) 329 SMC_RET1(handle, SMC_UNK); 330 331 assert(handle == cm_get_context(SECURE)); 332 333 /* 334 * Restore the relevant EL3 state which saved to service 335 * this SMC. 336 */ 337 if (get_std_smc_active_flag(tsp_ctx->state)) { 338 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 339 CTX_SPSR_EL3, 340 tsp_ctx->saved_spsr_el3); 341 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 342 CTX_ELR_EL3, 343 tsp_ctx->saved_elr_el3); 344 #if TSPD_ROUTE_IRQ_TO_EL3 345 /* 346 * Need to restore the previously interrupted 347 * secure context. 348 */ 349 memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx, 350 TSPD_SP_CTX_SIZE); 351 #endif 352 } 353 354 /* Get a reference to the non-secure context */ 355 ns_cpu_context = cm_get_context(NON_SECURE); 356 assert(ns_cpu_context); 357 358 /* 359 * Restore non-secure state. There is no need to save the 360 * secure system register context since the TSP was supposed 361 * to preserve it during S-EL1 interrupt handling. 362 */ 363 cm_el1_sysregs_context_restore(NON_SECURE); 364 cm_set_next_eret_context(NON_SECURE); 365 366 SMC_RET0((uint64_t) ns_cpu_context); 367 368 369 /* 370 * This function ID is used only by the TSP to indicate that it was 371 * interrupted due to a EL3 FIQ interrupt. Execution should resume 372 * in the normal world. 373 */ 374 case TSP_EL3_FIQ: 375 if (ns) 376 SMC_RET1(handle, SMC_UNK); 377 378 assert(handle == cm_get_context(SECURE)); 379 380 /* Assert that standard SMC execution has been preempted */ 381 assert(get_std_smc_active_flag(tsp_ctx->state)); 382 383 /* Save the secure system register state */ 384 cm_el1_sysregs_context_save(SECURE); 385 386 /* Get a reference to the non-secure context */ 387 ns_cpu_context = cm_get_context(NON_SECURE); 388 assert(ns_cpu_context); 389 390 /* Restore non-secure state */ 391 cm_el1_sysregs_context_restore(NON_SECURE); 392 cm_set_next_eret_context(NON_SECURE); 393 394 SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); 395 396 397 /* 398 * This function ID is used only by the SP to indicate it has 399 * finished initialising itself after a cold boot 400 */ 401 case TSP_ENTRY_DONE: 402 if (ns) 403 SMC_RET1(handle, SMC_UNK); 404 405 /* 406 * Stash the SP entry points information. This is done 407 * only once on the primary cpu 408 */ 409 assert(tsp_vectors == NULL); 410 tsp_vectors = (tsp_vectors_t *) x1; 411 412 if (tsp_vectors) { 413 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 414 415 /* 416 * TSP has been successfully initialized. Register power 417 * managemnt hooks with PSCI 418 */ 419 psci_register_spd_pm_hook(&tspd_pm); 420 421 /* 422 * Register an interrupt handler for S-EL1 interrupts 423 * when generated during code executing in the 424 * non-secure state. 425 */ 426 flags = 0; 427 set_interrupt_rm_flag(flags, NON_SECURE); 428 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 429 tspd_sel1_interrupt_handler, 430 flags); 431 if (rc) 432 panic(); 433 434 #if TSPD_ROUTE_IRQ_TO_EL3 435 /* 436 * Register an interrupt handler for NS interrupts when 437 * generated during code executing in secure state are 438 * routed to EL3. 439 */ 440 flags = 0; 441 set_interrupt_rm_flag(flags, SECURE); 442 443 rc = register_interrupt_type_handler(INTR_TYPE_NS, 444 tspd_ns_interrupt_handler, 445 flags); 446 if (rc) 447 panic(); 448 449 /* 450 * Disable the interrupt NS locally since it will be enabled globally 451 * within cm_init_my_context. 452 */ 453 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 454 #endif 455 } 456 457 458 #if TSP_INIT_ASYNC 459 /* Save the Secure EL1 system register context */ 460 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 461 cm_el1_sysregs_context_save(SECURE); 462 463 /* Program EL3 registers to enable entry into the next EL */ 464 next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE); 465 assert(next_image_info); 466 assert(NON_SECURE == 467 GET_SECURITY_STATE(next_image_info->h.attr)); 468 469 cm_init_my_context(next_image_info); 470 cm_prepare_el3_exit(NON_SECURE); 471 SMC_RET0(cm_get_context(NON_SECURE)); 472 #else 473 /* 474 * SP reports completion. The SPD must have initiated 475 * the original request through a synchronous entry 476 * into the SP. Jump back to the original C runtime 477 * context. 478 */ 479 tspd_synchronous_sp_exit(tsp_ctx, x1); 480 #endif 481 482 /* 483 * These function IDs is used only by the SP to indicate it has 484 * finished: 485 * 1. turning itself on in response to an earlier psci 486 * cpu_on request 487 * 2. resuming itself after an earlier psci cpu_suspend 488 * request. 489 */ 490 case TSP_ON_DONE: 491 case TSP_RESUME_DONE: 492 493 /* 494 * These function IDs is used only by the SP to indicate it has 495 * finished: 496 * 1. suspending itself after an earlier psci cpu_suspend 497 * request. 498 * 2. turning itself off in response to an earlier psci 499 * cpu_off request. 500 */ 501 case TSP_OFF_DONE: 502 case TSP_SUSPEND_DONE: 503 case TSP_SYSTEM_OFF_DONE: 504 case TSP_SYSTEM_RESET_DONE: 505 if (ns) 506 SMC_RET1(handle, SMC_UNK); 507 508 /* 509 * SP reports completion. The SPD must have initiated the 510 * original request through a synchronous entry into the SP. 511 * Jump back to the original C runtime context, and pass x1 as 512 * return value to the caller 513 */ 514 tspd_synchronous_sp_exit(tsp_ctx, x1); 515 516 /* 517 * Request from non-secure client to perform an 518 * arithmetic operation or response from secure 519 * payload to an earlier request. 520 */ 521 case TSP_FAST_FID(TSP_ADD): 522 case TSP_FAST_FID(TSP_SUB): 523 case TSP_FAST_FID(TSP_MUL): 524 case TSP_FAST_FID(TSP_DIV): 525 526 case TSP_STD_FID(TSP_ADD): 527 case TSP_STD_FID(TSP_SUB): 528 case TSP_STD_FID(TSP_MUL): 529 case TSP_STD_FID(TSP_DIV): 530 if (ns) { 531 /* 532 * This is a fresh request from the non-secure client. 533 * The parameters are in x1 and x2. Figure out which 534 * registers need to be preserved, save the non-secure 535 * state and send the request to the secure payload. 536 */ 537 assert(handle == cm_get_context(NON_SECURE)); 538 539 /* Check if we are already preempted */ 540 if (get_std_smc_active_flag(tsp_ctx->state)) 541 SMC_RET1(handle, SMC_UNK); 542 543 cm_el1_sysregs_context_save(NON_SECURE); 544 545 /* Save x1 and x2 for use by TSP_GET_ARGS call below */ 546 store_tsp_args(tsp_ctx, x1, x2); 547 548 /* 549 * We are done stashing the non-secure context. Ask the 550 * secure payload to do the work now. 551 */ 552 553 /* 554 * Verify if there is a valid context to use, copy the 555 * operation type and parameters to the secure context 556 * and jump to the fast smc entry point in the secure 557 * payload. Entry into S-EL1 will take place upon exit 558 * from this function. 559 */ 560 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 561 562 /* Set appropriate entry for SMC. 563 * We expect the TSP to manage the PSTATE.I and PSTATE.F 564 * flags as appropriate. 565 */ 566 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 567 cm_set_elr_el3(SECURE, (uint64_t) 568 &tsp_vectors->fast_smc_entry); 569 } else { 570 set_std_smc_active_flag(tsp_ctx->state); 571 cm_set_elr_el3(SECURE, (uint64_t) 572 &tsp_vectors->std_smc_entry); 573 #if TSPD_ROUTE_IRQ_TO_EL3 574 /* 575 * Enable the routing of NS interrupts to EL3 576 * during STD SMC processing on this core. 577 */ 578 enable_intr_rm_local(INTR_TYPE_NS, SECURE); 579 #endif 580 } 581 582 cm_el1_sysregs_context_restore(SECURE); 583 cm_set_next_eret_context(SECURE); 584 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); 585 } else { 586 /* 587 * This is the result from the secure client of an 588 * earlier request. The results are in x1-x3. Copy it 589 * into the non-secure context, save the secure state 590 * and return to the non-secure state. 591 */ 592 assert(handle == cm_get_context(SECURE)); 593 cm_el1_sysregs_context_save(SECURE); 594 595 /* Get a reference to the non-secure context */ 596 ns_cpu_context = cm_get_context(NON_SECURE); 597 assert(ns_cpu_context); 598 599 /* Restore non-secure state */ 600 cm_el1_sysregs_context_restore(NON_SECURE); 601 cm_set_next_eret_context(NON_SECURE); 602 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) { 603 clr_std_smc_active_flag(tsp_ctx->state); 604 #if TSPD_ROUTE_IRQ_TO_EL3 605 /* 606 * Disable the routing of NS interrupts to EL3 607 * after STD SMC processing is finished on this 608 * core. 609 */ 610 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 611 #endif 612 } 613 614 SMC_RET3(ns_cpu_context, x1, x2, x3); 615 } 616 617 break; 618 619 /* 620 * Request from non secure world to resume the preempted 621 * Standard SMC call. 622 */ 623 case TSP_FID_RESUME: 624 /* RESUME should be invoked only by normal world */ 625 if (!ns) { 626 assert(0); 627 break; 628 } 629 630 /* 631 * This is a resume request from the non-secure client. 632 * save the non-secure state and send the request to 633 * the secure payload. 634 */ 635 assert(handle == cm_get_context(NON_SECURE)); 636 637 /* Check if we are already preempted before resume */ 638 if (!get_std_smc_active_flag(tsp_ctx->state)) 639 SMC_RET1(handle, SMC_UNK); 640 641 cm_el1_sysregs_context_save(NON_SECURE); 642 643 /* 644 * We are done stashing the non-secure context. Ask the 645 * secure payload to do the work now. 646 */ 647 #if TSPD_ROUTE_IRQ_TO_EL3 648 /* 649 * Enable the routing of NS interrupts to EL3 during resumption 650 * of STD SMC call on this core. 651 */ 652 enable_intr_rm_local(INTR_TYPE_NS, SECURE); 653 #endif 654 655 656 657 /* We just need to return to the preempted point in 658 * TSP and the execution will resume as normal. 659 */ 660 cm_el1_sysregs_context_restore(SECURE); 661 cm_set_next_eret_context(SECURE); 662 SMC_RET0(&tsp_ctx->cpu_ctx); 663 664 /* 665 * This is a request from the secure payload for more arguments 666 * for an ongoing arithmetic operation requested by the 667 * non-secure world. Simply return the arguments from the non- 668 * secure client in the original call. 669 */ 670 case TSP_GET_ARGS: 671 if (ns) 672 SMC_RET1(handle, SMC_UNK); 673 674 get_tsp_args(tsp_ctx, x1, x2); 675 SMC_RET2(handle, x1, x2); 676 677 case TOS_CALL_COUNT: 678 /* 679 * Return the number of service function IDs implemented to 680 * provide service to non-secure 681 */ 682 SMC_RET1(handle, TSP_NUM_FID); 683 684 case TOS_UID: 685 /* Return TSP UID to the caller */ 686 SMC_UUID_RET(handle, tsp_uuid); 687 688 case TOS_CALL_VERSION: 689 /* Return the version of current implementation */ 690 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); 691 692 default: 693 break; 694 } 695 696 SMC_RET1(handle, SMC_UNK); 697 } 698 699 /* Define a SPD runtime service descriptor for fast SMC calls */ 700 DECLARE_RT_SVC( 701 tspd_fast, 702 703 OEN_TOS_START, 704 OEN_TOS_END, 705 SMC_TYPE_FAST, 706 tspd_setup, 707 tspd_smc_handler 708 ); 709 710 /* Define a SPD runtime service descriptor for standard SMC calls */ 711 DECLARE_RT_SVC( 712 tspd_std, 713 714 OEN_TOS_START, 715 OEN_TOS_END, 716 SMC_TYPE_STD, 717 NULL, 718 tspd_smc_handler 719 ); 720