1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <tsp.h> 52 #include <uuid.h> 53 #include "tspd_private.h" 54 55 /******************************************************************************* 56 * Address of the entrypoint vector table in the Secure Payload. It is 57 * initialised once on the primary core after a cold boot. 58 ******************************************************************************/ 59 tsp_vectors_t *tsp_vectors; 60 61 /******************************************************************************* 62 * Array to keep track of per-cpu Secure Payload state 63 ******************************************************************************/ 64 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 65 66 67 /* TSP UID */ 68 DEFINE_SVC_UUID(tsp_uuid, 69 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 70 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); 71 72 int32_t tspd_init(void); 73 74 /******************************************************************************* 75 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 76 * validates the interrupt and upon success arranges entry into the TSP at 77 * 'tsp_fiq_entry()' for handling the interrupt. 78 ******************************************************************************/ 79 static uint64_t tspd_sel1_interrupt_handler(uint32_t id, 80 uint32_t flags, 81 void *handle, 82 void *cookie) 83 { 84 uint32_t linear_id; 85 uint64_t mpidr; 86 tsp_context_t *tsp_ctx; 87 88 /* Check the security state when the exception was generated */ 89 assert(get_interrupt_src_ss(flags) == NON_SECURE); 90 91 #if IMF_READ_INTERRUPT_ID 92 /* Check the security status of the interrupt */ 93 assert(ic_get_interrupt_group(id) == SECURE); 94 #endif 95 96 /* Sanity check the pointer to this cpu's context */ 97 mpidr = read_mpidr(); 98 assert(handle == cm_get_context(mpidr, NON_SECURE)); 99 100 /* Save the non-secure context before entering the TSP */ 101 cm_el1_sysregs_context_save(NON_SECURE); 102 103 /* Get a reference to this cpu's TSP context */ 104 linear_id = platform_get_core_pos(mpidr); 105 tsp_ctx = &tspd_sp_context[linear_id]; 106 assert(&tsp_ctx->cpu_ctx == cm_get_context(mpidr, SECURE)); 107 108 /* 109 * Determine if the TSP was previously preempted. Its last known 110 * context has to be preserved in this case. 111 * The TSP should return control to the TSPD after handling this 112 * FIQ. Preserve essential EL3 context to allow entry into the 113 * TSP at the FIQ entry point using the 'cpu_context' structure. 114 * There is no need to save the secure system register context 115 * since the TSP is supposed to preserve it during S-EL1 interrupt 116 * handling. 117 */ 118 if (get_std_smc_active_flag(tsp_ctx->state)) { 119 tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 120 CTX_SPSR_EL3); 121 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 122 CTX_ELR_EL3); 123 } 124 125 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 126 CTX_SPSR_EL3, 127 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); 128 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 129 CTX_ELR_EL3, 130 (uint64_t) &tsp_vectors->fiq_entry); 131 cm_el1_sysregs_context_restore(SECURE); 132 cm_set_next_eret_context(SECURE); 133 134 /* 135 * Tell the TSP that it has to handle an FIQ synchronously. Also the 136 * instruction in normal world where the interrupt was generated is 137 * passed for debugging purposes. It is safe to retrieve this address 138 * from ELR_EL3 as the secure context will not take effect until 139 * el3_exit(). 140 */ 141 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); 142 } 143 144 /******************************************************************************* 145 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type 146 * (aarch32/aarch64) if not already known and initialises the context for entry 147 * into the SP for its initialisation. 148 ******************************************************************************/ 149 int32_t tspd_setup(void) 150 { 151 entry_point_info_t *image_info; 152 int32_t rc; 153 uint64_t mpidr = read_mpidr(); 154 uint32_t linear_id; 155 156 linear_id = platform_get_core_pos(mpidr); 157 158 /* 159 * Get information about the Secure Payload (BL32) image. Its 160 * absence is a critical failure. TODO: Add support to 161 * conditionally include the SPD service 162 */ 163 image_info = bl31_get_next_image_info(SECURE); 164 assert(image_info); 165 166 /* 167 * If there's no valid entry point for SP, we return a non-zero value 168 * signalling failure initializing the service. We bail out without 169 * registering any handlers 170 */ 171 if (!image_info->pc) 172 return 1; 173 174 /* 175 * We could inspect the SP image and determine it's execution 176 * state i.e whether AArch32 or AArch64. Assuming it's AArch64 177 * for the time being. 178 */ 179 rc = tspd_init_secure_context(image_info->pc, 180 TSP_AARCH64, 181 mpidr, 182 &tspd_sp_context[linear_id]); 183 assert(rc == 0); 184 185 /* 186 * All TSPD initialization done. Now register our init function with 187 * BL31 for deferred invocation 188 */ 189 bl31_register_bl32_init(&tspd_init); 190 191 return rc; 192 } 193 194 /******************************************************************************* 195 * This function passes control to the Secure Payload image (BL32) for the first 196 * time on the primary cpu after a cold boot. It assumes that a valid secure 197 * context has already been created by tspd_setup() which can be directly used. 198 * It also assumes that a valid non-secure context has been initialised by PSCI 199 * so it does not need to save and restore any non-secure state. This function 200 * performs a synchronous entry into the Secure payload. The SP passes control 201 * back to this routine through a SMC. 202 ******************************************************************************/ 203 int32_t tspd_init(void) 204 { 205 uint64_t mpidr = read_mpidr(); 206 uint32_t linear_id = platform_get_core_pos(mpidr), flags; 207 uint64_t rc; 208 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 209 210 /* 211 * Arrange for an entry into the test secure payload. We expect an array 212 * of vectors in return 213 */ 214 rc = tspd_synchronous_sp_entry(tsp_ctx); 215 assert(rc != 0); 216 if (rc) { 217 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 218 219 /* 220 * TSP has been successfully initialized. Register power 221 * managemnt hooks with PSCI 222 */ 223 psci_register_spd_pm_hook(&tspd_pm); 224 } 225 226 /* 227 * Register an interrupt handler for S-EL1 interrupts when generated 228 * during code executing in the non-secure state. 229 */ 230 flags = 0; 231 set_interrupt_rm_flag(flags, NON_SECURE); 232 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 233 tspd_sel1_interrupt_handler, 234 flags); 235 if (rc) 236 panic(); 237 238 return rc; 239 } 240 241 242 /******************************************************************************* 243 * This function is responsible for handling all SMCs in the Trusted OS/App 244 * range from the non-secure state as defined in the SMC Calling Convention 245 * Document. It is also responsible for communicating with the Secure payload 246 * to delegate work and return results back to the non-secure state. Lastly it 247 * will also return any information that the secure payload needs to do the 248 * work assigned to it. 249 ******************************************************************************/ 250 uint64_t tspd_smc_handler(uint32_t smc_fid, 251 uint64_t x1, 252 uint64_t x2, 253 uint64_t x3, 254 uint64_t x4, 255 void *cookie, 256 void *handle, 257 uint64_t flags) 258 { 259 cpu_context_t *ns_cpu_context; 260 unsigned long mpidr = read_mpidr(); 261 uint32_t linear_id = platform_get_core_pos(mpidr), ns; 262 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 263 264 /* Determine which security state this SMC originated from */ 265 ns = is_caller_non_secure(flags); 266 267 switch (smc_fid) { 268 269 /* 270 * This function ID is used by TSP to indicate that it was 271 * preempted by a normal world IRQ. 272 * 273 */ 274 case TSP_PREEMPTED: 275 if (ns) 276 SMC_RET1(handle, SMC_UNK); 277 278 assert(handle == cm_get_context(mpidr, SECURE)); 279 cm_el1_sysregs_context_save(SECURE); 280 /* Get a reference to the non-secure context */ 281 ns_cpu_context = cm_get_context(mpidr, NON_SECURE); 282 assert(ns_cpu_context); 283 284 /* 285 * Restore non-secure state. There is no need to save the 286 * secure system register context since the TSP was supposed 287 * to preserve it during S-EL1 interrupt handling. 288 */ 289 cm_el1_sysregs_context_restore(NON_SECURE); 290 cm_set_next_eret_context(NON_SECURE); 291 292 SMC_RET1(ns_cpu_context, SMC_PREEMPTED); 293 294 /* 295 * This function ID is used only by the TSP to indicate that it has 296 * finished handling a S-EL1 FIQ interrupt. Execution should resume 297 * in the normal world. 298 */ 299 case TSP_HANDLED_S_EL1_FIQ: 300 if (ns) 301 SMC_RET1(handle, SMC_UNK); 302 303 assert(handle == cm_get_context(mpidr, SECURE)); 304 305 /* 306 * Restore the relevant EL3 state which saved to service 307 * this SMC. 308 */ 309 if (get_std_smc_active_flag(tsp_ctx->state)) { 310 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 311 CTX_SPSR_EL3, 312 tsp_ctx->saved_spsr_el3); 313 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 314 CTX_ELR_EL3, 315 tsp_ctx->saved_elr_el3); 316 } 317 318 /* Get a reference to the non-secure context */ 319 ns_cpu_context = cm_get_context(mpidr, NON_SECURE); 320 assert(ns_cpu_context); 321 322 /* 323 * Restore non-secure state. There is no need to save the 324 * secure system register context since the TSP was supposed 325 * to preserve it during S-EL1 interrupt handling. 326 */ 327 cm_el1_sysregs_context_restore(NON_SECURE); 328 cm_set_next_eret_context(NON_SECURE); 329 330 SMC_RET0((uint64_t) ns_cpu_context); 331 332 333 /* 334 * This function ID is used only by the TSP to indicate that it was 335 * interrupted due to a EL3 FIQ interrupt. Execution should resume 336 * in the normal world. 337 */ 338 case TSP_EL3_FIQ: 339 if (ns) 340 SMC_RET1(handle, SMC_UNK); 341 342 assert(handle == cm_get_context(mpidr, SECURE)); 343 344 /* Assert that standard SMC execution has been preempted */ 345 assert(get_std_smc_active_flag(tsp_ctx->state)); 346 347 /* Save the secure system register state */ 348 cm_el1_sysregs_context_save(SECURE); 349 350 /* Get a reference to the non-secure context */ 351 ns_cpu_context = cm_get_context(mpidr, NON_SECURE); 352 assert(ns_cpu_context); 353 354 /* Restore non-secure state */ 355 cm_el1_sysregs_context_restore(NON_SECURE); 356 cm_set_next_eret_context(NON_SECURE); 357 358 SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); 359 360 361 /* 362 * This function ID is used only by the SP to indicate it has 363 * finished initialising itself after a cold boot 364 */ 365 case TSP_ENTRY_DONE: 366 if (ns) 367 SMC_RET1(handle, SMC_UNK); 368 369 /* 370 * Stash the SP entry points information. This is done 371 * only once on the primary cpu 372 */ 373 assert(tsp_vectors == NULL); 374 tsp_vectors = (tsp_vectors_t *) x1; 375 376 /* 377 * SP reports completion. The SPD must have initiated 378 * the original request through a synchronous entry 379 * into the SP. Jump back to the original C runtime 380 * context. 381 */ 382 tspd_synchronous_sp_exit(tsp_ctx, x1); 383 384 /* 385 * These function IDs is used only by the SP to indicate it has 386 * finished: 387 * 1. turning itself on in response to an earlier psci 388 * cpu_on request 389 * 2. resuming itself after an earlier psci cpu_suspend 390 * request. 391 */ 392 case TSP_ON_DONE: 393 case TSP_RESUME_DONE: 394 395 /* 396 * These function IDs is used only by the SP to indicate it has 397 * finished: 398 * 1. suspending itself after an earlier psci cpu_suspend 399 * request. 400 * 2. turning itself off in response to an earlier psci 401 * cpu_off request. 402 */ 403 case TSP_OFF_DONE: 404 case TSP_SUSPEND_DONE: 405 if (ns) 406 SMC_RET1(handle, SMC_UNK); 407 408 /* 409 * SP reports completion. The SPD must have initiated the 410 * original request through a synchronous entry into the SP. 411 * Jump back to the original C runtime context, and pass x1 as 412 * return value to the caller 413 */ 414 tspd_synchronous_sp_exit(tsp_ctx, x1); 415 416 /* 417 * Request from non-secure client to perform an 418 * arithmetic operation or response from secure 419 * payload to an earlier request. 420 */ 421 case TSP_FAST_FID(TSP_ADD): 422 case TSP_FAST_FID(TSP_SUB): 423 case TSP_FAST_FID(TSP_MUL): 424 case TSP_FAST_FID(TSP_DIV): 425 426 case TSP_STD_FID(TSP_ADD): 427 case TSP_STD_FID(TSP_SUB): 428 case TSP_STD_FID(TSP_MUL): 429 case TSP_STD_FID(TSP_DIV): 430 if (ns) { 431 /* 432 * This is a fresh request from the non-secure client. 433 * The parameters are in x1 and x2. Figure out which 434 * registers need to be preserved, save the non-secure 435 * state and send the request to the secure payload. 436 */ 437 assert(handle == cm_get_context(mpidr, NON_SECURE)); 438 439 /* Check if we are already preempted */ 440 if (get_std_smc_active_flag(tsp_ctx->state)) 441 SMC_RET1(handle, SMC_UNK); 442 443 cm_el1_sysregs_context_save(NON_SECURE); 444 445 /* Save x1 and x2 for use by TSP_GET_ARGS call below */ 446 store_tsp_args(tsp_ctx, x1, x2); 447 448 /* 449 * We are done stashing the non-secure context. Ask the 450 * secure payload to do the work now. 451 */ 452 453 /* 454 * Verify if there is a valid context to use, copy the 455 * operation type and parameters to the secure context 456 * and jump to the fast smc entry point in the secure 457 * payload. Entry into S-EL1 will take place upon exit 458 * from this function. 459 */ 460 assert(&tsp_ctx->cpu_ctx == cm_get_context(mpidr, SECURE)); 461 462 /* Set appropriate entry for SMC. 463 * We expect the TSP to manage the PSTATE.I and PSTATE.F 464 * flags as appropriate. 465 */ 466 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 467 cm_set_elr_el3(SECURE, (uint64_t) 468 &tsp_vectors->fast_smc_entry); 469 } else { 470 set_std_smc_active_flag(tsp_ctx->state); 471 cm_set_elr_el3(SECURE, (uint64_t) 472 &tsp_vectors->std_smc_entry); 473 } 474 475 cm_el1_sysregs_context_restore(SECURE); 476 cm_set_next_eret_context(SECURE); 477 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); 478 } else { 479 /* 480 * This is the result from the secure client of an 481 * earlier request. The results are in x1-x3. Copy it 482 * into the non-secure context, save the secure state 483 * and return to the non-secure state. 484 */ 485 assert(handle == cm_get_context(mpidr, SECURE)); 486 cm_el1_sysregs_context_save(SECURE); 487 488 /* Get a reference to the non-secure context */ 489 ns_cpu_context = cm_get_context(mpidr, NON_SECURE); 490 assert(ns_cpu_context); 491 492 /* Restore non-secure state */ 493 cm_el1_sysregs_context_restore(NON_SECURE); 494 cm_set_next_eret_context(NON_SECURE); 495 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) 496 clr_std_smc_active_flag(tsp_ctx->state); 497 SMC_RET3(ns_cpu_context, x1, x2, x3); 498 } 499 500 break; 501 502 /* 503 * Request from non secure world to resume the preempted 504 * Standard SMC call. 505 */ 506 case TSP_FID_RESUME: 507 /* RESUME should be invoked only by normal world */ 508 if (!ns) { 509 assert(0); 510 break; 511 } 512 513 /* 514 * This is a resume request from the non-secure client. 515 * save the non-secure state and send the request to 516 * the secure payload. 517 */ 518 assert(handle == cm_get_context(mpidr, NON_SECURE)); 519 520 /* Check if we are already preempted before resume */ 521 if (!get_std_smc_active_flag(tsp_ctx->state)) 522 SMC_RET1(handle, SMC_UNK); 523 524 cm_el1_sysregs_context_save(NON_SECURE); 525 526 /* 527 * We are done stashing the non-secure context. Ask the 528 * secure payload to do the work now. 529 */ 530 531 /* We just need to return to the preempted point in 532 * TSP and the execution will resume as normal. 533 */ 534 cm_el1_sysregs_context_restore(SECURE); 535 cm_set_next_eret_context(SECURE); 536 537 /* 538 * This is a request from the secure payload for more arguments 539 * for an ongoing arithmetic operation requested by the 540 * non-secure world. Simply return the arguments from the non- 541 * secure client in the original call. 542 */ 543 case TSP_GET_ARGS: 544 if (ns) 545 SMC_RET1(handle, SMC_UNK); 546 547 /* Get a reference to the non-secure context */ 548 ns_cpu_context = cm_get_context(mpidr, NON_SECURE); 549 assert(ns_cpu_context); 550 551 get_tsp_args(tsp_ctx, x1, x2); 552 SMC_RET2(handle, x1, x2); 553 554 case TOS_CALL_COUNT: 555 /* 556 * Return the number of service function IDs implemented to 557 * provide service to non-secure 558 */ 559 SMC_RET1(handle, TSP_NUM_FID); 560 561 case TOS_UID: 562 /* Return TSP UID to the caller */ 563 SMC_UUID_RET(handle, tsp_uuid); 564 565 case TOS_CALL_VERSION: 566 /* Return the version of current implementation */ 567 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); 568 569 default: 570 break; 571 } 572 573 SMC_RET1(handle, SMC_UNK); 574 } 575 576 /* Define a SPD runtime service descriptor for fast SMC calls */ 577 DECLARE_RT_SVC( 578 tspd_fast, 579 580 OEN_TOS_START, 581 OEN_TOS_END, 582 SMC_TYPE_FAST, 583 tspd_setup, 584 tspd_smc_handler 585 ); 586 587 /* Define a SPD runtime service descriptor for standard SMC calls */ 588 DECLARE_RT_SVC( 589 tspd_std, 590 591 OEN_TOS_START, 592 OEN_TOS_END, 593 SMC_TYPE_STD, 594 NULL, 595 tspd_smc_handler 596 ); 597