1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <tsp.h> 52 #include <uuid.h> 53 #include "tspd_private.h" 54 55 /******************************************************************************* 56 * Address of the entrypoint vector table in the Secure Payload. It is 57 * initialised once on the primary core after a cold boot. 58 ******************************************************************************/ 59 tsp_vectors_t *tsp_vectors; 60 61 /******************************************************************************* 62 * Array to keep track of per-cpu Secure Payload state 63 ******************************************************************************/ 64 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 65 66 67 /* TSP UID */ 68 DEFINE_SVC_UUID(tsp_uuid, 69 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 70 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); 71 72 int32_t tspd_init(void); 73 74 /******************************************************************************* 75 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 76 * validates the interrupt and upon success arranges entry into the TSP at 77 * 'tsp_fiq_entry()' for handling the interrupt. 78 ******************************************************************************/ 79 static uint64_t tspd_sel1_interrupt_handler(uint32_t id, 80 uint32_t flags, 81 void *handle, 82 void *cookie) 83 { 84 uint32_t linear_id; 85 uint64_t mpidr; 86 tsp_context_t *tsp_ctx; 87 88 /* Check the security state when the exception was generated */ 89 assert(get_interrupt_src_ss(flags) == NON_SECURE); 90 91 #if IMF_READ_INTERRUPT_ID 92 /* Check the security status of the interrupt */ 93 assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); 94 #endif 95 96 /* Sanity check the pointer to this cpu's context */ 97 mpidr = read_mpidr(); 98 assert(handle == cm_get_context(NON_SECURE)); 99 100 /* Save the non-secure context before entering the TSP */ 101 cm_el1_sysregs_context_save(NON_SECURE); 102 103 /* Get a reference to this cpu's TSP context */ 104 linear_id = platform_get_core_pos(mpidr); 105 tsp_ctx = &tspd_sp_context[linear_id]; 106 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 107 108 /* 109 * Determine if the TSP was previously preempted. Its last known 110 * context has to be preserved in this case. 111 * The TSP should return control to the TSPD after handling this 112 * FIQ. Preserve essential EL3 context to allow entry into the 113 * TSP at the FIQ entry point using the 'cpu_context' structure. 114 * There is no need to save the secure system register context 115 * since the TSP is supposed to preserve it during S-EL1 interrupt 116 * handling. 117 */ 118 if (get_std_smc_active_flag(tsp_ctx->state)) { 119 tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 120 CTX_SPSR_EL3); 121 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 122 CTX_ELR_EL3); 123 } 124 125 cm_el1_sysregs_context_restore(SECURE); 126 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry, 127 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); 128 cm_set_next_eret_context(SECURE); 129 130 /* 131 * Tell the TSP that it has to handle an FIQ synchronously. Also the 132 * instruction in normal world where the interrupt was generated is 133 * passed for debugging purposes. It is safe to retrieve this address 134 * from ELR_EL3 as the secure context will not take effect until 135 * el3_exit(). 136 */ 137 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); 138 } 139 140 /******************************************************************************* 141 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type 142 * (aarch32/aarch64) if not already known and initialises the context for entry 143 * into the SP for its initialisation. 144 ******************************************************************************/ 145 int32_t tspd_setup(void) 146 { 147 entry_point_info_t *tsp_ep_info; 148 uint64_t mpidr = read_mpidr(); 149 uint32_t linear_id; 150 151 linear_id = platform_get_core_pos(mpidr); 152 153 /* 154 * Get information about the Secure Payload (BL32) image. Its 155 * absence is a critical failure. TODO: Add support to 156 * conditionally include the SPD service 157 */ 158 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 159 if (!tsp_ep_info) { 160 WARN("No TSP provided by BL2 boot loader, Booting device" 161 " without TSP initialization. SMC`s destined for TSP" 162 " will return SMC_UNK\n"); 163 return 1; 164 } 165 166 /* 167 * If there's no valid entry point for SP, we return a non-zero value 168 * signalling failure initializing the service. We bail out without 169 * registering any handlers 170 */ 171 if (!tsp_ep_info->pc) 172 return 1; 173 174 /* 175 * We could inspect the SP image and determine it's execution 176 * state i.e whether AArch32 or AArch64. Assuming it's AArch64 177 * for the time being. 178 */ 179 tspd_init_tsp_ep_state(tsp_ep_info, 180 TSP_AARCH64, 181 tsp_ep_info->pc, 182 &tspd_sp_context[linear_id]); 183 184 /* 185 * All TSPD initialization done. Now register our init function with 186 * BL31 for deferred invocation 187 */ 188 bl31_register_bl32_init(&tspd_init); 189 190 return 0; 191 } 192 193 /******************************************************************************* 194 * This function passes control to the Secure Payload image (BL32) for the first 195 * time on the primary cpu after a cold boot. It assumes that a valid secure 196 * context has already been created by tspd_setup() which can be directly used. 197 * It also assumes that a valid non-secure context has been initialised by PSCI 198 * so it does not need to save and restore any non-secure state. This function 199 * performs a synchronous entry into the Secure payload. The SP passes control 200 * back to this routine through a SMC. 201 ******************************************************************************/ 202 int32_t tspd_init(void) 203 { 204 uint64_t mpidr = read_mpidr(); 205 uint32_t linear_id = platform_get_core_pos(mpidr), flags; 206 uint64_t rc; 207 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 208 entry_point_info_t *tsp_entry_point; 209 210 /* 211 * Get information about the Secure Payload (BL32) image. Its 212 * absence is a critical failure. 213 */ 214 tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); 215 assert(tsp_entry_point); 216 217 cm_init_context(mpidr, tsp_entry_point); 218 219 /* 220 * Arrange for an entry into the test secure payload. We expect an array 221 * of vectors in return 222 */ 223 rc = tspd_synchronous_sp_entry(tsp_ctx); 224 assert(rc != 0); 225 if (rc) { 226 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 227 228 /* 229 * TSP has been successfully initialized. Register power 230 * managemnt hooks with PSCI 231 */ 232 psci_register_spd_pm_hook(&tspd_pm); 233 } 234 235 /* 236 * Register an interrupt handler for S-EL1 interrupts when generated 237 * during code executing in the non-secure state. 238 */ 239 flags = 0; 240 set_interrupt_rm_flag(flags, NON_SECURE); 241 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 242 tspd_sel1_interrupt_handler, 243 flags); 244 if (rc) 245 panic(); 246 247 return rc; 248 } 249 250 251 /******************************************************************************* 252 * This function is responsible for handling all SMCs in the Trusted OS/App 253 * range from the non-secure state as defined in the SMC Calling Convention 254 * Document. It is also responsible for communicating with the Secure payload 255 * to delegate work and return results back to the non-secure state. Lastly it 256 * will also return any information that the secure payload needs to do the 257 * work assigned to it. 258 ******************************************************************************/ 259 uint64_t tspd_smc_handler(uint32_t smc_fid, 260 uint64_t x1, 261 uint64_t x2, 262 uint64_t x3, 263 uint64_t x4, 264 void *cookie, 265 void *handle, 266 uint64_t flags) 267 { 268 cpu_context_t *ns_cpu_context; 269 unsigned long mpidr = read_mpidr(); 270 uint32_t linear_id = platform_get_core_pos(mpidr), ns; 271 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 272 273 /* Determine which security state this SMC originated from */ 274 ns = is_caller_non_secure(flags); 275 276 switch (smc_fid) { 277 278 /* 279 * This function ID is used by TSP to indicate that it was 280 * preempted by a normal world IRQ. 281 * 282 */ 283 case TSP_PREEMPTED: 284 if (ns) 285 SMC_RET1(handle, SMC_UNK); 286 287 assert(handle == cm_get_context(SECURE)); 288 cm_el1_sysregs_context_save(SECURE); 289 /* Get a reference to the non-secure context */ 290 ns_cpu_context = cm_get_context(NON_SECURE); 291 assert(ns_cpu_context); 292 293 /* 294 * Restore non-secure state. There is no need to save the 295 * secure system register context since the TSP was supposed 296 * to preserve it during S-EL1 interrupt handling. 297 */ 298 cm_el1_sysregs_context_restore(NON_SECURE); 299 cm_set_next_eret_context(NON_SECURE); 300 301 SMC_RET1(ns_cpu_context, SMC_PREEMPTED); 302 303 /* 304 * This function ID is used only by the TSP to indicate that it has 305 * finished handling a S-EL1 FIQ interrupt. Execution should resume 306 * in the normal world. 307 */ 308 case TSP_HANDLED_S_EL1_FIQ: 309 if (ns) 310 SMC_RET1(handle, SMC_UNK); 311 312 assert(handle == cm_get_context(SECURE)); 313 314 /* 315 * Restore the relevant EL3 state which saved to service 316 * this SMC. 317 */ 318 if (get_std_smc_active_flag(tsp_ctx->state)) { 319 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 320 CTX_SPSR_EL3, 321 tsp_ctx->saved_spsr_el3); 322 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 323 CTX_ELR_EL3, 324 tsp_ctx->saved_elr_el3); 325 } 326 327 /* Get a reference to the non-secure context */ 328 ns_cpu_context = cm_get_context(NON_SECURE); 329 assert(ns_cpu_context); 330 331 /* 332 * Restore non-secure state. There is no need to save the 333 * secure system register context since the TSP was supposed 334 * to preserve it during S-EL1 interrupt handling. 335 */ 336 cm_el1_sysregs_context_restore(NON_SECURE); 337 cm_set_next_eret_context(NON_SECURE); 338 339 SMC_RET0((uint64_t) ns_cpu_context); 340 341 342 /* 343 * This function ID is used only by the TSP to indicate that it was 344 * interrupted due to a EL3 FIQ interrupt. Execution should resume 345 * in the normal world. 346 */ 347 case TSP_EL3_FIQ: 348 if (ns) 349 SMC_RET1(handle, SMC_UNK); 350 351 assert(handle == cm_get_context(SECURE)); 352 353 /* Assert that standard SMC execution has been preempted */ 354 assert(get_std_smc_active_flag(tsp_ctx->state)); 355 356 /* Save the secure system register state */ 357 cm_el1_sysregs_context_save(SECURE); 358 359 /* Get a reference to the non-secure context */ 360 ns_cpu_context = cm_get_context(NON_SECURE); 361 assert(ns_cpu_context); 362 363 /* Restore non-secure state */ 364 cm_el1_sysregs_context_restore(NON_SECURE); 365 cm_set_next_eret_context(NON_SECURE); 366 367 SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); 368 369 370 /* 371 * This function ID is used only by the SP to indicate it has 372 * finished initialising itself after a cold boot 373 */ 374 case TSP_ENTRY_DONE: 375 if (ns) 376 SMC_RET1(handle, SMC_UNK); 377 378 /* 379 * Stash the SP entry points information. This is done 380 * only once on the primary cpu 381 */ 382 assert(tsp_vectors == NULL); 383 tsp_vectors = (tsp_vectors_t *) x1; 384 385 /* 386 * SP reports completion. The SPD must have initiated 387 * the original request through a synchronous entry 388 * into the SP. Jump back to the original C runtime 389 * context. 390 */ 391 tspd_synchronous_sp_exit(tsp_ctx, x1); 392 393 /* 394 * These function IDs is used only by the SP to indicate it has 395 * finished: 396 * 1. turning itself on in response to an earlier psci 397 * cpu_on request 398 * 2. resuming itself after an earlier psci cpu_suspend 399 * request. 400 */ 401 case TSP_ON_DONE: 402 case TSP_RESUME_DONE: 403 404 /* 405 * These function IDs is used only by the SP to indicate it has 406 * finished: 407 * 1. suspending itself after an earlier psci cpu_suspend 408 * request. 409 * 2. turning itself off in response to an earlier psci 410 * cpu_off request. 411 */ 412 case TSP_OFF_DONE: 413 case TSP_SUSPEND_DONE: 414 if (ns) 415 SMC_RET1(handle, SMC_UNK); 416 417 /* 418 * SP reports completion. The SPD must have initiated the 419 * original request through a synchronous entry into the SP. 420 * Jump back to the original C runtime context, and pass x1 as 421 * return value to the caller 422 */ 423 tspd_synchronous_sp_exit(tsp_ctx, x1); 424 425 /* 426 * Request from non-secure client to perform an 427 * arithmetic operation or response from secure 428 * payload to an earlier request. 429 */ 430 case TSP_FAST_FID(TSP_ADD): 431 case TSP_FAST_FID(TSP_SUB): 432 case TSP_FAST_FID(TSP_MUL): 433 case TSP_FAST_FID(TSP_DIV): 434 435 case TSP_STD_FID(TSP_ADD): 436 case TSP_STD_FID(TSP_SUB): 437 case TSP_STD_FID(TSP_MUL): 438 case TSP_STD_FID(TSP_DIV): 439 if (ns) { 440 /* 441 * This is a fresh request from the non-secure client. 442 * The parameters are in x1 and x2. Figure out which 443 * registers need to be preserved, save the non-secure 444 * state and send the request to the secure payload. 445 */ 446 assert(handle == cm_get_context(NON_SECURE)); 447 448 /* Check if we are already preempted */ 449 if (get_std_smc_active_flag(tsp_ctx->state)) 450 SMC_RET1(handle, SMC_UNK); 451 452 cm_el1_sysregs_context_save(NON_SECURE); 453 454 /* Save x1 and x2 for use by TSP_GET_ARGS call below */ 455 store_tsp_args(tsp_ctx, x1, x2); 456 457 /* 458 * We are done stashing the non-secure context. Ask the 459 * secure payload to do the work now. 460 */ 461 462 /* 463 * Verify if there is a valid context to use, copy the 464 * operation type and parameters to the secure context 465 * and jump to the fast smc entry point in the secure 466 * payload. Entry into S-EL1 will take place upon exit 467 * from this function. 468 */ 469 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 470 471 /* Set appropriate entry for SMC. 472 * We expect the TSP to manage the PSTATE.I and PSTATE.F 473 * flags as appropriate. 474 */ 475 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 476 cm_set_elr_el3(SECURE, (uint64_t) 477 &tsp_vectors->fast_smc_entry); 478 } else { 479 set_std_smc_active_flag(tsp_ctx->state); 480 cm_set_elr_el3(SECURE, (uint64_t) 481 &tsp_vectors->std_smc_entry); 482 } 483 484 cm_el1_sysregs_context_restore(SECURE); 485 cm_set_next_eret_context(SECURE); 486 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); 487 } else { 488 /* 489 * This is the result from the secure client of an 490 * earlier request. The results are in x1-x3. Copy it 491 * into the non-secure context, save the secure state 492 * and return to the non-secure state. 493 */ 494 assert(handle == cm_get_context(SECURE)); 495 cm_el1_sysregs_context_save(SECURE); 496 497 /* Get a reference to the non-secure context */ 498 ns_cpu_context = cm_get_context(NON_SECURE); 499 assert(ns_cpu_context); 500 501 /* Restore non-secure state */ 502 cm_el1_sysregs_context_restore(NON_SECURE); 503 cm_set_next_eret_context(NON_SECURE); 504 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) 505 clr_std_smc_active_flag(tsp_ctx->state); 506 SMC_RET3(ns_cpu_context, x1, x2, x3); 507 } 508 509 break; 510 511 /* 512 * Request from non secure world to resume the preempted 513 * Standard SMC call. 514 */ 515 case TSP_FID_RESUME: 516 /* RESUME should be invoked only by normal world */ 517 if (!ns) { 518 assert(0); 519 break; 520 } 521 522 /* 523 * This is a resume request from the non-secure client. 524 * save the non-secure state and send the request to 525 * the secure payload. 526 */ 527 assert(handle == cm_get_context(NON_SECURE)); 528 529 /* Check if we are already preempted before resume */ 530 if (!get_std_smc_active_flag(tsp_ctx->state)) 531 SMC_RET1(handle, SMC_UNK); 532 533 cm_el1_sysregs_context_save(NON_SECURE); 534 535 /* 536 * We are done stashing the non-secure context. Ask the 537 * secure payload to do the work now. 538 */ 539 540 /* We just need to return to the preempted point in 541 * TSP and the execution will resume as normal. 542 */ 543 cm_el1_sysregs_context_restore(SECURE); 544 cm_set_next_eret_context(SECURE); 545 SMC_RET0(&tsp_ctx->cpu_ctx); 546 547 /* 548 * This is a request from the secure payload for more arguments 549 * for an ongoing arithmetic operation requested by the 550 * non-secure world. Simply return the arguments from the non- 551 * secure client in the original call. 552 */ 553 case TSP_GET_ARGS: 554 if (ns) 555 SMC_RET1(handle, SMC_UNK); 556 557 get_tsp_args(tsp_ctx, x1, x2); 558 SMC_RET2(handle, x1, x2); 559 560 case TOS_CALL_COUNT: 561 /* 562 * Return the number of service function IDs implemented to 563 * provide service to non-secure 564 */ 565 SMC_RET1(handle, TSP_NUM_FID); 566 567 case TOS_UID: 568 /* Return TSP UID to the caller */ 569 SMC_UUID_RET(handle, tsp_uuid); 570 571 case TOS_CALL_VERSION: 572 /* Return the version of current implementation */ 573 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); 574 575 default: 576 break; 577 } 578 579 SMC_RET1(handle, SMC_UNK); 580 } 581 582 /* Define a SPD runtime service descriptor for fast SMC calls */ 583 DECLARE_RT_SVC( 584 tspd_fast, 585 586 OEN_TOS_START, 587 OEN_TOS_END, 588 SMC_TYPE_FAST, 589 tspd_setup, 590 tspd_smc_handler 591 ); 592 593 /* Define a SPD runtime service descriptor for standard SMC calls */ 594 DECLARE_RT_SVC( 595 tspd_std, 596 597 OEN_TOS_START, 598 OEN_TOS_END, 599 SMC_TYPE_STD, 600 NULL, 601 tspd_smc_handler 602 ); 603