1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <tsp.h> 52 #include <uuid.h> 53 #include "tspd_private.h" 54 55 /******************************************************************************* 56 * Address of the entrypoint vector table in the Secure Payload. It is 57 * initialised once on the primary core after a cold boot. 58 ******************************************************************************/ 59 tsp_vectors_t *tsp_vectors; 60 61 /******************************************************************************* 62 * Array to keep track of per-cpu Secure Payload state 63 ******************************************************************************/ 64 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 65 66 67 /* TSP UID */ 68 DEFINE_SVC_UUID(tsp_uuid, 69 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 70 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); 71 72 int32_t tspd_init(void); 73 74 /******************************************************************************* 75 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 76 * validates the interrupt and upon success arranges entry into the TSP at 77 * 'tsp_fiq_entry()' for handling the interrupt. 78 ******************************************************************************/ 79 static uint64_t tspd_sel1_interrupt_handler(uint32_t id, 80 uint32_t flags, 81 void *handle, 82 void *cookie) 83 { 84 uint32_t linear_id; 85 uint64_t mpidr; 86 tsp_context_t *tsp_ctx; 87 88 /* Check the security state when the exception was generated */ 89 assert(get_interrupt_src_ss(flags) == NON_SECURE); 90 91 #if IMF_READ_INTERRUPT_ID 92 /* Check the security status of the interrupt */ 93 assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); 94 #endif 95 96 /* Sanity check the pointer to this cpu's context */ 97 mpidr = read_mpidr(); 98 assert(handle == cm_get_context(NON_SECURE)); 99 100 /* Save the non-secure context before entering the TSP */ 101 cm_el1_sysregs_context_save(NON_SECURE); 102 103 /* Get a reference to this cpu's TSP context */ 104 linear_id = platform_get_core_pos(mpidr); 105 tsp_ctx = &tspd_sp_context[linear_id]; 106 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 107 108 /* 109 * Determine if the TSP was previously preempted. Its last known 110 * context has to be preserved in this case. 111 * The TSP should return control to the TSPD after handling this 112 * FIQ. Preserve essential EL3 context to allow entry into the 113 * TSP at the FIQ entry point using the 'cpu_context' structure. 114 * There is no need to save the secure system register context 115 * since the TSP is supposed to preserve it during S-EL1 interrupt 116 * handling. 117 */ 118 if (get_std_smc_active_flag(tsp_ctx->state)) { 119 tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 120 CTX_SPSR_EL3); 121 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 122 CTX_ELR_EL3); 123 } 124 125 cm_el1_sysregs_context_restore(SECURE); 126 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry, 127 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); 128 cm_set_next_eret_context(SECURE); 129 130 /* 131 * Tell the TSP that it has to handle an FIQ synchronously. Also the 132 * instruction in normal world where the interrupt was generated is 133 * passed for debugging purposes. It is safe to retrieve this address 134 * from ELR_EL3 as the secure context will not take effect until 135 * el3_exit(). 136 */ 137 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); 138 } 139 140 /******************************************************************************* 141 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type 142 * (aarch32/aarch64) if not already known and initialises the context for entry 143 * into the SP for its initialisation. 144 ******************************************************************************/ 145 int32_t tspd_setup(void) 146 { 147 entry_point_info_t *image_info; 148 int32_t rc; 149 uint64_t mpidr = read_mpidr(); 150 uint32_t linear_id; 151 152 linear_id = platform_get_core_pos(mpidr); 153 154 /* 155 * Get information about the Secure Payload (BL32) image. Its 156 * absence is a critical failure. TODO: Add support to 157 * conditionally include the SPD service 158 */ 159 image_info = bl31_plat_get_next_image_ep_info(SECURE); 160 assert(image_info); 161 162 /* 163 * If there's no valid entry point for SP, we return a non-zero value 164 * signalling failure initializing the service. We bail out without 165 * registering any handlers 166 */ 167 if (!image_info->pc) 168 return 1; 169 170 /* 171 * We could inspect the SP image and determine it's execution 172 * state i.e whether AArch32 or AArch64. Assuming it's AArch64 173 * for the time being. 174 */ 175 rc = tspd_init_secure_context(image_info->pc, 176 TSP_AARCH64, 177 mpidr, 178 &tspd_sp_context[linear_id]); 179 assert(rc == 0); 180 181 /* 182 * All TSPD initialization done. Now register our init function with 183 * BL31 for deferred invocation 184 */ 185 bl31_register_bl32_init(&tspd_init); 186 187 return rc; 188 } 189 190 /******************************************************************************* 191 * This function passes control to the Secure Payload image (BL32) for the first 192 * time on the primary cpu after a cold boot. It assumes that a valid secure 193 * context has already been created by tspd_setup() which can be directly used. 194 * It also assumes that a valid non-secure context has been initialised by PSCI 195 * so it does not need to save and restore any non-secure state. This function 196 * performs a synchronous entry into the Secure payload. The SP passes control 197 * back to this routine through a SMC. 198 ******************************************************************************/ 199 int32_t tspd_init(void) 200 { 201 uint64_t mpidr = read_mpidr(); 202 uint32_t linear_id = platform_get_core_pos(mpidr), flags; 203 uint64_t rc; 204 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 205 206 /* 207 * Arrange for an entry into the test secure payload. We expect an array 208 * of vectors in return 209 */ 210 rc = tspd_synchronous_sp_entry(tsp_ctx); 211 assert(rc != 0); 212 if (rc) { 213 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 214 215 /* 216 * TSP has been successfully initialized. Register power 217 * managemnt hooks with PSCI 218 */ 219 psci_register_spd_pm_hook(&tspd_pm); 220 } 221 222 /* 223 * Register an interrupt handler for S-EL1 interrupts when generated 224 * during code executing in the non-secure state. 225 */ 226 flags = 0; 227 set_interrupt_rm_flag(flags, NON_SECURE); 228 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 229 tspd_sel1_interrupt_handler, 230 flags); 231 if (rc) 232 panic(); 233 234 return rc; 235 } 236 237 238 /******************************************************************************* 239 * This function is responsible for handling all SMCs in the Trusted OS/App 240 * range from the non-secure state as defined in the SMC Calling Convention 241 * Document. It is also responsible for communicating with the Secure payload 242 * to delegate work and return results back to the non-secure state. Lastly it 243 * will also return any information that the secure payload needs to do the 244 * work assigned to it. 245 ******************************************************************************/ 246 uint64_t tspd_smc_handler(uint32_t smc_fid, 247 uint64_t x1, 248 uint64_t x2, 249 uint64_t x3, 250 uint64_t x4, 251 void *cookie, 252 void *handle, 253 uint64_t flags) 254 { 255 cpu_context_t *ns_cpu_context; 256 unsigned long mpidr = read_mpidr(); 257 uint32_t linear_id = platform_get_core_pos(mpidr), ns; 258 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 259 260 /* Determine which security state this SMC originated from */ 261 ns = is_caller_non_secure(flags); 262 263 switch (smc_fid) { 264 265 /* 266 * This function ID is used by TSP to indicate that it was 267 * preempted by a normal world IRQ. 268 * 269 */ 270 case TSP_PREEMPTED: 271 if (ns) 272 SMC_RET1(handle, SMC_UNK); 273 274 assert(handle == cm_get_context(SECURE)); 275 cm_el1_sysregs_context_save(SECURE); 276 /* Get a reference to the non-secure context */ 277 ns_cpu_context = cm_get_context(NON_SECURE); 278 assert(ns_cpu_context); 279 280 /* 281 * Restore non-secure state. There is no need to save the 282 * secure system register context since the TSP was supposed 283 * to preserve it during S-EL1 interrupt handling. 284 */ 285 cm_el1_sysregs_context_restore(NON_SECURE); 286 cm_set_next_eret_context(NON_SECURE); 287 288 SMC_RET1(ns_cpu_context, SMC_PREEMPTED); 289 290 /* 291 * This function ID is used only by the TSP to indicate that it has 292 * finished handling a S-EL1 FIQ interrupt. Execution should resume 293 * in the normal world. 294 */ 295 case TSP_HANDLED_S_EL1_FIQ: 296 if (ns) 297 SMC_RET1(handle, SMC_UNK); 298 299 assert(handle == cm_get_context(SECURE)); 300 301 /* 302 * Restore the relevant EL3 state which saved to service 303 * this SMC. 304 */ 305 if (get_std_smc_active_flag(tsp_ctx->state)) { 306 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 307 CTX_SPSR_EL3, 308 tsp_ctx->saved_spsr_el3); 309 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 310 CTX_ELR_EL3, 311 tsp_ctx->saved_elr_el3); 312 } 313 314 /* Get a reference to the non-secure context */ 315 ns_cpu_context = cm_get_context(NON_SECURE); 316 assert(ns_cpu_context); 317 318 /* 319 * Restore non-secure state. There is no need to save the 320 * secure system register context since the TSP was supposed 321 * to preserve it during S-EL1 interrupt handling. 322 */ 323 cm_el1_sysregs_context_restore(NON_SECURE); 324 cm_set_next_eret_context(NON_SECURE); 325 326 SMC_RET0((uint64_t) ns_cpu_context); 327 328 329 /* 330 * This function ID is used only by the TSP to indicate that it was 331 * interrupted due to a EL3 FIQ interrupt. Execution should resume 332 * in the normal world. 333 */ 334 case TSP_EL3_FIQ: 335 if (ns) 336 SMC_RET1(handle, SMC_UNK); 337 338 assert(handle == cm_get_context(SECURE)); 339 340 /* Assert that standard SMC execution has been preempted */ 341 assert(get_std_smc_active_flag(tsp_ctx->state)); 342 343 /* Save the secure system register state */ 344 cm_el1_sysregs_context_save(SECURE); 345 346 /* Get a reference to the non-secure context */ 347 ns_cpu_context = cm_get_context(NON_SECURE); 348 assert(ns_cpu_context); 349 350 /* Restore non-secure state */ 351 cm_el1_sysregs_context_restore(NON_SECURE); 352 cm_set_next_eret_context(NON_SECURE); 353 354 SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); 355 356 357 /* 358 * This function ID is used only by the SP to indicate it has 359 * finished initialising itself after a cold boot 360 */ 361 case TSP_ENTRY_DONE: 362 if (ns) 363 SMC_RET1(handle, SMC_UNK); 364 365 /* 366 * Stash the SP entry points information. This is done 367 * only once on the primary cpu 368 */ 369 assert(tsp_vectors == NULL); 370 tsp_vectors = (tsp_vectors_t *) x1; 371 372 /* 373 * SP reports completion. The SPD must have initiated 374 * the original request through a synchronous entry 375 * into the SP. Jump back to the original C runtime 376 * context. 377 */ 378 tspd_synchronous_sp_exit(tsp_ctx, x1); 379 380 /* 381 * These function IDs is used only by the SP to indicate it has 382 * finished: 383 * 1. turning itself on in response to an earlier psci 384 * cpu_on request 385 * 2. resuming itself after an earlier psci cpu_suspend 386 * request. 387 */ 388 case TSP_ON_DONE: 389 case TSP_RESUME_DONE: 390 391 /* 392 * These function IDs is used only by the SP to indicate it has 393 * finished: 394 * 1. suspending itself after an earlier psci cpu_suspend 395 * request. 396 * 2. turning itself off in response to an earlier psci 397 * cpu_off request. 398 */ 399 case TSP_OFF_DONE: 400 case TSP_SUSPEND_DONE: 401 if (ns) 402 SMC_RET1(handle, SMC_UNK); 403 404 /* 405 * SP reports completion. The SPD must have initiated the 406 * original request through a synchronous entry into the SP. 407 * Jump back to the original C runtime context, and pass x1 as 408 * return value to the caller 409 */ 410 tspd_synchronous_sp_exit(tsp_ctx, x1); 411 412 /* 413 * Request from non-secure client to perform an 414 * arithmetic operation or response from secure 415 * payload to an earlier request. 416 */ 417 case TSP_FAST_FID(TSP_ADD): 418 case TSP_FAST_FID(TSP_SUB): 419 case TSP_FAST_FID(TSP_MUL): 420 case TSP_FAST_FID(TSP_DIV): 421 422 case TSP_STD_FID(TSP_ADD): 423 case TSP_STD_FID(TSP_SUB): 424 case TSP_STD_FID(TSP_MUL): 425 case TSP_STD_FID(TSP_DIV): 426 if (ns) { 427 /* 428 * This is a fresh request from the non-secure client. 429 * The parameters are in x1 and x2. Figure out which 430 * registers need to be preserved, save the non-secure 431 * state and send the request to the secure payload. 432 */ 433 assert(handle == cm_get_context(NON_SECURE)); 434 435 /* Check if we are already preempted */ 436 if (get_std_smc_active_flag(tsp_ctx->state)) 437 SMC_RET1(handle, SMC_UNK); 438 439 cm_el1_sysregs_context_save(NON_SECURE); 440 441 /* Save x1 and x2 for use by TSP_GET_ARGS call below */ 442 store_tsp_args(tsp_ctx, x1, x2); 443 444 /* 445 * We are done stashing the non-secure context. Ask the 446 * secure payload to do the work now. 447 */ 448 449 /* 450 * Verify if there is a valid context to use, copy the 451 * operation type and parameters to the secure context 452 * and jump to the fast smc entry point in the secure 453 * payload. Entry into S-EL1 will take place upon exit 454 * from this function. 455 */ 456 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 457 458 /* Set appropriate entry for SMC. 459 * We expect the TSP to manage the PSTATE.I and PSTATE.F 460 * flags as appropriate. 461 */ 462 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 463 cm_set_elr_el3(SECURE, (uint64_t) 464 &tsp_vectors->fast_smc_entry); 465 } else { 466 set_std_smc_active_flag(tsp_ctx->state); 467 cm_set_elr_el3(SECURE, (uint64_t) 468 &tsp_vectors->std_smc_entry); 469 } 470 471 cm_el1_sysregs_context_restore(SECURE); 472 cm_set_next_eret_context(SECURE); 473 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); 474 } else { 475 /* 476 * This is the result from the secure client of an 477 * earlier request. The results are in x1-x3. Copy it 478 * into the non-secure context, save the secure state 479 * and return to the non-secure state. 480 */ 481 assert(handle == cm_get_context(SECURE)); 482 cm_el1_sysregs_context_save(SECURE); 483 484 /* Get a reference to the non-secure context */ 485 ns_cpu_context = cm_get_context(NON_SECURE); 486 assert(ns_cpu_context); 487 488 /* Restore non-secure state */ 489 cm_el1_sysregs_context_restore(NON_SECURE); 490 cm_set_next_eret_context(NON_SECURE); 491 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) 492 clr_std_smc_active_flag(tsp_ctx->state); 493 SMC_RET3(ns_cpu_context, x1, x2, x3); 494 } 495 496 break; 497 498 /* 499 * Request from non secure world to resume the preempted 500 * Standard SMC call. 501 */ 502 case TSP_FID_RESUME: 503 /* RESUME should be invoked only by normal world */ 504 if (!ns) { 505 assert(0); 506 break; 507 } 508 509 /* 510 * This is a resume request from the non-secure client. 511 * save the non-secure state and send the request to 512 * the secure payload. 513 */ 514 assert(handle == cm_get_context(NON_SECURE)); 515 516 /* Check if we are already preempted before resume */ 517 if (!get_std_smc_active_flag(tsp_ctx->state)) 518 SMC_RET1(handle, SMC_UNK); 519 520 cm_el1_sysregs_context_save(NON_SECURE); 521 522 /* 523 * We are done stashing the non-secure context. Ask the 524 * secure payload to do the work now. 525 */ 526 527 /* We just need to return to the preempted point in 528 * TSP and the execution will resume as normal. 529 */ 530 cm_el1_sysregs_context_restore(SECURE); 531 cm_set_next_eret_context(SECURE); 532 SMC_RET0(&tsp_ctx->cpu_ctx); 533 534 /* 535 * This is a request from the secure payload for more arguments 536 * for an ongoing arithmetic operation requested by the 537 * non-secure world. Simply return the arguments from the non- 538 * secure client in the original call. 539 */ 540 case TSP_GET_ARGS: 541 if (ns) 542 SMC_RET1(handle, SMC_UNK); 543 544 get_tsp_args(tsp_ctx, x1, x2); 545 SMC_RET2(handle, x1, x2); 546 547 case TOS_CALL_COUNT: 548 /* 549 * Return the number of service function IDs implemented to 550 * provide service to non-secure 551 */ 552 SMC_RET1(handle, TSP_NUM_FID); 553 554 case TOS_UID: 555 /* Return TSP UID to the caller */ 556 SMC_UUID_RET(handle, tsp_uuid); 557 558 case TOS_CALL_VERSION: 559 /* Return the version of current implementation */ 560 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); 561 562 default: 563 break; 564 } 565 566 SMC_RET1(handle, SMC_UNK); 567 } 568 569 /* Define a SPD runtime service descriptor for fast SMC calls */ 570 DECLARE_RT_SVC( 571 tspd_fast, 572 573 OEN_TOS_START, 574 OEN_TOS_END, 575 SMC_TYPE_FAST, 576 tspd_setup, 577 tspd_smc_handler 578 ); 579 580 /* Define a SPD runtime service descriptor for standard SMC calls */ 581 DECLARE_RT_SVC( 582 tspd_std, 583 584 OEN_TOS_START, 585 OEN_TOS_END, 586 SMC_TYPE_STD, 587 NULL, 588 tspd_smc_handler 589 ); 590