1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <string.h> 52 #include <tsp.h> 53 #include <uuid.h> 54 #include "tspd_private.h" 55 56 /******************************************************************************* 57 * Address of the entrypoint vector table in the Secure Payload. It is 58 * initialised once on the primary core after a cold boot. 59 ******************************************************************************/ 60 tsp_vectors_t *tsp_vectors; 61 62 /******************************************************************************* 63 * Array to keep track of per-cpu Secure Payload state 64 ******************************************************************************/ 65 tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 66 67 68 /* TSP UID */ 69 DEFINE_SVC_UUID(tsp_uuid, 70 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 71 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); 72 73 int32_t tspd_init(void); 74 75 /* 76 * This helper function handles Secure EL1 preemption. The preemption could be 77 * due Non Secure interrupts or EL3 interrupts. In both the cases we context 78 * switch to the normal world and in case of EL3 interrupts, it will again be 79 * routed to EL3 which will get handled at the exception vectors. 80 */ 81 uint64_t tspd_handle_sp_preemption(void *handle) 82 { 83 cpu_context_t *ns_cpu_context; 84 85 assert(handle == cm_get_context(SECURE)); 86 cm_el1_sysregs_context_save(SECURE); 87 /* Get a reference to the non-secure context */ 88 ns_cpu_context = cm_get_context(NON_SECURE); 89 assert(ns_cpu_context); 90 91 /* 92 * Restore non-secure state. The secure system 93 * register context will be saved when required. 94 */ 95 cm_el1_sysregs_context_restore(NON_SECURE); 96 cm_set_next_eret_context(NON_SECURE); 97 98 /* 99 * We need to restore non secure context according to 100 * the SEL1 context which got preempted and currently 101 * TSP can only be preempted when a STD SMC is ongoing. 102 * Return SMC_PREEMPTED in x0 and restore non secure 103 * context. 104 */ 105 SMC_RET1(ns_cpu_context, SMC_PREEMPTED); 106 } 107 108 /******************************************************************************* 109 * This function is the handler registered for S-EL1 interrupts by the TSPD. It 110 * validates the interrupt and upon success arranges entry into the TSP at 111 * 'tsp_sel1_intr_entry()' for handling the interrupt. 112 ******************************************************************************/ 113 static uint64_t tspd_sel1_interrupt_handler(uint32_t id, 114 uint32_t flags, 115 void *handle, 116 void *cookie) 117 { 118 uint32_t linear_id; 119 tsp_context_t *tsp_ctx; 120 121 /* Check the security state when the exception was generated */ 122 assert(get_interrupt_src_ss(flags) == NON_SECURE); 123 124 /* Sanity check the pointer to this cpu's context */ 125 assert(handle == cm_get_context(NON_SECURE)); 126 127 /* Save the non-secure context before entering the TSP */ 128 cm_el1_sysregs_context_save(NON_SECURE); 129 130 /* Get a reference to this cpu's TSP context */ 131 linear_id = plat_my_core_pos(); 132 tsp_ctx = &tspd_sp_context[linear_id]; 133 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 134 135 /* 136 * Determine if the TSP was previously preempted. Its last known 137 * context has to be preserved in this case. 138 * The TSP should return control to the TSPD after handling this 139 * S-EL1 interrupt. Preserve essential EL3 context to allow entry into 140 * the TSP at the S-EL1 interrupt entry point using the 'cpu_context' 141 * structure. There is no need to save the secure system register 142 * context since the TSP is supposed to preserve it during S-EL1 143 * interrupt handling. 144 */ 145 if (get_std_smc_active_flag(tsp_ctx->state)) { 146 tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 147 CTX_SPSR_EL3); 148 tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, 149 CTX_ELR_EL3); 150 #if TSP_NS_INTR_ASYNC_PREEMPT 151 /*Need to save the previously interrupted secure context */ 152 memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE); 153 #endif 154 } 155 156 cm_el1_sysregs_context_restore(SECURE); 157 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry, 158 SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); 159 160 cm_set_next_eret_context(SECURE); 161 162 /* 163 * Tell the TSP that it has to handle a S-EL1 interrupt synchronously. 164 * Also the instruction in normal world where the interrupt was 165 * generated is passed for debugging purposes. It is safe to retrieve 166 * this address from ELR_EL3 as the secure context will not take effect 167 * until el3_exit(). 168 */ 169 SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_SEL1_INTR_AND_RETURN, read_elr_el3()); 170 } 171 172 #if TSP_NS_INTR_ASYNC_PREEMPT 173 /******************************************************************************* 174 * This function is the handler registered for Non secure interrupts by the 175 * TSPD. It validates the interrupt and upon success arranges entry into the 176 * normal world for handling the interrupt. 177 ******************************************************************************/ 178 static uint64_t tspd_ns_interrupt_handler(uint32_t id, 179 uint32_t flags, 180 void *handle, 181 void *cookie) 182 { 183 /* Check the security state when the exception was generated */ 184 assert(get_interrupt_src_ss(flags) == SECURE); 185 186 /* 187 * Disable the routing of NS interrupts from secure world to EL3 while 188 * interrupted on this core. 189 */ 190 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 191 192 return tspd_handle_sp_preemption(handle); 193 } 194 #endif 195 196 /******************************************************************************* 197 * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type 198 * (aarch32/aarch64) if not already known and initialises the context for entry 199 * into the SP for its initialisation. 200 ******************************************************************************/ 201 int32_t tspd_setup(void) 202 { 203 entry_point_info_t *tsp_ep_info; 204 uint32_t linear_id; 205 206 linear_id = plat_my_core_pos(); 207 208 /* 209 * Get information about the Secure Payload (BL32) image. Its 210 * absence is a critical failure. TODO: Add support to 211 * conditionally include the SPD service 212 */ 213 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 214 if (!tsp_ep_info) { 215 WARN("No TSP provided by BL2 boot loader, Booting device" 216 " without TSP initialization. SMC`s destined for TSP" 217 " will return SMC_UNK\n"); 218 return 1; 219 } 220 221 /* 222 * If there's no valid entry point for SP, we return a non-zero value 223 * signalling failure initializing the service. We bail out without 224 * registering any handlers 225 */ 226 if (!tsp_ep_info->pc) 227 return 1; 228 229 /* 230 * We could inspect the SP image and determine it's execution 231 * state i.e whether AArch32 or AArch64. Assuming it's AArch64 232 * for the time being. 233 */ 234 tspd_init_tsp_ep_state(tsp_ep_info, 235 TSP_AARCH64, 236 tsp_ep_info->pc, 237 &tspd_sp_context[linear_id]); 238 239 #if TSP_INIT_ASYNC 240 bl31_set_next_image_type(SECURE); 241 #else 242 /* 243 * All TSPD initialization done. Now register our init function with 244 * BL31 for deferred invocation 245 */ 246 bl31_register_bl32_init(&tspd_init); 247 #endif 248 return 0; 249 } 250 251 /******************************************************************************* 252 * This function passes control to the Secure Payload image (BL32) for the first 253 * time on the primary cpu after a cold boot. It assumes that a valid secure 254 * context has already been created by tspd_setup() which can be directly used. 255 * It also assumes that a valid non-secure context has been initialised by PSCI 256 * so it does not need to save and restore any non-secure state. This function 257 * performs a synchronous entry into the Secure payload. The SP passes control 258 * back to this routine through a SMC. 259 ******************************************************************************/ 260 int32_t tspd_init(void) 261 { 262 uint32_t linear_id = plat_my_core_pos(); 263 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 264 entry_point_info_t *tsp_entry_point; 265 uint64_t rc; 266 267 /* 268 * Get information about the Secure Payload (BL32) image. Its 269 * absence is a critical failure. 270 */ 271 tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); 272 assert(tsp_entry_point); 273 274 cm_init_my_context(tsp_entry_point); 275 276 /* 277 * Arrange for an entry into the test secure payload. It will be 278 * returned via TSP_ENTRY_DONE case 279 */ 280 rc = tspd_synchronous_sp_entry(tsp_ctx); 281 assert(rc != 0); 282 283 return rc; 284 } 285 286 287 /******************************************************************************* 288 * This function is responsible for handling all SMCs in the Trusted OS/App 289 * range from the non-secure state as defined in the SMC Calling Convention 290 * Document. It is also responsible for communicating with the Secure payload 291 * to delegate work and return results back to the non-secure state. Lastly it 292 * will also return any information that the secure payload needs to do the 293 * work assigned to it. 294 ******************************************************************************/ 295 uint64_t tspd_smc_handler(uint32_t smc_fid, 296 uint64_t x1, 297 uint64_t x2, 298 uint64_t x3, 299 uint64_t x4, 300 void *cookie, 301 void *handle, 302 uint64_t flags) 303 { 304 cpu_context_t *ns_cpu_context; 305 uint32_t linear_id = plat_my_core_pos(), ns; 306 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; 307 uint64_t rc; 308 #if TSP_INIT_ASYNC 309 entry_point_info_t *next_image_info; 310 #endif 311 312 /* Determine which security state this SMC originated from */ 313 ns = is_caller_non_secure(flags); 314 315 switch (smc_fid) { 316 317 /* 318 * This function ID is used by TSP to indicate that it was 319 * preempted by a normal world IRQ. 320 * 321 */ 322 case TSP_PREEMPTED: 323 if (ns) 324 SMC_RET1(handle, SMC_UNK); 325 326 return tspd_handle_sp_preemption(handle); 327 328 /* 329 * This function ID is used only by the TSP to indicate that it has 330 * finished handling a S-EL1 interrupt. Execution should resume 331 * in the normal world. 332 */ 333 case TSP_HANDLED_S_EL1_INTR: 334 if (ns) 335 SMC_RET1(handle, SMC_UNK); 336 337 assert(handle == cm_get_context(SECURE)); 338 339 /* 340 * Restore the relevant EL3 state which saved to service 341 * this SMC. 342 */ 343 if (get_std_smc_active_flag(tsp_ctx->state)) { 344 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 345 CTX_SPSR_EL3, 346 tsp_ctx->saved_spsr_el3); 347 SMC_SET_EL3(&tsp_ctx->cpu_ctx, 348 CTX_ELR_EL3, 349 tsp_ctx->saved_elr_el3); 350 #if TSP_NS_INTR_ASYNC_PREEMPT 351 /* 352 * Need to restore the previously interrupted 353 * secure context. 354 */ 355 memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx, 356 TSPD_SP_CTX_SIZE); 357 #endif 358 } 359 360 /* Get a reference to the non-secure context */ 361 ns_cpu_context = cm_get_context(NON_SECURE); 362 assert(ns_cpu_context); 363 364 /* 365 * Restore non-secure state. There is no need to save the 366 * secure system register context since the TSP was supposed 367 * to preserve it during S-EL1 interrupt handling. 368 */ 369 cm_el1_sysregs_context_restore(NON_SECURE); 370 cm_set_next_eret_context(NON_SECURE); 371 372 SMC_RET0((uint64_t) ns_cpu_context); 373 374 /* 375 * This function ID is used only by the SP to indicate it has 376 * finished initialising itself after a cold boot 377 */ 378 case TSP_ENTRY_DONE: 379 if (ns) 380 SMC_RET1(handle, SMC_UNK); 381 382 /* 383 * Stash the SP entry points information. This is done 384 * only once on the primary cpu 385 */ 386 assert(tsp_vectors == NULL); 387 tsp_vectors = (tsp_vectors_t *) x1; 388 389 if (tsp_vectors) { 390 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); 391 392 /* 393 * TSP has been successfully initialized. Register power 394 * managemnt hooks with PSCI 395 */ 396 psci_register_spd_pm_hook(&tspd_pm); 397 398 /* 399 * Register an interrupt handler for S-EL1 interrupts 400 * when generated during code executing in the 401 * non-secure state. 402 */ 403 flags = 0; 404 set_interrupt_rm_flag(flags, NON_SECURE); 405 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 406 tspd_sel1_interrupt_handler, 407 flags); 408 if (rc) 409 panic(); 410 411 #if TSP_NS_INTR_ASYNC_PREEMPT 412 /* 413 * Register an interrupt handler for NS interrupts when 414 * generated during code executing in secure state are 415 * routed to EL3. 416 */ 417 flags = 0; 418 set_interrupt_rm_flag(flags, SECURE); 419 420 rc = register_interrupt_type_handler(INTR_TYPE_NS, 421 tspd_ns_interrupt_handler, 422 flags); 423 if (rc) 424 panic(); 425 426 /* 427 * Disable the NS interrupt locally. 428 */ 429 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 430 #endif 431 } 432 433 434 #if TSP_INIT_ASYNC 435 /* Save the Secure EL1 system register context */ 436 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 437 cm_el1_sysregs_context_save(SECURE); 438 439 /* Program EL3 registers to enable entry into the next EL */ 440 next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE); 441 assert(next_image_info); 442 assert(NON_SECURE == 443 GET_SECURITY_STATE(next_image_info->h.attr)); 444 445 cm_init_my_context(next_image_info); 446 cm_prepare_el3_exit(NON_SECURE); 447 SMC_RET0(cm_get_context(NON_SECURE)); 448 #else 449 /* 450 * SP reports completion. The SPD must have initiated 451 * the original request through a synchronous entry 452 * into the SP. Jump back to the original C runtime 453 * context. 454 */ 455 tspd_synchronous_sp_exit(tsp_ctx, x1); 456 #endif 457 458 /* 459 * These function IDs is used only by the SP to indicate it has 460 * finished: 461 * 1. turning itself on in response to an earlier psci 462 * cpu_on request 463 * 2. resuming itself after an earlier psci cpu_suspend 464 * request. 465 */ 466 case TSP_ON_DONE: 467 case TSP_RESUME_DONE: 468 469 /* 470 * These function IDs is used only by the SP to indicate it has 471 * finished: 472 * 1. suspending itself after an earlier psci cpu_suspend 473 * request. 474 * 2. turning itself off in response to an earlier psci 475 * cpu_off request. 476 */ 477 case TSP_OFF_DONE: 478 case TSP_SUSPEND_DONE: 479 case TSP_SYSTEM_OFF_DONE: 480 case TSP_SYSTEM_RESET_DONE: 481 if (ns) 482 SMC_RET1(handle, SMC_UNK); 483 484 /* 485 * SP reports completion. The SPD must have initiated the 486 * original request through a synchronous entry into the SP. 487 * Jump back to the original C runtime context, and pass x1 as 488 * return value to the caller 489 */ 490 tspd_synchronous_sp_exit(tsp_ctx, x1); 491 492 /* 493 * Request from non-secure client to perform an 494 * arithmetic operation or response from secure 495 * payload to an earlier request. 496 */ 497 case TSP_FAST_FID(TSP_ADD): 498 case TSP_FAST_FID(TSP_SUB): 499 case TSP_FAST_FID(TSP_MUL): 500 case TSP_FAST_FID(TSP_DIV): 501 502 case TSP_STD_FID(TSP_ADD): 503 case TSP_STD_FID(TSP_SUB): 504 case TSP_STD_FID(TSP_MUL): 505 case TSP_STD_FID(TSP_DIV): 506 if (ns) { 507 /* 508 * This is a fresh request from the non-secure client. 509 * The parameters are in x1 and x2. Figure out which 510 * registers need to be preserved, save the non-secure 511 * state and send the request to the secure payload. 512 */ 513 assert(handle == cm_get_context(NON_SECURE)); 514 515 /* Check if we are already preempted */ 516 if (get_std_smc_active_flag(tsp_ctx->state)) 517 SMC_RET1(handle, SMC_UNK); 518 519 cm_el1_sysregs_context_save(NON_SECURE); 520 521 /* Save x1 and x2 for use by TSP_GET_ARGS call below */ 522 store_tsp_args(tsp_ctx, x1, x2); 523 524 /* 525 * We are done stashing the non-secure context. Ask the 526 * secure payload to do the work now. 527 */ 528 529 /* 530 * Verify if there is a valid context to use, copy the 531 * operation type and parameters to the secure context 532 * and jump to the fast smc entry point in the secure 533 * payload. Entry into S-EL1 will take place upon exit 534 * from this function. 535 */ 536 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); 537 538 /* Set appropriate entry for SMC. 539 * We expect the TSP to manage the PSTATE.I and PSTATE.F 540 * flags as appropriate. 541 */ 542 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 543 cm_set_elr_el3(SECURE, (uint64_t) 544 &tsp_vectors->fast_smc_entry); 545 } else { 546 set_std_smc_active_flag(tsp_ctx->state); 547 cm_set_elr_el3(SECURE, (uint64_t) 548 &tsp_vectors->std_smc_entry); 549 #if TSP_NS_INTR_ASYNC_PREEMPT 550 /* 551 * Enable the routing of NS interrupts to EL3 552 * during STD SMC processing on this core. 553 */ 554 enable_intr_rm_local(INTR_TYPE_NS, SECURE); 555 #endif 556 } 557 558 cm_el1_sysregs_context_restore(SECURE); 559 cm_set_next_eret_context(SECURE); 560 SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); 561 } else { 562 /* 563 * This is the result from the secure client of an 564 * earlier request. The results are in x1-x3. Copy it 565 * into the non-secure context, save the secure state 566 * and return to the non-secure state. 567 */ 568 assert(handle == cm_get_context(SECURE)); 569 cm_el1_sysregs_context_save(SECURE); 570 571 /* Get a reference to the non-secure context */ 572 ns_cpu_context = cm_get_context(NON_SECURE); 573 assert(ns_cpu_context); 574 575 /* Restore non-secure state */ 576 cm_el1_sysregs_context_restore(NON_SECURE); 577 cm_set_next_eret_context(NON_SECURE); 578 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) { 579 clr_std_smc_active_flag(tsp_ctx->state); 580 #if TSP_NS_INTR_ASYNC_PREEMPT 581 /* 582 * Disable the routing of NS interrupts to EL3 583 * after STD SMC processing is finished on this 584 * core. 585 */ 586 disable_intr_rm_local(INTR_TYPE_NS, SECURE); 587 #endif 588 } 589 590 SMC_RET3(ns_cpu_context, x1, x2, x3); 591 } 592 593 break; 594 595 /* 596 * Request from non secure world to resume the preempted 597 * Standard SMC call. 598 */ 599 case TSP_FID_RESUME: 600 /* RESUME should be invoked only by normal world */ 601 if (!ns) { 602 assert(0); 603 break; 604 } 605 606 /* 607 * This is a resume request from the non-secure client. 608 * save the non-secure state and send the request to 609 * the secure payload. 610 */ 611 assert(handle == cm_get_context(NON_SECURE)); 612 613 /* Check if we are already preempted before resume */ 614 if (!get_std_smc_active_flag(tsp_ctx->state)) 615 SMC_RET1(handle, SMC_UNK); 616 617 cm_el1_sysregs_context_save(NON_SECURE); 618 619 /* 620 * We are done stashing the non-secure context. Ask the 621 * secure payload to do the work now. 622 */ 623 #if TSP_NS_INTR_ASYNC_PREEMPT 624 /* 625 * Enable the routing of NS interrupts to EL3 during resumption 626 * of STD SMC call on this core. 627 */ 628 enable_intr_rm_local(INTR_TYPE_NS, SECURE); 629 #endif 630 631 632 633 /* We just need to return to the preempted point in 634 * TSP and the execution will resume as normal. 635 */ 636 cm_el1_sysregs_context_restore(SECURE); 637 cm_set_next_eret_context(SECURE); 638 SMC_RET0(&tsp_ctx->cpu_ctx); 639 640 /* 641 * This is a request from the secure payload for more arguments 642 * for an ongoing arithmetic operation requested by the 643 * non-secure world. Simply return the arguments from the non- 644 * secure client in the original call. 645 */ 646 case TSP_GET_ARGS: 647 if (ns) 648 SMC_RET1(handle, SMC_UNK); 649 650 get_tsp_args(tsp_ctx, x1, x2); 651 SMC_RET2(handle, x1, x2); 652 653 case TOS_CALL_COUNT: 654 /* 655 * Return the number of service function IDs implemented to 656 * provide service to non-secure 657 */ 658 SMC_RET1(handle, TSP_NUM_FID); 659 660 case TOS_UID: 661 /* Return TSP UID to the caller */ 662 SMC_UUID_RET(handle, tsp_uuid); 663 664 case TOS_CALL_VERSION: 665 /* Return the version of current implementation */ 666 SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); 667 668 default: 669 break; 670 } 671 672 SMC_RET1(handle, SMC_UNK); 673 } 674 675 /* Define a SPD runtime service descriptor for fast SMC calls */ 676 DECLARE_RT_SVC( 677 tspd_fast, 678 679 OEN_TOS_START, 680 OEN_TOS_END, 681 SMC_TYPE_FAST, 682 tspd_setup, 683 tspd_smc_handler 684 ); 685 686 /* Define a SPD runtime service descriptor for standard SMC calls */ 687 DECLARE_RT_SVC( 688 tspd_std, 689 690 OEN_TOS_START, 691 OEN_TOS_END, 692 SMC_TYPE_STD, 693 NULL, 694 tspd_smc_handler 695 ); 696