1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <bl32/tsp/tsp.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <lib/utils.h> 16 17 #include "tspd_private.h" 18 19 /******************************************************************************* 20 * Given a secure payload entrypoint info pointer, entry point PC, register 21 * width, cpu id & pointer to a context data structure, this function will 22 * initialize tsp context and entry point info for the secure payload 23 ******************************************************************************/ 24 void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, 25 uint32_t rw, 26 uint64_t pc, 27 tsp_context_t *tsp_ctx) 28 { 29 uint32_t ep_attr; 30 31 /* Passing a NULL context is a critical programming error */ 32 assert(tsp_ctx); 33 assert(tsp_entry_point); 34 assert(pc); 35 36 /* 37 * We support AArch64 TSP for now. 38 * TODO: Add support for AArch32 TSP 39 */ 40 assert(rw == TSP_AARCH64); 41 42 /* Associate this context with the cpu specified */ 43 tsp_ctx->mpidr = read_mpidr_el1(); 44 tsp_ctx->state = 0; 45 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 46 clr_yield_smc_active_flag(tsp_ctx->state); 47 48 cm_set_context(&tsp_ctx->cpu_ctx, SECURE); 49 50 /* initialise an entrypoint to set up the CPU context */ 51 ep_attr = SECURE | EP_ST_ENABLE; 52 if (read_sctlr_el3() & SCTLR_EE_BIT) 53 ep_attr |= EP_EE_BIG; 54 SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr); 55 56 tsp_entry_point->pc = pc; 57 tsp_entry_point->spsr = SPSR_64(MODE_EL1, 58 MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 zeromem(&tsp_entry_point->args, sizeof(tsp_entry_point->args)); 61 } 62 63 /******************************************************************************* 64 * This function takes an SP context pointer and: 65 * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. 66 * 2. Saves the current C runtime state (callee saved registers) on the stack 67 * frame and saves a reference to this state. 68 * 3. Calls el3_exit() so that the EL3 system and general purpose registers 69 * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. 70 ******************************************************************************/ 71 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) 72 { 73 uint64_t rc; 74 75 assert(tsp_ctx != NULL); 76 assert(tsp_ctx->c_rt_ctx == 0); 77 78 /* Apply the Secure EL1 system register context and switch to it */ 79 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 80 cm_el1_sysregs_context_restore(SECURE); 81 cm_set_next_eret_context(SECURE); 82 83 rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); 84 #if ENABLE_ASSERTIONS 85 tsp_ctx->c_rt_ctx = 0; 86 #endif 87 88 return rc; 89 } 90 91 92 /******************************************************************************* 93 * This function takes an SP context pointer and: 94 * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. 95 * 2. Restores the current C runtime state (callee saved registers) from the 96 * stack frame using the reference to this state saved in tspd_enter_sp(). 97 * 3. It does not need to save any general purpose or EL3 system register state 98 * as the generic smc entry routine should have saved those. 99 ******************************************************************************/ 100 void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) 101 { 102 assert(tsp_ctx != NULL); 103 /* Save the Secure EL1 system register context */ 104 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 105 cm_el1_sysregs_context_save(SECURE); 106 107 assert(tsp_ctx->c_rt_ctx != 0); 108 tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); 109 110 /* Should never reach here */ 111 assert(0); 112 } 113 114 /******************************************************************************* 115 * This function takes an SP context pointer and abort any preempted SMC 116 * request. 117 * Return 1 if there was a preempted SMC request, 0 otherwise. 118 ******************************************************************************/ 119 int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx) 120 { 121 if (!get_yield_smc_active_flag(tsp_ctx->state)) 122 return 0; 123 124 /* Abort any preempted SMC request */ 125 clr_yield_smc_active_flag(tsp_ctx->state); 126 127 /* 128 * Arrange for an entry into the test secure payload. It will 129 * be returned via TSP_ABORT_DONE case in tspd_smc_handler. 130 */ 131 cm_set_elr_el3(SECURE, 132 (uint64_t) &tsp_vectors->abort_yield_smc_entry); 133 uint64_t rc = tspd_synchronous_sp_entry(tsp_ctx); 134 135 if (rc != 0) 136 panic(); 137 138 return 1; 139 } 140 141