1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context_mgmt.h> 35 #include <debug.h> 36 #include <string.h> 37 #include <tsp.h> 38 #include "tspd_private.h" 39 40 /******************************************************************************* 41 * Given a secure payload entrypoint info pointer, entry point PC, register 42 * width, cpu id & pointer to a context data structure, this function will 43 * initialize tsp context and entry point info for the secure payload 44 ******************************************************************************/ 45 void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, 46 uint32_t rw, 47 uint64_t pc, 48 tsp_context_t *tsp_ctx) 49 { 50 uint32_t ep_attr; 51 52 /* Passing a NULL context is a critical programming error */ 53 assert(tsp_ctx); 54 assert(tsp_entry_point); 55 assert(pc); 56 57 /* 58 * We support AArch64 TSP for now. 59 * TODO: Add support for AArch32 TSP 60 */ 61 assert(rw == TSP_AARCH64); 62 63 /* Associate this context with the cpu specified */ 64 tsp_ctx->mpidr = read_mpidr_el1(); 65 tsp_ctx->state = 0; 66 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 67 clr_std_smc_active_flag(tsp_ctx->state); 68 69 cm_set_context(&tsp_ctx->cpu_ctx, SECURE); 70 71 /* initialise an entrypoint to set up the CPU context */ 72 ep_attr = SECURE | EP_ST_ENABLE; 73 if (read_sctlr_el3() & SCTLR_EE_BIT) 74 ep_attr |= EP_EE_BIG; 75 SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr); 76 77 tsp_entry_point->pc = pc; 78 tsp_entry_point->spsr = SPSR_64(MODE_EL1, 79 MODE_SP_ELX, 80 DISABLE_ALL_EXCEPTIONS); 81 memset(&tsp_entry_point->args, 0, sizeof(tsp_entry_point->args)); 82 } 83 84 /******************************************************************************* 85 * This function takes an SP context pointer and: 86 * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. 87 * 2. Saves the current C runtime state (callee saved registers) on the stack 88 * frame and saves a reference to this state. 89 * 3. Calls el3_exit() so that the EL3 system and general purpose registers 90 * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. 91 ******************************************************************************/ 92 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) 93 { 94 uint64_t rc; 95 96 assert(tsp_ctx != NULL); 97 assert(tsp_ctx->c_rt_ctx == 0); 98 99 /* Apply the Secure EL1 system register context and switch to it */ 100 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 101 cm_el1_sysregs_context_restore(SECURE); 102 cm_set_next_eret_context(SECURE); 103 104 rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); 105 #if DEBUG 106 tsp_ctx->c_rt_ctx = 0; 107 #endif 108 109 return rc; 110 } 111 112 113 /******************************************************************************* 114 * This function takes an SP context pointer and: 115 * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. 116 * 2. Restores the current C runtime state (callee saved registers) from the 117 * stack frame using the reference to this state saved in tspd_enter_sp(). 118 * 3. It does not need to save any general purpose or EL3 system register state 119 * as the generic smc entry routine should have saved those. 120 ******************************************************************************/ 121 void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) 122 { 123 assert(tsp_ctx != NULL); 124 /* Save the Secure EL1 system register context */ 125 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 126 cm_el1_sysregs_context_save(SECURE); 127 128 assert(tsp_ctx->c_rt_ctx != 0); 129 tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); 130 131 /* Should never reach here */ 132 assert(0); 133 } 134 135 /******************************************************************************* 136 * This function takes an SP context pointer and abort any preempted SMC 137 * request. 138 * Return 1 if there was a preempted SMC request, 0 otherwise. 139 ******************************************************************************/ 140 int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx) 141 { 142 if (!get_std_smc_active_flag(tsp_ctx->state)) 143 return 0; 144 145 /* Abort any preempted SMC request */ 146 clr_std_smc_active_flag(tsp_ctx->state); 147 148 /* 149 * Arrange for an entry into the test secure payload. It will 150 * be returned via TSP_ABORT_DONE case in tspd_smc_handler. 151 */ 152 cm_set_elr_el3(SECURE, 153 (uint64_t) &tsp_vectors->abort_std_smc_entry); 154 uint64_t rc = tspd_synchronous_sp_entry(tsp_ctx); 155 156 if (rc != 0) 157 panic(); 158 159 return 1; 160 } 161 162