1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl_common.h> 34 #include <context_mgmt.h> 35 #include <string.h> 36 #include "tspd_private.h" 37 38 /******************************************************************************* 39 * Given a secure payload entrypoint, register width, cpu id & pointer to a 40 * context data structure, this function will create a secure context ready for 41 * programming an entry into the secure payload. 42 ******************************************************************************/ 43 int32_t tspd_init_secure_context(uint64_t entrypoint, 44 uint32_t rw, 45 uint64_t mpidr, 46 tsp_context_t *tsp_ctx) 47 { 48 uint32_t scr, sctlr; 49 el1_sys_regs_t *el1_state; 50 uint32_t spsr; 51 52 /* Passing a NULL context is a critical programming error */ 53 assert(tsp_ctx); 54 55 /* 56 * We support AArch64 TSP for now. 57 * TODO: Add support for AArch32 TSP 58 */ 59 assert(rw == TSP_AARCH64); 60 61 /* 62 * This might look redundant if the context was statically 63 * allocated but this function cannot make that assumption. 64 */ 65 memset(tsp_ctx, 0, sizeof(*tsp_ctx)); 66 67 /* 68 * Set the right security state, register width and enable access to 69 * the secure physical timer for the SP. 70 */ 71 scr = read_scr(); 72 scr &= ~SCR_NS_BIT; 73 scr &= ~SCR_RW_BIT; 74 scr |= SCR_ST_BIT; 75 if (rw == TSP_AARCH64) 76 scr |= SCR_RW_BIT; 77 78 /* Get a pointer to the S-EL1 context memory */ 79 el1_state = get_sysregs_ctx(&tsp_ctx->cpu_ctx); 80 81 /* 82 * Program the SCTLR_EL1 such that upon entry in S-EL1, caches and MMU are 83 * disabled and exception endianess is set to be the same as EL3 84 */ 85 sctlr = read_sctlr_el3(); 86 sctlr &= SCTLR_EE_BIT; 87 sctlr |= SCTLR_EL1_RES1; 88 write_ctx_reg(el1_state, CTX_SCTLR_EL1, sctlr); 89 90 /* Set this context as ready to be initialised i.e OFF */ 91 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); 92 93 /* 94 * This context has not been used yet. It will become valid 95 * when the TSP is interrupted and wants the TSPD to preserve 96 * the context. 97 */ 98 clr_std_smc_active_flag(tsp_ctx->state); 99 100 /* Associate this context with the cpu specified */ 101 tsp_ctx->mpidr = mpidr; 102 103 cm_set_context(&tsp_ctx->cpu_ctx, SECURE); 104 spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 105 cm_set_el3_eret_context(SECURE, entrypoint, spsr, scr); 106 107 return 0; 108 } 109 110 /******************************************************************************* 111 * This function takes an SP context pointer and: 112 * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. 113 * 2. Saves the current C runtime state (callee saved registers) on the stack 114 * frame and saves a reference to this state. 115 * 3. Calls el3_exit() so that the EL3 system and general purpose registers 116 * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. 117 ******************************************************************************/ 118 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) 119 { 120 uint64_t rc; 121 122 assert(tsp_ctx->c_rt_ctx == 0); 123 124 /* Apply the Secure EL1 system register context and switch to it */ 125 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 126 cm_el1_sysregs_context_restore(SECURE); 127 cm_set_next_eret_context(SECURE); 128 129 rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); 130 #if DEBUG 131 tsp_ctx->c_rt_ctx = 0; 132 #endif 133 134 return rc; 135 } 136 137 138 /******************************************************************************* 139 * This function takes an SP context pointer and: 140 * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. 141 * 2. Restores the current C runtime state (callee saved registers) from the 142 * stack frame using the reference to this state saved in tspd_enter_sp(). 143 * 3. It does not need to save any general purpose or EL3 system register state 144 * as the generic smc entry routine should have saved those. 145 ******************************************************************************/ 146 void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) 147 { 148 /* Save the Secure EL1 system register context */ 149 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); 150 cm_el1_sysregs_context_save(SECURE); 151 152 assert(tsp_ctx->c_rt_ctx != 0); 153 tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); 154 155 /* Should never reach here */ 156 assert(0); 157 } 158