1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <inttypes.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch_helpers.h> 16 #include <bl31/bl31.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <common/runtime_svc.h> 21 #include <lib/el3_runtime/context_mgmt.h> 22 #include <lib/smccc.h> 23 #include <plat/common/platform.h> 24 #include <tools_share/uuid.h> 25 26 #include "sm_err.h" 27 #include "smcall.h" 28 29 /* Trusty UID: RFC-4122 compliant UUID version 4 */ 30 DEFINE_SVC_UUID2(trusty_uuid, 31 0x40ee25f0, 0xa2bc, 0x304c, 0x8c, 0x4c, 32 0xa1, 0x73, 0xc5, 0x7d, 0x8a, 0xf1); 33 34 /* macro to check if Hypervisor is enabled in the HCR_EL2 register */ 35 #define HYP_ENABLE_FLAG 0x286001U 36 37 /* length of Trusty's input parameters (in bytes) */ 38 #define TRUSTY_PARAMS_LEN_BYTES (4096U * 2) 39 40 struct trusty_stack { 41 uint8_t space[PLATFORM_STACK_SIZE] __aligned(16); 42 uint32_t end; 43 }; 44 45 struct trusty_cpu_ctx { 46 cpu_context_t cpu_ctx; 47 void *saved_sp; 48 uint32_t saved_security_state; 49 int32_t fiq_handler_active; 50 uint64_t fiq_handler_pc; 51 uint64_t fiq_handler_cpsr; 52 uint64_t fiq_handler_sp; 53 uint64_t fiq_pc; 54 uint64_t fiq_cpsr; 55 uint64_t fiq_sp_el1; 56 gp_regs_t fiq_gpregs; 57 struct trusty_stack secure_stack; 58 }; 59 60 struct smc_args { 61 uint64_t r0; 62 uint64_t r1; 63 uint64_t r2; 64 uint64_t r3; 65 uint64_t r4; 66 uint64_t r5; 67 uint64_t r6; 68 uint64_t r7; 69 }; 70 71 static struct trusty_cpu_ctx trusty_cpu_ctx[PLATFORM_CORE_COUNT]; 72 73 struct smc_args trusty_init_context_stack(void **sp, void *new_stack); 74 struct smc_args trusty_context_switch_helper(void **sp, void *smc_params); 75 76 static uint32_t current_vmid; 77 78 static struct trusty_cpu_ctx *get_trusty_ctx(void) 79 { 80 return &trusty_cpu_ctx[plat_my_core_pos()]; 81 } 82 83 static bool is_hypervisor_mode(void) 84 { 85 uint64_t hcr = read_hcr(); 86 87 return ((hcr & HYP_ENABLE_FLAG) != 0U) ? true : false; 88 } 89 90 static struct smc_args trusty_context_switch(uint32_t security_state, uint64_t r0, 91 uint64_t r1, uint64_t r2, uint64_t r3) 92 { 93 struct smc_args args, ret_args; 94 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 95 struct trusty_cpu_ctx *ctx_smc; 96 97 assert(ctx->saved_security_state != security_state); 98 99 args.r7 = 0; 100 if (is_hypervisor_mode()) { 101 /* According to the ARM DEN0028A spec, VMID is stored in x7 */ 102 ctx_smc = cm_get_context(NON_SECURE); 103 assert(ctx_smc != NULL); 104 args.r7 = SMC_GET_GP(ctx_smc, CTX_GPREG_X7); 105 } 106 /* r4, r5, r6 reserved for future use. */ 107 args.r6 = 0; 108 args.r5 = 0; 109 args.r4 = 0; 110 args.r3 = r3; 111 args.r2 = r2; 112 args.r1 = r1; 113 args.r0 = r0; 114 115 /* 116 * To avoid the additional overhead in PSCI flow, skip FP context 117 * saving/restoring in case of CPU suspend and resume, assuming that 118 * when it's needed the PSCI caller has preserved FP context before 119 * going here. 120 */ 121 if (r0 != SMC_FC_CPU_SUSPEND && r0 != SMC_FC_CPU_RESUME) 122 fpregs_context_save(get_fpregs_ctx(cm_get_context(security_state))); 123 cm_el1_sysregs_context_save(security_state); 124 125 ctx->saved_security_state = security_state; 126 ret_args = trusty_context_switch_helper(&ctx->saved_sp, &args); 127 128 assert(ctx->saved_security_state == ((security_state == 0U) ? 1U : 0U)); 129 130 cm_el1_sysregs_context_restore(security_state); 131 if (r0 != SMC_FC_CPU_SUSPEND && r0 != SMC_FC_CPU_RESUME) 132 fpregs_context_restore(get_fpregs_ctx(cm_get_context(security_state))); 133 134 cm_set_next_eret_context(security_state); 135 136 return ret_args; 137 } 138 139 static uint64_t trusty_fiq_handler(uint32_t id, 140 uint32_t flags, 141 void *handle, 142 void *cookie) 143 { 144 struct smc_args ret; 145 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 146 147 assert(!is_caller_secure(flags)); 148 149 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0); 150 if (ret.r0 != 0U) { 151 SMC_RET0(handle); 152 } 153 154 if (ctx->fiq_handler_active != 0) { 155 INFO("%s: fiq handler already active\n", __func__); 156 SMC_RET0(handle); 157 } 158 159 ctx->fiq_handler_active = 1; 160 (void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs)); 161 ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3); 162 ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); 163 ctx->fiq_sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1); 164 165 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp); 166 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr); 167 168 SMC_RET0(handle); 169 } 170 171 static uint64_t trusty_set_fiq_handler(void *handle, uint64_t cpu, 172 uint64_t handler, uint64_t stack) 173 { 174 struct trusty_cpu_ctx *ctx; 175 176 if (cpu >= (uint64_t)PLATFORM_CORE_COUNT) { 177 ERROR("%s: cpu %" PRId64 " >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT); 178 return (uint64_t)SM_ERR_INVALID_PARAMETERS; 179 } 180 181 ctx = &trusty_cpu_ctx[cpu]; 182 ctx->fiq_handler_pc = handler; 183 ctx->fiq_handler_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); 184 ctx->fiq_handler_sp = stack; 185 186 SMC_RET1(handle, 0); 187 } 188 189 static uint64_t trusty_get_fiq_regs(void *handle) 190 { 191 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 192 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0); 193 194 SMC_RET4(handle, ctx->fiq_pc, ctx->fiq_cpsr, sp_el0, ctx->fiq_sp_el1); 195 } 196 197 static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t x3) 198 { 199 struct smc_args ret; 200 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 201 202 if (ctx->fiq_handler_active == 0) { 203 NOTICE("%s: fiq handler not active\n", __func__); 204 SMC_RET1(handle, (uint64_t)SM_ERR_INVALID_PARAMETERS); 205 } 206 207 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0); 208 if (ret.r0 != 1U) { 209 INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %" PRId64 "\n", 210 __func__, handle, ret.r0); 211 } 212 213 /* 214 * Restore register state to state recorded on fiq entry. 215 * 216 * x0, sp_el1, pc and cpsr need to be restored because el1 cannot 217 * restore them. 218 * 219 * x1-x4 and x8-x17 need to be restored here because smc_handler64 220 * corrupts them (el1 code also restored them). 221 */ 222 (void)memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs)); 223 ctx->fiq_handler_active = 0; 224 write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1); 225 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr); 226 227 SMC_RET0(handle); 228 } 229 230 static uintptr_t trusty_smc_handler(uint32_t smc_fid, 231 u_register_t x1, 232 u_register_t x2, 233 u_register_t x3, 234 u_register_t x4, 235 void *cookie, 236 void *handle, 237 u_register_t flags) 238 { 239 struct smc_args ret; 240 uint32_t vmid = 0U; 241 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE); 242 243 /* 244 * Return success for SET_ROT_PARAMS if Trusty is not present, as 245 * Verified Boot is not even supported and returning success here 246 * would not compromise the boot process. 247 */ 248 if ((ep_info == NULL) && (smc_fid == SMC_YC_SET_ROT_PARAMS)) { 249 SMC_RET1(handle, 0); 250 } else if (ep_info == NULL) { 251 SMC_RET1(handle, SMC_UNK); 252 } else { 253 ; /* do nothing */ 254 } 255 256 if (is_caller_secure(flags)) { 257 if (smc_fid == SMC_YC_NS_RETURN) { 258 ret = trusty_context_switch(SECURE, x1, 0, 0, 0); 259 SMC_RET8(handle, ret.r0, ret.r1, ret.r2, ret.r3, 260 ret.r4, ret.r5, ret.r6, ret.r7); 261 } 262 INFO("%s (0x%x, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %p, %p, 0x%lx) \ 263 cpu %d, unknown smc\n", 264 __func__, smc_fid, x1, x2, x3, x4, cookie, handle, flags, 265 plat_my_core_pos()); 266 SMC_RET1(handle, SMC_UNK); 267 } else { 268 switch (smc_fid) { 269 case SMC_FC64_GET_UUID: 270 case SMC_FC_GET_UUID: 271 /* provide the UUID for the service to the client */ 272 SMC_UUID_RET(handle, trusty_uuid); 273 break; 274 case SMC_FC64_SET_FIQ_HANDLER: 275 return trusty_set_fiq_handler(handle, x1, x2, x3); 276 case SMC_FC64_GET_FIQ_REGS: 277 return trusty_get_fiq_regs(handle); 278 case SMC_FC_FIQ_EXIT: 279 return trusty_fiq_exit(handle, x1, x2, x3); 280 default: 281 /* Not all OENs greater than SMC_ENTITY_SECURE_MONITOR are supported */ 282 if (SMC_ENTITY(smc_fid) > SMC_ENTITY_SECURE_MONITOR) { 283 VERBOSE("%s: unsupported SMC FID (0x%x)\n", __func__, smc_fid); 284 SMC_RET1(handle, SMC_UNK); 285 } 286 287 if (is_hypervisor_mode()) 288 vmid = SMC_GET_GP(handle, CTX_GPREG_X7); 289 290 if ((current_vmid != 0) && (current_vmid != vmid)) { 291 /* This message will cause SMC mechanism 292 * abnormal in multi-guest environment. 293 * Change it to WARN in case you need it. 294 */ 295 VERBOSE("Previous SMC not finished.\n"); 296 SMC_RET1(handle, SM_ERR_BUSY); 297 } 298 current_vmid = vmid; 299 ret = trusty_context_switch(NON_SECURE, smc_fid, x1, 300 x2, x3); 301 current_vmid = 0; 302 SMC_RET1(handle, ret.r0); 303 } 304 } 305 } 306 307 static int32_t trusty_init(void) 308 { 309 entry_point_info_t *ep_info; 310 struct smc_args zero_args = {0}; 311 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 312 uint32_t cpu = plat_my_core_pos(); 313 uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), 314 CTX_SPSR_EL3)); 315 316 /* 317 * Get information about the Trusty image. Its absence is a critical 318 * failure. 319 */ 320 ep_info = bl31_plat_get_next_image_ep_info(SECURE); 321 assert(ep_info != NULL); 322 323 fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE))); 324 cm_el1_sysregs_context_save(NON_SECURE); 325 326 cm_set_context(&ctx->cpu_ctx, SECURE); 327 cm_init_my_context(ep_info); 328 329 /* 330 * Adjust secondary cpu entry point for 32 bit images to the 331 * end of exception vectors 332 */ 333 if ((cpu != 0U) && (reg_width == MODE_RW_32)) { 334 INFO("trusty: cpu %d, adjust entry point to 0x%lx\n", 335 cpu, ep_info->pc + (1U << 5)); 336 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5)); 337 } 338 339 cm_el1_sysregs_context_restore(SECURE); 340 fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE))); 341 cm_set_next_eret_context(SECURE); 342 343 ctx->saved_security_state = ~0U; /* initial saved state is invalid */ 344 (void)trusty_init_context_stack(&ctx->saved_sp, &ctx->secure_stack.end); 345 346 (void)trusty_context_switch_helper(&ctx->saved_sp, &zero_args); 347 348 cm_el1_sysregs_context_restore(NON_SECURE); 349 fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE))); 350 cm_set_next_eret_context(NON_SECURE); 351 352 return 1; 353 } 354 355 static void trusty_cpu_suspend(uint32_t off) 356 { 357 struct smc_args ret; 358 359 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_SUSPEND, off, 0, 0); 360 if (ret.r0 != 0U) { 361 INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %" PRId64 "\n", 362 __func__, plat_my_core_pos(), ret.r0); 363 } 364 } 365 366 static void trusty_cpu_resume(uint32_t on) 367 { 368 struct smc_args ret; 369 370 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_RESUME, on, 0, 0); 371 if (ret.r0 != 0U) { 372 INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %" PRId64 "\n", 373 __func__, plat_my_core_pos(), ret.r0); 374 } 375 } 376 377 static int32_t trusty_cpu_off_handler(u_register_t max_off_lvl) 378 { 379 trusty_cpu_suspend(max_off_lvl); 380 381 return 0; 382 } 383 384 static void trusty_cpu_on_finish_handler(u_register_t max_off_lvl) 385 { 386 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 387 388 if (ctx->saved_sp == NULL) { 389 (void)trusty_init(); 390 } else { 391 trusty_cpu_resume(max_off_lvl); 392 } 393 } 394 395 static void trusty_cpu_suspend_handler(u_register_t max_off_lvl) 396 { 397 trusty_cpu_suspend(max_off_lvl); 398 } 399 400 static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl) 401 { 402 trusty_cpu_resume(max_off_lvl); 403 } 404 405 static const spd_pm_ops_t trusty_pm = { 406 .svc_off = trusty_cpu_off_handler, 407 .svc_suspend = trusty_cpu_suspend_handler, 408 .svc_on_finish = trusty_cpu_on_finish_handler, 409 .svc_suspend_finish = trusty_cpu_suspend_finish_handler, 410 }; 411 412 void plat_trusty_set_boot_args(aapcs64_params_t *args); 413 414 #if !defined(TSP_SEC_MEM_SIZE) && defined(BL32_MEM_SIZE) 415 #define TSP_SEC_MEM_SIZE BL32_MEM_SIZE 416 #endif 417 418 #ifdef TSP_SEC_MEM_SIZE 419 #pragma weak plat_trusty_set_boot_args 420 void plat_trusty_set_boot_args(aapcs64_params_t *args) 421 { 422 args->arg0 = TSP_SEC_MEM_SIZE; 423 } 424 #endif 425 426 static int32_t trusty_setup(void) 427 { 428 entry_point_info_t *ep_info; 429 uint32_t instr; 430 uint32_t flags; 431 int32_t ret; 432 bool aarch32 = false; 433 434 /* Get trusty's entry point info */ 435 ep_info = bl31_plat_get_next_image_ep_info(SECURE); 436 if (ep_info == NULL) { 437 VERBOSE("Trusty image missing.\n"); 438 return -1; 439 } 440 441 /* memmap first page of trusty's code memory before peeking */ 442 ret = mmap_add_dynamic_region(ep_info->pc, /* PA */ 443 ep_info->pc, /* VA */ 444 PAGE_SIZE, /* size */ 445 MT_SECURE | MT_RW_DATA); /* attrs */ 446 assert(ret == 0); 447 448 /* peek into trusty's code to see if we have a 32-bit or 64-bit image */ 449 instr = *(uint32_t *)ep_info->pc; 450 451 if (instr >> 24 == 0xeaU) { 452 INFO("trusty: Found 32 bit image\n"); 453 aarch32 = true; 454 } else if (instr >> 8 == 0xd53810U || instr >> 16 == 0x9400U) { 455 INFO("trusty: Found 64 bit image\n"); 456 } else { 457 ERROR("trusty: Found unknown image, 0x%x\n", instr); 458 return -1; 459 } 460 461 /* unmap trusty's memory page */ 462 (void)mmap_remove_dynamic_region(ep_info->pc, PAGE_SIZE); 463 464 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); 465 if (!aarch32) 466 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 467 DISABLE_ALL_EXCEPTIONS); 468 else 469 ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 470 SPSR_E_LITTLE, 471 DAIF_FIQ_BIT | 472 DAIF_IRQ_BIT | 473 DAIF_ABT_BIT); 474 (void)memset(&ep_info->args, 0, sizeof(ep_info->args)); 475 plat_trusty_set_boot_args(&ep_info->args); 476 477 /* register init handler */ 478 bl31_register_bl32_init(trusty_init); 479 480 /* register power management hooks */ 481 psci_register_spd_pm_hook(&trusty_pm); 482 483 /* register interrupt handler */ 484 flags = 0; 485 set_interrupt_rm_flag(flags, NON_SECURE); 486 ret = register_interrupt_type_handler(INTR_TYPE_S_EL1, 487 trusty_fiq_handler, 488 flags); 489 if (ret != 0) { 490 VERBOSE("trusty: failed to register fiq handler, ret = %d\n", ret); 491 } 492 493 if (aarch32) { 494 entry_point_info_t *ns_ep_info; 495 uint32_t spsr; 496 497 ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE); 498 if (ns_ep_info == NULL) { 499 NOTICE("Trusty: non-secure image missing.\n"); 500 return -1; 501 } 502 spsr = ns_ep_info->spsr; 503 if (GET_RW(spsr) == MODE_RW_64 && GET_EL(spsr) == MODE_EL2) { 504 spsr &= ~(MODE_EL_MASK << MODE_EL_SHIFT); 505 spsr |= MODE_EL1 << MODE_EL_SHIFT; 506 } 507 if (GET_RW(spsr) == MODE_RW_32 && GET_M32(spsr) == MODE32_hyp) { 508 spsr &= ~(MODE32_MASK << MODE32_SHIFT); 509 spsr |= MODE32_svc << MODE32_SHIFT; 510 } 511 if (spsr != ns_ep_info->spsr) { 512 NOTICE("Trusty: Switch bl33 from EL2 to EL1 (spsr 0x%x -> 0x%x)\n", 513 ns_ep_info->spsr, spsr); 514 ns_ep_info->spsr = spsr; 515 } 516 } 517 518 return 0; 519 } 520 521 /* Define a SPD runtime service descriptor for fast SMC calls */ 522 DECLARE_RT_SVC( 523 trusty_fast, 524 525 OEN_TOS_START, 526 OEN_TOS_END, 527 SMC_TYPE_FAST, 528 trusty_setup, 529 trusty_smc_handler 530 ); 531 532 /* Define a SPD runtime service descriptor for yielding SMC calls */ 533 DECLARE_RT_SVC( 534 trusty_std, 535 536 OEN_TAP_START, 537 SMC_ENTITY_SECURE_MONITOR, 538 SMC_TYPE_YIELD, 539 NULL, 540 trusty_smc_handler 541 ); 542