1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> /* for context_mgmt.h */ 33 #include <bl_common.h> 34 #include <bl31.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <interrupt_mgmt.h> 38 #include <platform.h> 39 #include <runtime_svc.h> 40 #include <string.h> 41 42 #include "smcall.h" 43 #include "sm_err.h" 44 45 /* macro to check if Hypervisor is enabled in the HCR_EL2 register */ 46 #define HYP_ENABLE_FLAG 0x286001 47 48 /* length of Trusty's input parameters (in bytes) */ 49 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 50 51 struct trusty_stack { 52 uint8_t space[PLATFORM_STACK_SIZE] __aligned(16); 53 }; 54 55 struct trusty_cpu_ctx { 56 cpu_context_t cpu_ctx; 57 void *saved_sp; 58 uint32_t saved_security_state; 59 int fiq_handler_active; 60 uint64_t fiq_handler_pc; 61 uint64_t fiq_handler_cpsr; 62 uint64_t fiq_handler_sp; 63 uint64_t fiq_pc; 64 uint64_t fiq_cpsr; 65 uint64_t fiq_sp_el1; 66 gp_regs_t fiq_gpregs; 67 struct trusty_stack secure_stack; 68 }; 69 70 struct args { 71 uint64_t r0; 72 uint64_t r1; 73 uint64_t r2; 74 uint64_t r3; 75 uint64_t r4; 76 uint64_t r5; 77 uint64_t r6; 78 uint64_t r7; 79 }; 80 81 struct trusty_cpu_ctx trusty_cpu_ctx[PLATFORM_CORE_COUNT]; 82 83 struct args trusty_init_context_stack(void **sp, void *new_stack); 84 struct args trusty_context_switch_helper(void **sp, void *smc_params); 85 86 static uint32_t current_vmid; 87 88 static struct trusty_cpu_ctx *get_trusty_ctx(void) 89 { 90 return &trusty_cpu_ctx[plat_my_core_pos()]; 91 } 92 93 static uint32_t is_hypervisor_mode(void) 94 { 95 uint64_t hcr = read_hcr(); 96 97 return !!(hcr & HYP_ENABLE_FLAG); 98 } 99 100 static struct args trusty_context_switch(uint32_t security_state, uint64_t r0, 101 uint64_t r1, uint64_t r2, uint64_t r3) 102 { 103 struct args ret; 104 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 105 struct trusty_cpu_ctx *ctx_smc; 106 107 assert(ctx->saved_security_state != security_state); 108 109 ret.r7 = 0; 110 if (is_hypervisor_mode()) { 111 /* According to the ARM DEN0028A spec, VMID is stored in x7 */ 112 ctx_smc = cm_get_context(NON_SECURE); 113 assert(ctx_smc); 114 ret.r7 = SMC_GET_GP(ctx_smc, CTX_GPREG_X7); 115 } 116 /* r4, r5, r6 reserved for future use. */ 117 ret.r6 = 0; 118 ret.r5 = 0; 119 ret.r4 = 0; 120 ret.r3 = r3; 121 ret.r2 = r2; 122 ret.r1 = r1; 123 ret.r0 = r0; 124 125 cm_el1_sysregs_context_save(security_state); 126 127 ctx->saved_security_state = security_state; 128 ret = trusty_context_switch_helper(&ctx->saved_sp, &ret); 129 130 assert(ctx->saved_security_state == !security_state); 131 132 cm_el1_sysregs_context_restore(security_state); 133 cm_set_next_eret_context(security_state); 134 135 return ret; 136 } 137 138 static uint64_t trusty_fiq_handler(uint32_t id, 139 uint32_t flags, 140 void *handle, 141 void *cookie) 142 { 143 struct args ret; 144 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 145 146 assert(!is_caller_secure(flags)); 147 148 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0); 149 if (ret.r0) { 150 SMC_RET0(handle); 151 } 152 153 if (ctx->fiq_handler_active) { 154 INFO("%s: fiq handler already active\n", __func__); 155 SMC_RET0(handle); 156 } 157 158 ctx->fiq_handler_active = 1; 159 memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs)); 160 ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3); 161 ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); 162 ctx->fiq_sp_el1 = read_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1); 163 164 write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp); 165 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, ctx->fiq_handler_cpsr); 166 167 SMC_RET0(handle); 168 } 169 170 static uint64_t trusty_set_fiq_handler(void *handle, uint64_t cpu, 171 uint64_t handler, uint64_t stack) 172 { 173 struct trusty_cpu_ctx *ctx; 174 175 if (cpu >= PLATFORM_CORE_COUNT) { 176 ERROR("%s: cpu %ld >= %d\n", __func__, cpu, PLATFORM_CORE_COUNT); 177 return SM_ERR_INVALID_PARAMETERS; 178 } 179 180 ctx = &trusty_cpu_ctx[cpu]; 181 ctx->fiq_handler_pc = handler; 182 ctx->fiq_handler_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); 183 ctx->fiq_handler_sp = stack; 184 185 SMC_RET1(handle, 0); 186 } 187 188 static uint64_t trusty_get_fiq_regs(void *handle) 189 { 190 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 191 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0); 192 193 SMC_RET4(handle, ctx->fiq_pc, ctx->fiq_cpsr, sp_el0, ctx->fiq_sp_el1); 194 } 195 196 static uint64_t trusty_fiq_exit(void *handle, uint64_t x1, uint64_t x2, uint64_t x3) 197 { 198 struct args ret; 199 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 200 201 if (!ctx->fiq_handler_active) { 202 NOTICE("%s: fiq handler not active\n", __func__); 203 SMC_RET1(handle, SM_ERR_INVALID_PARAMETERS); 204 } 205 206 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0); 207 if (ret.r0 != 1) { 208 INFO("%s(%p) SMC_FC_FIQ_EXIT returned unexpected value, %ld\n", 209 __func__, handle, ret.r0); 210 } 211 212 /* 213 * Restore register state to state recorded on fiq entry. 214 * 215 * x0, sp_el1, pc and cpsr need to be restored because el1 cannot 216 * restore them. 217 * 218 * x1-x4 and x8-x17 need to be restored here because smc_handler64 219 * corrupts them (el1 code also restored them). 220 */ 221 memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs)); 222 ctx->fiq_handler_active = 0; 223 write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1); 224 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, ctx->fiq_cpsr); 225 226 SMC_RET0(handle); 227 } 228 229 static uint64_t trusty_smc_handler(uint32_t smc_fid, 230 uint64_t x1, 231 uint64_t x2, 232 uint64_t x3, 233 uint64_t x4, 234 void *cookie, 235 void *handle, 236 uint64_t flags) 237 { 238 struct args ret; 239 uint32_t vmid = 0; 240 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE); 241 242 /* 243 * Return success for SET_ROT_PARAMS if Trusty is not present, as 244 * Verified Boot is not even supported and returning success here 245 * would not compromise the boot process. 246 */ 247 if (!ep_info && (smc_fid == SMC_SC_SET_ROT_PARAMS)) { 248 SMC_RET1(handle, 0); 249 } else if (!ep_info) { 250 SMC_RET1(handle, SMC_UNK); 251 } 252 253 if (is_caller_secure(flags)) { 254 if (smc_fid == SMC_SC_NS_RETURN) { 255 ret = trusty_context_switch(SECURE, x1, 0, 0, 0); 256 SMC_RET8(handle, ret.r0, ret.r1, ret.r2, ret.r3, 257 ret.r4, ret.r5, ret.r6, ret.r7); 258 } 259 INFO("%s (0x%x, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %p, %p, 0x%lx) \ 260 cpu %d, unknown smc\n", 261 __func__, smc_fid, x1, x2, x3, x4, cookie, handle, flags, 262 plat_my_core_pos()); 263 SMC_RET1(handle, SMC_UNK); 264 } else { 265 switch (smc_fid) { 266 case SMC_FC64_SET_FIQ_HANDLER: 267 return trusty_set_fiq_handler(handle, x1, x2, x3); 268 case SMC_FC64_GET_FIQ_REGS: 269 return trusty_get_fiq_regs(handle); 270 case SMC_FC_FIQ_EXIT: 271 return trusty_fiq_exit(handle, x1, x2, x3); 272 default: 273 if (is_hypervisor_mode()) 274 vmid = SMC_GET_GP(handle, CTX_GPREG_X7); 275 276 if ((current_vmid != 0) && (current_vmid != vmid)) { 277 /* This message will cause SMC mechanism 278 * abnormal in multi-guest environment. 279 * Change it to WARN in case you need it. 280 */ 281 VERBOSE("Previous SMC not finished.\n"); 282 SMC_RET1(handle, SM_ERR_BUSY); 283 } 284 current_vmid = vmid; 285 ret = trusty_context_switch(NON_SECURE, smc_fid, x1, 286 x2, x3); 287 current_vmid = 0; 288 SMC_RET1(handle, ret.r0); 289 } 290 } 291 } 292 293 static int32_t trusty_init(void) 294 { 295 void el3_exit(void); 296 entry_point_info_t *ep_info; 297 struct args zero_args = {0}; 298 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 299 uint32_t cpu = plat_my_core_pos(); 300 int reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), 301 CTX_SPSR_EL3)); 302 303 /* 304 * Get information about the Trusty image. Its absence is a critical 305 * failure. 306 */ 307 ep_info = bl31_plat_get_next_image_ep_info(SECURE); 308 assert(ep_info); 309 310 cm_el1_sysregs_context_save(NON_SECURE); 311 312 cm_set_context(&ctx->cpu_ctx, SECURE); 313 cm_init_my_context(ep_info); 314 315 /* 316 * Adjust secondary cpu entry point for 32 bit images to the 317 * end of exeption vectors 318 */ 319 if ((cpu != 0) && (reg_width == MODE_RW_32)) { 320 INFO("trusty: cpu %d, adjust entry point to 0x%lx\n", 321 cpu, ep_info->pc + (1U << 5)); 322 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5)); 323 } 324 325 cm_el1_sysregs_context_restore(SECURE); 326 cm_set_next_eret_context(SECURE); 327 328 ctx->saved_security_state = ~0; /* initial saved state is invalid */ 329 trusty_init_context_stack(&ctx->saved_sp, &ctx->secure_stack); 330 331 trusty_context_switch_helper(&ctx->saved_sp, &zero_args); 332 333 cm_el1_sysregs_context_restore(NON_SECURE); 334 cm_set_next_eret_context(NON_SECURE); 335 336 return 0; 337 } 338 339 static void trusty_cpu_suspend(void) 340 { 341 struct args ret; 342 343 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_SUSPEND, 0, 0, 0); 344 if (ret.r0 != 0) { 345 INFO("%s: cpu %d, SMC_FC_CPU_SUSPEND returned unexpected value, %ld\n", 346 __func__, plat_my_core_pos(), ret.r0); 347 } 348 } 349 350 static void trusty_cpu_resume(void) 351 { 352 struct args ret; 353 354 ret = trusty_context_switch(NON_SECURE, SMC_FC_CPU_RESUME, 0, 0, 0); 355 if (ret.r0 != 0) { 356 INFO("%s: cpu %d, SMC_FC_CPU_RESUME returned unexpected value, %ld\n", 357 __func__, plat_my_core_pos(), ret.r0); 358 } 359 } 360 361 static int32_t trusty_cpu_off_handler(uint64_t unused) 362 { 363 trusty_cpu_suspend(); 364 365 return 0; 366 } 367 368 static void trusty_cpu_on_finish_handler(uint64_t unused) 369 { 370 struct trusty_cpu_ctx *ctx = get_trusty_ctx(); 371 372 if (!ctx->saved_sp) { 373 trusty_init(); 374 } else { 375 trusty_cpu_resume(); 376 } 377 } 378 379 static void trusty_cpu_suspend_handler(uint64_t unused) 380 { 381 trusty_cpu_suspend(); 382 } 383 384 static void trusty_cpu_suspend_finish_handler(uint64_t unused) 385 { 386 trusty_cpu_resume(); 387 } 388 389 static const spd_pm_ops_t trusty_pm = { 390 .svc_off = trusty_cpu_off_handler, 391 .svc_suspend = trusty_cpu_suspend_handler, 392 .svc_on_finish = trusty_cpu_on_finish_handler, 393 .svc_suspend_finish = trusty_cpu_suspend_finish_handler, 394 }; 395 396 static int32_t trusty_setup(void) 397 { 398 entry_point_info_t *ep_info; 399 uint32_t instr; 400 uint32_t flags; 401 int ret; 402 int aarch32 = 0; 403 404 ep_info = bl31_plat_get_next_image_ep_info(SECURE); 405 if (!ep_info) { 406 INFO("Trusty image missing.\n"); 407 return -1; 408 } 409 410 instr = *(uint32_t *)ep_info->pc; 411 412 if (instr >> 24 == 0xea) { 413 INFO("trusty: Found 32 bit image\n"); 414 aarch32 = 1; 415 } else if (instr >> 8 == 0xd53810) { 416 INFO("trusty: Found 64 bit image\n"); 417 } else { 418 INFO("trusty: Found unknown image, 0x%x\n", instr); 419 } 420 421 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); 422 if (!aarch32) 423 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 424 DISABLE_ALL_EXCEPTIONS); 425 else 426 ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 427 SPSR_E_LITTLE, 428 DAIF_FIQ_BIT | 429 DAIF_IRQ_BIT | 430 DAIF_ABT_BIT); 431 432 /* 433 * arg0 = TZDRAM aperture available for BL32 434 * arg1 = BL32 boot params 435 * arg2 = BL32 boot params length 436 */ 437 ep_info->args.arg1 = ep_info->args.arg2; 438 ep_info->args.arg2 = TRUSTY_PARAMS_LEN_BYTES; 439 440 bl31_register_bl32_init(trusty_init); 441 442 psci_register_spd_pm_hook(&trusty_pm); 443 444 flags = 0; 445 set_interrupt_rm_flag(flags, NON_SECURE); 446 ret = register_interrupt_type_handler(INTR_TYPE_S_EL1, 447 trusty_fiq_handler, 448 flags); 449 if (ret) 450 ERROR("trusty: failed to register fiq handler, ret = %d\n", ret); 451 452 return 0; 453 } 454 455 /* Define a SPD runtime service descriptor for fast SMC calls */ 456 DECLARE_RT_SVC( 457 trusty_fast, 458 459 OEN_TOS_START, 460 SMC_ENTITY_SECURE_MONITOR, 461 SMC_TYPE_FAST, 462 trusty_setup, 463 trusty_smc_handler 464 ); 465 466 /* Define a SPD runtime service descriptor for standard SMC calls */ 467 DECLARE_RT_SVC( 468 trusty_std, 469 470 OEN_TAP_START, 471 SMC_ENTITY_SECURE_MONITOR, 472 SMC_TYPE_STD, 473 NULL, 474 trusty_smc_handler 475 ); 476