122038315SVarun Wadekar /* 222038315SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 322038315SVarun Wadekar * 422038315SVarun Wadekar * Redistribution and use in source and binary forms, with or without 522038315SVarun Wadekar * modification, are permitted provided that the following conditions are met: 622038315SVarun Wadekar * 722038315SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 822038315SVarun Wadekar * list of conditions and the following disclaimer. 922038315SVarun Wadekar * 1022038315SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1122038315SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1222038315SVarun Wadekar * and/or other materials provided with the distribution. 1322038315SVarun Wadekar * 1422038315SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1522038315SVarun Wadekar * to endorse or promote products derived from this software without specific 1622038315SVarun Wadekar * prior written permission. 1722038315SVarun Wadekar * 1822038315SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1922038315SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2022038315SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2122038315SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2222038315SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2322038315SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2422038315SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2522038315SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2622038315SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2722038315SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2822038315SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2922038315SVarun Wadekar */ 3022038315SVarun Wadekar 3122038315SVarun Wadekar #ifndef __TLKD_PRIVATE_H__ 3222038315SVarun Wadekar #define __TLKD_PRIVATE_H__ 3322038315SVarun Wadekar 3422038315SVarun Wadekar #include <arch.h> 3522038315SVarun Wadekar #include <context.h> 3622038315SVarun Wadekar #include <interrupt_mgmt.h> 3722038315SVarun Wadekar #include <platform_def.h> 3822038315SVarun Wadekar #include <psci.h> 3922038315SVarun Wadekar 4022038315SVarun Wadekar /* 4122038315SVarun Wadekar * This flag is used by the TLKD to determine if the SP is servicing a standard 4222038315SVarun Wadekar * SMC request prior to programming the next entry into the SP e.g. if SP 4322038315SVarun Wadekar * execution is preempted by a non-secure interrupt and handed control to the 4422038315SVarun Wadekar * normal world. If another request which is distinct from what the SP was 4522038315SVarun Wadekar * previously doing arrives, then this flag will be help the TLKD to either 4622038315SVarun Wadekar * reject the new request or service it while ensuring that the previous context 4722038315SVarun Wadekar * is not corrupted. 4822038315SVarun Wadekar */ 4922038315SVarun Wadekar #define STD_SMC_ACTIVE_FLAG_SHIFT 2 5022038315SVarun Wadekar #define STD_SMC_ACTIVE_FLAG_MASK 1 5122038315SVarun Wadekar #define get_std_smc_active_flag(state) (((state) >> STD_SMC_ACTIVE_FLAG_SHIFT) \ 5222038315SVarun Wadekar & STD_SMC_ACTIVE_FLAG_MASK) 5322038315SVarun Wadekar #define set_std_smc_active_flag(state) ((state) |= \ 5422038315SVarun Wadekar (1 << STD_SMC_ACTIVE_FLAG_SHIFT)) 5522038315SVarun Wadekar #define clr_std_smc_active_flag(state) ((state) &= \ 5622038315SVarun Wadekar ~(STD_SMC_ACTIVE_FLAG_MASK \ 5722038315SVarun Wadekar << STD_SMC_ACTIVE_FLAG_SHIFT)) 5822038315SVarun Wadekar 5922038315SVarun Wadekar /******************************************************************************* 60*6e159e7aSVarun Wadekar * Translate virtual address received from the NS world 61*6e159e7aSVarun Wadekar ******************************************************************************/ 62*6e159e7aSVarun Wadekar #define TLK_TRANSLATE_NS_VADDR 4 63*6e159e7aSVarun Wadekar 64*6e159e7aSVarun Wadekar /******************************************************************************* 6522038315SVarun Wadekar * Secure Payload execution state information i.e. aarch32 or aarch64 6622038315SVarun Wadekar ******************************************************************************/ 6722038315SVarun Wadekar #define SP_AARCH32 MODE_RW_32 6822038315SVarun Wadekar #define SP_AARCH64 MODE_RW_64 6922038315SVarun Wadekar 7022038315SVarun Wadekar /******************************************************************************* 7122038315SVarun Wadekar * Number of cpus that the present on this platform. TODO: Rely on a topology 7222038315SVarun Wadekar * tree to determine this in the future to avoid assumptions about mpidr 7322038315SVarun Wadekar * allocation 7422038315SVarun Wadekar ******************************************************************************/ 7522038315SVarun Wadekar #define TLKD_CORE_COUNT PLATFORM_CORE_COUNT 7622038315SVarun Wadekar 7722038315SVarun Wadekar /******************************************************************************* 7822038315SVarun Wadekar * Constants that allow assembler code to preserve callee-saved registers of the 7922038315SVarun Wadekar * C runtime context while performing a security state switch. 8022038315SVarun Wadekar ******************************************************************************/ 8122038315SVarun Wadekar #define TLKD_C_RT_CTX_X19 0x0 8222038315SVarun Wadekar #define TLKD_C_RT_CTX_X20 0x8 8322038315SVarun Wadekar #define TLKD_C_RT_CTX_X21 0x10 8422038315SVarun Wadekar #define TLKD_C_RT_CTX_X22 0x18 8522038315SVarun Wadekar #define TLKD_C_RT_CTX_X23 0x20 8622038315SVarun Wadekar #define TLKD_C_RT_CTX_X24 0x28 8722038315SVarun Wadekar #define TLKD_C_RT_CTX_X25 0x30 8822038315SVarun Wadekar #define TLKD_C_RT_CTX_X26 0x38 8922038315SVarun Wadekar #define TLKD_C_RT_CTX_X27 0x40 9022038315SVarun Wadekar #define TLKD_C_RT_CTX_X28 0x48 9122038315SVarun Wadekar #define TLKD_C_RT_CTX_X29 0x50 9222038315SVarun Wadekar #define TLKD_C_RT_CTX_X30 0x58 9322038315SVarun Wadekar #define TLKD_C_RT_CTX_SIZE 0x60 9422038315SVarun Wadekar #define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) 9522038315SVarun Wadekar 9622038315SVarun Wadekar #ifndef __ASSEMBLY__ 9722038315SVarun Wadekar 9822038315SVarun Wadekar #include <cassert.h> 9922038315SVarun Wadekar #include <stdint.h> 10022038315SVarun Wadekar 10122038315SVarun Wadekar /* AArch64 callee saved general purpose register context structure. */ 10222038315SVarun Wadekar DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES); 10322038315SVarun Wadekar 10422038315SVarun Wadekar /* 10522038315SVarun Wadekar * Compile time assertion to ensure that both the compiler and linker 10622038315SVarun Wadekar * have the same double word aligned view of the size of the C runtime 10722038315SVarun Wadekar * register context. 10822038315SVarun Wadekar */ 10922038315SVarun Wadekar CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 11022038315SVarun Wadekar assert_tlkd_c_rt_regs_size_mismatch); 11122038315SVarun Wadekar 11222038315SVarun Wadekar /******************************************************************************* 11322038315SVarun Wadekar * Structure which helps the SPD to maintain the per-cpu state of the SP. 11422038315SVarun Wadekar * 'state' - collection of flags to track SP state e.g. on/off 11522038315SVarun Wadekar * 'mpidr' - mpidr to associate a context with a cpu 11622038315SVarun Wadekar * 'c_rt_ctx' - stack address to restore C runtime context from after 11722038315SVarun Wadekar * returning from a synchronous entry into the SP. 11822038315SVarun Wadekar * 'cpu_ctx' - space to maintain SP architectural state 11922038315SVarun Wadekar * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 12022038315SVarun Wadekar * which will queried using the TSP_GET_ARGS SMC by TSP. 12122038315SVarun Wadekar ******************************************************************************/ 12222038315SVarun Wadekar typedef struct tlk_context { 12322038315SVarun Wadekar uint32_t state; 12422038315SVarun Wadekar uint64_t mpidr; 12522038315SVarun Wadekar uint64_t c_rt_ctx; 12622038315SVarun Wadekar cpu_context_t cpu_ctx; 12722038315SVarun Wadekar } tlk_context_t; 12822038315SVarun Wadekar 12922038315SVarun Wadekar /******************************************************************************* 13022038315SVarun Wadekar * Function & Data prototypes 13122038315SVarun Wadekar ******************************************************************************/ 132*6e159e7aSVarun Wadekar uint64_t tlkd_va_translate(uintptr_t va, int type); 13322038315SVarun Wadekar uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx); 13422038315SVarun Wadekar void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 13522038315SVarun Wadekar uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx); 13622038315SVarun Wadekar void __dead2 tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, 13722038315SVarun Wadekar uint64_t ret); 13822038315SVarun Wadekar void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, 13922038315SVarun Wadekar uint32_t rw, 14022038315SVarun Wadekar uint64_t pc, 14122038315SVarun Wadekar tlk_context_t *tlk_ctx); 14222038315SVarun Wadekar 14322038315SVarun Wadekar #endif /*__ASSEMBLY__*/ 14422038315SVarun Wadekar 14522038315SVarun Wadekar #endif /* __TLKD_PRIVATE_H__ */ 146