1*22038315SVarun Wadekar /* 2*22038315SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*22038315SVarun Wadekar * 4*22038315SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*22038315SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*22038315SVarun Wadekar * 7*22038315SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*22038315SVarun Wadekar * list of conditions and the following disclaimer. 9*22038315SVarun Wadekar * 10*22038315SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*22038315SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*22038315SVarun Wadekar * and/or other materials provided with the distribution. 13*22038315SVarun Wadekar * 14*22038315SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*22038315SVarun Wadekar * to endorse or promote products derived from this software without specific 16*22038315SVarun Wadekar * prior written permission. 17*22038315SVarun Wadekar * 18*22038315SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*22038315SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*22038315SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*22038315SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*22038315SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*22038315SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*22038315SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*22038315SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*22038315SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*22038315SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*22038315SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*22038315SVarun Wadekar */ 30*22038315SVarun Wadekar 31*22038315SVarun Wadekar #ifndef __TLKD_PRIVATE_H__ 32*22038315SVarun Wadekar #define __TLKD_PRIVATE_H__ 33*22038315SVarun Wadekar 34*22038315SVarun Wadekar #include <arch.h> 35*22038315SVarun Wadekar #include <context.h> 36*22038315SVarun Wadekar #include <interrupt_mgmt.h> 37*22038315SVarun Wadekar #include <platform_def.h> 38*22038315SVarun Wadekar #include <psci.h> 39*22038315SVarun Wadekar 40*22038315SVarun Wadekar /* 41*22038315SVarun Wadekar * This flag is used by the TLKD to determine if the SP is servicing a standard 42*22038315SVarun Wadekar * SMC request prior to programming the next entry into the SP e.g. if SP 43*22038315SVarun Wadekar * execution is preempted by a non-secure interrupt and handed control to the 44*22038315SVarun Wadekar * normal world. If another request which is distinct from what the SP was 45*22038315SVarun Wadekar * previously doing arrives, then this flag will be help the TLKD to either 46*22038315SVarun Wadekar * reject the new request or service it while ensuring that the previous context 47*22038315SVarun Wadekar * is not corrupted. 48*22038315SVarun Wadekar */ 49*22038315SVarun Wadekar #define STD_SMC_ACTIVE_FLAG_SHIFT 2 50*22038315SVarun Wadekar #define STD_SMC_ACTIVE_FLAG_MASK 1 51*22038315SVarun Wadekar #define get_std_smc_active_flag(state) (((state) >> STD_SMC_ACTIVE_FLAG_SHIFT) \ 52*22038315SVarun Wadekar & STD_SMC_ACTIVE_FLAG_MASK) 53*22038315SVarun Wadekar #define set_std_smc_active_flag(state) ((state) |= \ 54*22038315SVarun Wadekar (1 << STD_SMC_ACTIVE_FLAG_SHIFT)) 55*22038315SVarun Wadekar #define clr_std_smc_active_flag(state) ((state) &= \ 56*22038315SVarun Wadekar ~(STD_SMC_ACTIVE_FLAG_MASK \ 57*22038315SVarun Wadekar << STD_SMC_ACTIVE_FLAG_SHIFT)) 58*22038315SVarun Wadekar 59*22038315SVarun Wadekar /******************************************************************************* 60*22038315SVarun Wadekar * Secure Payload execution state information i.e. aarch32 or aarch64 61*22038315SVarun Wadekar ******************************************************************************/ 62*22038315SVarun Wadekar #define SP_AARCH32 MODE_RW_32 63*22038315SVarun Wadekar #define SP_AARCH64 MODE_RW_64 64*22038315SVarun Wadekar 65*22038315SVarun Wadekar /******************************************************************************* 66*22038315SVarun Wadekar * Number of cpus that the present on this platform. TODO: Rely on a topology 67*22038315SVarun Wadekar * tree to determine this in the future to avoid assumptions about mpidr 68*22038315SVarun Wadekar * allocation 69*22038315SVarun Wadekar ******************************************************************************/ 70*22038315SVarun Wadekar #define TLKD_CORE_COUNT PLATFORM_CORE_COUNT 71*22038315SVarun Wadekar 72*22038315SVarun Wadekar /******************************************************************************* 73*22038315SVarun Wadekar * Constants that allow assembler code to preserve callee-saved registers of the 74*22038315SVarun Wadekar * C runtime context while performing a security state switch. 75*22038315SVarun Wadekar ******************************************************************************/ 76*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X19 0x0 77*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X20 0x8 78*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X21 0x10 79*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X22 0x18 80*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X23 0x20 81*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X24 0x28 82*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X25 0x30 83*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X26 0x38 84*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X27 0x40 85*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X28 0x48 86*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X29 0x50 87*22038315SVarun Wadekar #define TLKD_C_RT_CTX_X30 0x58 88*22038315SVarun Wadekar #define TLKD_C_RT_CTX_SIZE 0x60 89*22038315SVarun Wadekar #define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) 90*22038315SVarun Wadekar 91*22038315SVarun Wadekar #ifndef __ASSEMBLY__ 92*22038315SVarun Wadekar 93*22038315SVarun Wadekar #include <cassert.h> 94*22038315SVarun Wadekar #include <stdint.h> 95*22038315SVarun Wadekar 96*22038315SVarun Wadekar /* AArch64 callee saved general purpose register context structure. */ 97*22038315SVarun Wadekar DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES); 98*22038315SVarun Wadekar 99*22038315SVarun Wadekar /* 100*22038315SVarun Wadekar * Compile time assertion to ensure that both the compiler and linker 101*22038315SVarun Wadekar * have the same double word aligned view of the size of the C runtime 102*22038315SVarun Wadekar * register context. 103*22038315SVarun Wadekar */ 104*22038315SVarun Wadekar CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 105*22038315SVarun Wadekar assert_tlkd_c_rt_regs_size_mismatch); 106*22038315SVarun Wadekar 107*22038315SVarun Wadekar /******************************************************************************* 108*22038315SVarun Wadekar * Structure which helps the SPD to maintain the per-cpu state of the SP. 109*22038315SVarun Wadekar * 'state' - collection of flags to track SP state e.g. on/off 110*22038315SVarun Wadekar * 'mpidr' - mpidr to associate a context with a cpu 111*22038315SVarun Wadekar * 'c_rt_ctx' - stack address to restore C runtime context from after 112*22038315SVarun Wadekar * returning from a synchronous entry into the SP. 113*22038315SVarun Wadekar * 'cpu_ctx' - space to maintain SP architectural state 114*22038315SVarun Wadekar * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 115*22038315SVarun Wadekar * which will queried using the TSP_GET_ARGS SMC by TSP. 116*22038315SVarun Wadekar ******************************************************************************/ 117*22038315SVarun Wadekar typedef struct tlk_context { 118*22038315SVarun Wadekar uint32_t state; 119*22038315SVarun Wadekar uint64_t mpidr; 120*22038315SVarun Wadekar uint64_t c_rt_ctx; 121*22038315SVarun Wadekar cpu_context_t cpu_ctx; 122*22038315SVarun Wadekar } tlk_context_t; 123*22038315SVarun Wadekar 124*22038315SVarun Wadekar /******************************************************************************* 125*22038315SVarun Wadekar * Function & Data prototypes 126*22038315SVarun Wadekar ******************************************************************************/ 127*22038315SVarun Wadekar uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx); 128*22038315SVarun Wadekar void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 129*22038315SVarun Wadekar uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx); 130*22038315SVarun Wadekar void __dead2 tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, 131*22038315SVarun Wadekar uint64_t ret); 132*22038315SVarun Wadekar void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, 133*22038315SVarun Wadekar uint32_t rw, 134*22038315SVarun Wadekar uint64_t pc, 135*22038315SVarun Wadekar tlk_context_t *tlk_ctx); 136*22038315SVarun Wadekar 137*22038315SVarun Wadekar #endif /*__ASSEMBLY__*/ 138*22038315SVarun Wadekar 139*22038315SVarun Wadekar #endif /* __TLKD_PRIVATE_H__ */ 140