122038315SVarun Wadekar /* 222038315SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 322038315SVarun Wadekar * 422038315SVarun Wadekar * Redistribution and use in source and binary forms, with or without 522038315SVarun Wadekar * modification, are permitted provided that the following conditions are met: 622038315SVarun Wadekar * 722038315SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 822038315SVarun Wadekar * list of conditions and the following disclaimer. 922038315SVarun Wadekar * 1022038315SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1122038315SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1222038315SVarun Wadekar * and/or other materials provided with the distribution. 1322038315SVarun Wadekar * 1422038315SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1522038315SVarun Wadekar * to endorse or promote products derived from this software without specific 1622038315SVarun Wadekar * prior written permission. 1722038315SVarun Wadekar * 1822038315SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1922038315SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2022038315SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2122038315SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2222038315SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2322038315SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2422038315SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2522038315SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2622038315SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2722038315SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2822038315SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2922038315SVarun Wadekar */ 3022038315SVarun Wadekar 31*cb790c5eSVarun Wadekar #include <arch_helpers.h> 32*cb790c5eSVarun Wadekar #include <assert.h> 33*cb790c5eSVarun Wadekar #include <bl_common.h> 34*cb790c5eSVarun Wadekar #include <context_mgmt.h> 35*cb790c5eSVarun Wadekar #include <debug.h> 3622038315SVarun Wadekar #include <psci.h> 37*cb790c5eSVarun Wadekar #include <tlk.h> 38*cb790c5eSVarun Wadekar 39*cb790c5eSVarun Wadekar #include "tlkd_private.h" 40*cb790c5eSVarun Wadekar 41*cb790c5eSVarun Wadekar extern tlk_context_t tlk_ctx; 4222038315SVarun Wadekar 4322038315SVarun Wadekar #define MPIDR_CPU0 0x80000000 4422038315SVarun Wadekar 4522038315SVarun Wadekar /******************************************************************************* 4622038315SVarun Wadekar * Return the type of payload TLKD is dealing with. Report the current 4722038315SVarun Wadekar * resident cpu (mpidr format) if it is a UP/UP migratable payload. 4822038315SVarun Wadekar ******************************************************************************/ 4922038315SVarun Wadekar static int32_t cpu_migrate_info(uint64_t *resident_cpu) 5022038315SVarun Wadekar { 5122038315SVarun Wadekar /* the payload runs only on CPU0 */ 5222038315SVarun Wadekar *resident_cpu = MPIDR_CPU0; 5322038315SVarun Wadekar 5422038315SVarun Wadekar /* Uniprocessor, not migrate capable payload */ 5522038315SVarun Wadekar return PSCI_TOS_NOT_UP_MIG_CAP; 5622038315SVarun Wadekar } 5722038315SVarun Wadekar 5822038315SVarun Wadekar /******************************************************************************* 59*cb790c5eSVarun Wadekar * This cpu is being suspended. Inform TLK of the SYSTEM_SUSPEND event, so 60*cb790c5eSVarun Wadekar * that it can pass this information to its Trusted Apps. 61*cb790c5eSVarun Wadekar ******************************************************************************/ 62*cb790c5eSVarun Wadekar static void cpu_suspend_handler(uint64_t suspend_level) 63*cb790c5eSVarun Wadekar { 64*cb790c5eSVarun Wadekar gp_regs_t *gp_regs; 65*cb790c5eSVarun Wadekar int cpu = read_mpidr() & MPIDR_CPU_MASK; 66*cb790c5eSVarun Wadekar int32_t rc = 0; 67*cb790c5eSVarun Wadekar 68*cb790c5eSVarun Wadekar /* 69*cb790c5eSVarun Wadekar * TLK runs only on CPU0 and suspends its Trusted Apps during 70*cb790c5eSVarun Wadekar * SYSTEM_SUSPEND. It has no role to play during CPU_SUSPEND. 71*cb790c5eSVarun Wadekar */ 72*cb790c5eSVarun Wadekar if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) 73*cb790c5eSVarun Wadekar return; 74*cb790c5eSVarun Wadekar 75*cb790c5eSVarun Wadekar /* pass system suspend event to TLK */ 76*cb790c5eSVarun Wadekar gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); 77*cb790c5eSVarun Wadekar write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); 78*cb790c5eSVarun Wadekar 79*cb790c5eSVarun Wadekar /* Program the entry point and enter TLK */ 80*cb790c5eSVarun Wadekar rc = tlkd_synchronous_sp_entry(&tlk_ctx); 81*cb790c5eSVarun Wadekar 82*cb790c5eSVarun Wadekar /* 83*cb790c5eSVarun Wadekar * Read the response from TLK. A non-zero return means that 84*cb790c5eSVarun Wadekar * something went wrong while communicating with it. 85*cb790c5eSVarun Wadekar */ 86*cb790c5eSVarun Wadekar if (rc != 0) 87*cb790c5eSVarun Wadekar panic(); 88*cb790c5eSVarun Wadekar } 89*cb790c5eSVarun Wadekar 90*cb790c5eSVarun Wadekar /******************************************************************************* 91*cb790c5eSVarun Wadekar * This cpu is being resumed. Inform TLK of the SYSTEM_SUSPEND exit, so 92*cb790c5eSVarun Wadekar * that it can pass this information to its Trusted Apps. 93*cb790c5eSVarun Wadekar ******************************************************************************/ 94*cb790c5eSVarun Wadekar static void cpu_resume_handler(uint64_t suspend_level) 95*cb790c5eSVarun Wadekar { 96*cb790c5eSVarun Wadekar gp_regs_t *gp_regs; 97*cb790c5eSVarun Wadekar int cpu = read_mpidr() & MPIDR_CPU_MASK; 98*cb790c5eSVarun Wadekar int32_t rc = 0; 99*cb790c5eSVarun Wadekar 100*cb790c5eSVarun Wadekar /* 101*cb790c5eSVarun Wadekar * TLK runs only on CPU0 and resumes its Trusted Apps during 102*cb790c5eSVarun Wadekar * SYSTEM_SUSPEND exit. It has no role to play during CPU_SUSPEND 103*cb790c5eSVarun Wadekar * exit. 104*cb790c5eSVarun Wadekar */ 105*cb790c5eSVarun Wadekar if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) 106*cb790c5eSVarun Wadekar return; 107*cb790c5eSVarun Wadekar 108*cb790c5eSVarun Wadekar /* pass system resume event to TLK */ 109*cb790c5eSVarun Wadekar gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); 110*cb790c5eSVarun Wadekar write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); 111*cb790c5eSVarun Wadekar 112*cb790c5eSVarun Wadekar /* Program the entry point and enter TLK */ 113*cb790c5eSVarun Wadekar rc = tlkd_synchronous_sp_entry(&tlk_ctx); 114*cb790c5eSVarun Wadekar 115*cb790c5eSVarun Wadekar /* 116*cb790c5eSVarun Wadekar * Read the response from TLK. A non-zero return means that 117*cb790c5eSVarun Wadekar * something went wrong while communicating with it. 118*cb790c5eSVarun Wadekar */ 119*cb790c5eSVarun Wadekar if (rc != 0) 120*cb790c5eSVarun Wadekar panic(); 121*cb790c5eSVarun Wadekar } 122*cb790c5eSVarun Wadekar 123*cb790c5eSVarun Wadekar /******************************************************************************* 124*cb790c5eSVarun Wadekar * System is about to be reset. Inform the SP to allow any book-keeping 125*cb790c5eSVarun Wadekar ******************************************************************************/ 126*cb790c5eSVarun Wadekar static void system_off_handler(void) 127*cb790c5eSVarun Wadekar { 128*cb790c5eSVarun Wadekar int cpu = read_mpidr() & MPIDR_CPU_MASK; 129*cb790c5eSVarun Wadekar gp_regs_t *gp_regs; 130*cb790c5eSVarun Wadekar 131*cb790c5eSVarun Wadekar /* TLK runs only on CPU0 */ 132*cb790c5eSVarun Wadekar if (cpu != 0) 133*cb790c5eSVarun Wadekar return; 134*cb790c5eSVarun Wadekar 135*cb790c5eSVarun Wadekar /* pass system off/reset events to TLK */ 136*cb790c5eSVarun Wadekar gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); 137*cb790c5eSVarun Wadekar write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF); 138*cb790c5eSVarun Wadekar 139*cb790c5eSVarun Wadekar /* 140*cb790c5eSVarun Wadekar * Enter the SP. We do not care about the return value because we 141*cb790c5eSVarun Wadekar * must continue with the shutdown anyway. 142*cb790c5eSVarun Wadekar */ 143*cb790c5eSVarun Wadekar (void)tlkd_synchronous_sp_entry(&tlk_ctx); 144*cb790c5eSVarun Wadekar } 145*cb790c5eSVarun Wadekar 146*cb790c5eSVarun Wadekar /******************************************************************************* 14722038315SVarun Wadekar * Structure populated by the Dispatcher to be given a chance to perform any 14822038315SVarun Wadekar * bookkeeping before PSCI executes a power mgmt. operation. 14922038315SVarun Wadekar ******************************************************************************/ 15022038315SVarun Wadekar const spd_pm_ops_t tlkd_pm_ops = { 15122038315SVarun Wadekar .svc_migrate_info = cpu_migrate_info, 152*cb790c5eSVarun Wadekar .svc_suspend = cpu_suspend_handler, 153*cb790c5eSVarun Wadekar .svc_suspend_finish = cpu_resume_handler, 154*cb790c5eSVarun Wadekar .svc_system_off = system_off_handler, 155*cb790c5eSVarun Wadekar .svc_system_reset = system_off_handler 15622038315SVarun Wadekar }; 157