1*22038315SVarun Wadekar /* 2*22038315SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*22038315SVarun Wadekar * 4*22038315SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*22038315SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*22038315SVarun Wadekar * 7*22038315SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*22038315SVarun Wadekar * list of conditions and the following disclaimer. 9*22038315SVarun Wadekar * 10*22038315SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*22038315SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*22038315SVarun Wadekar * and/or other materials provided with the distribution. 13*22038315SVarun Wadekar * 14*22038315SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*22038315SVarun Wadekar * to endorse or promote products derived from this software without specific 16*22038315SVarun Wadekar * prior written permission. 17*22038315SVarun Wadekar * 18*22038315SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*22038315SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*22038315SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*22038315SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*22038315SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*22038315SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*22038315SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*22038315SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*22038315SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*22038315SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*22038315SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*22038315SVarun Wadekar */ 30*22038315SVarun Wadekar 31*22038315SVarun Wadekar #include <psci.h> 32*22038315SVarun Wadekar 33*22038315SVarun Wadekar #define MPIDR_CPU0 0x80000000 34*22038315SVarun Wadekar 35*22038315SVarun Wadekar /******************************************************************************* 36*22038315SVarun Wadekar * Return the type of payload TLKD is dealing with. Report the current 37*22038315SVarun Wadekar * resident cpu (mpidr format) if it is a UP/UP migratable payload. 38*22038315SVarun Wadekar ******************************************************************************/ 39*22038315SVarun Wadekar static int32_t cpu_migrate_info(uint64_t *resident_cpu) 40*22038315SVarun Wadekar { 41*22038315SVarun Wadekar /* the payload runs only on CPU0 */ 42*22038315SVarun Wadekar *resident_cpu = MPIDR_CPU0; 43*22038315SVarun Wadekar 44*22038315SVarun Wadekar /* Uniprocessor, not migrate capable payload */ 45*22038315SVarun Wadekar return PSCI_TOS_NOT_UP_MIG_CAP; 46*22038315SVarun Wadekar } 47*22038315SVarun Wadekar 48*22038315SVarun Wadekar /******************************************************************************* 49*22038315SVarun Wadekar * Structure populated by the Dispatcher to be given a chance to perform any 50*22038315SVarun Wadekar * bookkeeping before PSCI executes a power mgmt. operation. 51*22038315SVarun Wadekar ******************************************************************************/ 52*22038315SVarun Wadekar const spd_pm_ops_t tlkd_pm_ops = { 53*22038315SVarun Wadekar .svc_migrate_info = cpu_migrate_info, 54*22038315SVarun Wadekar }; 55