1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 /******************************************************************************* 33 * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a 34 * plug-in component to the Secure Monitor, registered as a runtime service. The 35 * SPD is expected to be a functional extension of the Secure Payload (SP) that 36 * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting 37 * the Trusted OS/Applications range to the dispatcher. The SPD will either 38 * handle the request locally or delegate it to the Secure Payload. It is also 39 * responsible for initialising and maintaining communication with the SP. 40 ******************************************************************************/ 41 #include <arch_helpers.h> 42 #include <assert.h> 43 #include <bl_common.h> 44 #include <bl31.h> 45 #include <context_mgmt.h> 46 #include <debug.h> 47 #include <errno.h> 48 #include <platform.h> 49 #include <runtime_svc.h> 50 #include <stddef.h> 51 #include <uuid.h> 52 #include "opteed_private.h" 53 #include "teesmc_opteed_macros.h" 54 #include "teesmc_opteed.h" 55 56 /******************************************************************************* 57 * Address of the entrypoint vector table in OPTEE. It is 58 * initialised once on the primary core after a cold boot. 59 ******************************************************************************/ 60 optee_vectors_t *optee_vectors; 61 62 /******************************************************************************* 63 * Array to keep track of per-cpu OPTEE state 64 ******************************************************************************/ 65 optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; 66 uint32_t opteed_rw; 67 68 69 70 static int32_t opteed_init(void); 71 72 /******************************************************************************* 73 * This function is the handler registered for S-EL1 interrupts by the 74 * OPTEED. It validates the interrupt and upon success arranges entry into 75 * the OPTEE at 'optee_fiq_entry()' for handling the interrupt. 76 ******************************************************************************/ 77 static uint64_t opteed_sel1_interrupt_handler(uint32_t id, 78 uint32_t flags, 79 void *handle, 80 void *cookie) 81 { 82 uint32_t linear_id; 83 optee_context_t *optee_ctx; 84 85 /* Check the security state when the exception was generated */ 86 assert(get_interrupt_src_ss(flags) == NON_SECURE); 87 88 /* Sanity check the pointer to this cpu's context */ 89 assert(handle == cm_get_context(NON_SECURE)); 90 91 /* Save the non-secure context before entering the OPTEE */ 92 cm_el1_sysregs_context_save(NON_SECURE); 93 94 /* Get a reference to this cpu's OPTEE context */ 95 linear_id = plat_my_core_pos(); 96 optee_ctx = &opteed_sp_context[linear_id]; 97 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); 98 99 cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry); 100 cm_el1_sysregs_context_restore(SECURE); 101 cm_set_next_eret_context(SECURE); 102 103 /* 104 * Tell the OPTEE that it has to handle an FIQ (synchronously). 105 * Also the instruction in normal world where the interrupt was 106 * generated is passed for debugging purposes. It is safe to 107 * retrieve this address from ELR_EL3 as the secure context will 108 * not take effect until el3_exit(). 109 */ 110 SMC_RET1(&optee_ctx->cpu_ctx, read_elr_el3()); 111 } 112 113 /******************************************************************************* 114 * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type 115 * (aarch32/aarch64) if not already known and initialises the context for entry 116 * into OPTEE for its initialization. 117 ******************************************************************************/ 118 int32_t opteed_setup(void) 119 { 120 entry_point_info_t *optee_ep_info; 121 uint32_t linear_id; 122 123 linear_id = plat_my_core_pos(); 124 125 /* 126 * Get information about the Secure Payload (BL32) image. Its 127 * absence is a critical failure. TODO: Add support to 128 * conditionally include the SPD service 129 */ 130 optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 131 if (!optee_ep_info) { 132 WARN("No OPTEE provided by BL2 boot loader, Booting device" 133 " without OPTEE initialization. SMC`s destined for OPTEE" 134 " will return SMC_UNK\n"); 135 return 1; 136 } 137 138 /* 139 * If there's no valid entry point for SP, we return a non-zero value 140 * signalling failure initializing the service. We bail out without 141 * registering any handlers 142 */ 143 if (!optee_ep_info->pc) 144 return 1; 145 146 /* 147 * We could inspect the SP image and determine it's execution 148 * state i.e whether AArch32 or AArch64. Assuming it's AArch32 149 * for the time being. 150 */ 151 opteed_rw = OPTEE_AARCH32; 152 opteed_init_optee_ep_state(optee_ep_info, 153 opteed_rw, 154 optee_ep_info->pc, 155 &opteed_sp_context[linear_id]); 156 157 /* 158 * All OPTEED initialization done. Now register our init function with 159 * BL31 for deferred invocation 160 */ 161 bl31_register_bl32_init(&opteed_init); 162 163 return 0; 164 } 165 166 /******************************************************************************* 167 * This function passes control to the OPTEE image (BL32) for the first time 168 * on the primary cpu after a cold boot. It assumes that a valid secure 169 * context has already been created by opteed_setup() which can be directly 170 * used. It also assumes that a valid non-secure context has been 171 * initialised by PSCI so it does not need to save and restore any 172 * non-secure state. This function performs a synchronous entry into 173 * OPTEE. OPTEE passes control back to this routine through a SMC. 174 ******************************************************************************/ 175 static int32_t opteed_init(void) 176 { 177 uint32_t linear_id = plat_my_core_pos(); 178 optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; 179 entry_point_info_t *optee_entry_point; 180 uint64_t rc; 181 182 /* 183 * Get information about the OPTEE (BL32) image. Its 184 * absence is a critical failure. 185 */ 186 optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); 187 assert(optee_entry_point); 188 189 cm_init_my_context(optee_entry_point); 190 191 /* 192 * Arrange for an entry into OPTEE. It will be returned via 193 * OPTEE_ENTRY_DONE case 194 */ 195 rc = opteed_synchronous_sp_entry(optee_ctx); 196 assert(rc != 0); 197 198 return rc; 199 } 200 201 202 /******************************************************************************* 203 * This function is responsible for handling all SMCs in the Trusted OS/App 204 * range from the non-secure state as defined in the SMC Calling Convention 205 * Document. It is also responsible for communicating with the Secure 206 * payload to delegate work and return results back to the non-secure 207 * state. Lastly it will also return any information that OPTEE needs to do 208 * the work assigned to it. 209 ******************************************************************************/ 210 uint64_t opteed_smc_handler(uint32_t smc_fid, 211 uint64_t x1, 212 uint64_t x2, 213 uint64_t x3, 214 uint64_t x4, 215 void *cookie, 216 void *handle, 217 uint64_t flags) 218 { 219 cpu_context_t *ns_cpu_context; 220 uint32_t linear_id = plat_my_core_pos(); 221 optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; 222 uint64_t rc; 223 224 /* 225 * Determine which security state this SMC originated from 226 */ 227 228 if (is_caller_non_secure(flags)) { 229 /* 230 * This is a fresh request from the non-secure client. 231 * The parameters are in x1 and x2. Figure out which 232 * registers need to be preserved, save the non-secure 233 * state and send the request to the secure payload. 234 */ 235 assert(handle == cm_get_context(NON_SECURE)); 236 237 cm_el1_sysregs_context_save(NON_SECURE); 238 239 /* 240 * We are done stashing the non-secure context. Ask the 241 * OPTEE to do the work now. 242 */ 243 244 /* 245 * Verify if there is a valid context to use, copy the 246 * operation type and parameters to the secure context 247 * and jump to the fast smc entry point in the secure 248 * payload. Entry into S-EL1 will take place upon exit 249 * from this function. 250 */ 251 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); 252 253 /* Set appropriate entry for SMC. 254 * We expect OPTEE to manage the PSTATE.I and PSTATE.F 255 * flags as appropriate. 256 */ 257 if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { 258 cm_set_elr_el3(SECURE, (uint64_t) 259 &optee_vectors->fast_smc_entry); 260 } else { 261 cm_set_elr_el3(SECURE, (uint64_t) 262 &optee_vectors->std_smc_entry); 263 } 264 265 cm_el1_sysregs_context_restore(SECURE); 266 cm_set_next_eret_context(SECURE); 267 268 /* Propagate hypervisor client ID */ 269 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), 270 CTX_GPREG_X7, 271 read_ctx_reg(get_gpregs_ctx(handle), 272 CTX_GPREG_X7)); 273 274 SMC_RET4(&optee_ctx->cpu_ctx, smc_fid, x1, x2, x3); 275 } 276 277 /* 278 * Returning from OPTEE 279 */ 280 281 switch (smc_fid) { 282 /* 283 * OPTEE has finished initialising itself after a cold boot 284 */ 285 case TEESMC_OPTEED_RETURN_ENTRY_DONE: 286 /* 287 * Stash the OPTEE entry points information. This is done 288 * only once on the primary cpu 289 */ 290 assert(optee_vectors == NULL); 291 optee_vectors = (optee_vectors_t *) x1; 292 293 if (optee_vectors) { 294 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); 295 296 /* 297 * OPTEE has been successfully initialized. 298 * Register power management hooks with PSCI 299 */ 300 psci_register_spd_pm_hook(&opteed_pm); 301 302 /* 303 * Register an interrupt handler for S-EL1 interrupts 304 * when generated during code executing in the 305 * non-secure state. 306 */ 307 flags = 0; 308 set_interrupt_rm_flag(flags, NON_SECURE); 309 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 310 opteed_sel1_interrupt_handler, 311 flags); 312 if (rc) 313 panic(); 314 } 315 316 /* 317 * OPTEE reports completion. The OPTEED must have initiated 318 * the original request through a synchronous entry into 319 * OPTEE. Jump back to the original C runtime context. 320 */ 321 opteed_synchronous_sp_exit(optee_ctx, x1); 322 323 324 /* 325 * These function IDs is used only by OP-TEE to indicate it has 326 * finished: 327 * 1. turning itself on in response to an earlier psci 328 * cpu_on request 329 * 2. resuming itself after an earlier psci cpu_suspend 330 * request. 331 */ 332 case TEESMC_OPTEED_RETURN_ON_DONE: 333 case TEESMC_OPTEED_RETURN_RESUME_DONE: 334 335 336 /* 337 * These function IDs is used only by the SP to indicate it has 338 * finished: 339 * 1. suspending itself after an earlier psci cpu_suspend 340 * request. 341 * 2. turning itself off in response to an earlier psci 342 * cpu_off request. 343 */ 344 case TEESMC_OPTEED_RETURN_OFF_DONE: 345 case TEESMC_OPTEED_RETURN_SUSPEND_DONE: 346 case TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE: 347 case TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE: 348 349 /* 350 * OPTEE reports completion. The OPTEED must have initiated the 351 * original request through a synchronous entry into OPTEE. 352 * Jump back to the original C runtime context, and pass x1 as 353 * return value to the caller 354 */ 355 opteed_synchronous_sp_exit(optee_ctx, x1); 356 357 /* 358 * OPTEE is returning from a call or being preempted from a call, in 359 * either case execution should resume in the normal world. 360 */ 361 case TEESMC_OPTEED_RETURN_CALL_DONE: 362 /* 363 * This is the result from the secure client of an 364 * earlier request. The results are in x0-x3. Copy it 365 * into the non-secure context, save the secure state 366 * and return to the non-secure state. 367 */ 368 assert(handle == cm_get_context(SECURE)); 369 cm_el1_sysregs_context_save(SECURE); 370 371 /* Get a reference to the non-secure context */ 372 ns_cpu_context = cm_get_context(NON_SECURE); 373 assert(ns_cpu_context); 374 375 /* Restore non-secure state */ 376 cm_el1_sysregs_context_restore(NON_SECURE); 377 cm_set_next_eret_context(NON_SECURE); 378 379 SMC_RET4(ns_cpu_context, x1, x2, x3, x4); 380 381 /* 382 * OPTEE has finished handling a S-EL1 FIQ interrupt. Execution 383 * should resume in the normal world. 384 */ 385 case TEESMC_OPTEED_RETURN_FIQ_DONE: 386 /* Get a reference to the non-secure context */ 387 ns_cpu_context = cm_get_context(NON_SECURE); 388 assert(ns_cpu_context); 389 390 /* 391 * Restore non-secure state. There is no need to save the 392 * secure system register context since OPTEE was supposed 393 * to preserve it during S-EL1 interrupt handling. 394 */ 395 cm_el1_sysregs_context_restore(NON_SECURE); 396 cm_set_next_eret_context(NON_SECURE); 397 398 SMC_RET0((uint64_t) ns_cpu_context); 399 400 default: 401 panic(); 402 } 403 } 404 405 /* Define an OPTEED runtime service descriptor for fast SMC calls */ 406 DECLARE_RT_SVC( 407 opteed_fast, 408 409 OEN_TOS_START, 410 OEN_TOS_END, 411 SMC_TYPE_FAST, 412 opteed_setup, 413 opteed_smc_handler 414 ); 415 416 /* Define an OPTEED runtime service descriptor for standard SMC calls */ 417 DECLARE_RT_SVC( 418 opteed_std, 419 420 OEN_TOS_START, 421 OEN_TOS_END, 422 SMC_TYPE_STD, 423 NULL, 424 opteed_smc_handler 425 ); 426