1*6f625747SDouglas RaillardARM Trusted Firmware - version 1.3 2*6f625747SDouglas Raillard================================== 3*6f625747SDouglas Raillard 4*6f625747SDouglas RaillardARM Trusted Firmware provides a reference implementation of secure world 5*6f625747SDouglas Raillardsoftware for `ARMv8-A`_, including a `Secure Monitor`_ executing at 6*6f625747SDouglas RaillardException Level 3 (EL3). It implements various ARM interface standards, such as 7*6f625747SDouglas Raillardthe Power State Coordination Interface (`PSCI`_), Trusted Board Boot Requirements 8*6f625747SDouglas Raillard(TBBR, ARM DEN0006C-1) and `SMC Calling Convention`_. As far as possible 9*6f625747SDouglas Raillardthe code is designed for reuse or porting to other ARMv8-A model and hardware 10*6f625747SDouglas Raillardplatforms. 11*6f625747SDouglas Raillard 12*6f625747SDouglas RaillardARM will continue development in collaboration with interested parties to 13*6f625747SDouglas Raillardprovide a full reference implementation of PSCI, TBBR and Secure Monitor code 14*6f625747SDouglas Raillardto the benefit of all developers working with ARMv8-A TrustZone technology. 15*6f625747SDouglas Raillard 16*6f625747SDouglas RaillardLicense 17*6f625747SDouglas Raillard------- 18*6f625747SDouglas Raillard 19*6f625747SDouglas RaillardThe software is provided under a BSD-3-Clause `license`_. Contributions to this 20*6f625747SDouglas Raillardproject are accepted under the same license with developer sign-off as 21*6f625747SDouglas Raillarddescribed in the `Contributing Guidelines`_. 22*6f625747SDouglas Raillard 23*6f625747SDouglas RaillardThis project contains code from other projects as listed below. The original 24*6f625747SDouglas Raillardlicense text is included in those source files. 25*6f625747SDouglas Raillard 26*6f625747SDouglas Raillard- The stdlib source code is derived from FreeBSD code. 27*6f625747SDouglas Raillard 28*6f625747SDouglas Raillard- The libfdt source code is dual licensed. It is used by this project under 29*6f625747SDouglas Raillard the terms of the BSD-2-Clause license. 30*6f625747SDouglas Raillard 31*6f625747SDouglas RaillardThis Release 32*6f625747SDouglas Raillard------------ 33*6f625747SDouglas Raillard 34*6f625747SDouglas RaillardThis release provides a suitable starting point for productization of secure 35*6f625747SDouglas Raillardworld boot and runtime firmware, executing in either the AArch32 or AArch64 36*6f625747SDouglas Raillardexecution state. 37*6f625747SDouglas Raillard 38*6f625747SDouglas RaillardUsers are encouraged to do their own security validation, including penetration 39*6f625747SDouglas Raillardtesting, on any secure world code derived from ARM Trusted Firmware. 40*6f625747SDouglas Raillard 41*6f625747SDouglas RaillardFunctionality 42*6f625747SDouglas Raillard~~~~~~~~~~~~~ 43*6f625747SDouglas Raillard 44*6f625747SDouglas Raillard- Initialization of the secure world (for example, exception vectors, control 45*6f625747SDouglas Raillard registers, interrupt controller and interrupts for the platform), before 46*6f625747SDouglas Raillard transitioning into the normal world at the Exception Level and Register 47*6f625747SDouglas Raillard Width specified by the platform. 48*6f625747SDouglas Raillard 49*6f625747SDouglas Raillard- Library support for CPU specific reset and power down sequences. This 50*6f625747SDouglas Raillard includes support for errata workarounds. 51*6f625747SDouglas Raillard 52*6f625747SDouglas Raillard- Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt 53*6f625747SDouglas Raillard Controller specifications (GICv2 and GICv3). The latter also enables GICv3 54*6f625747SDouglas Raillard hardware systems that do not contain legacy GICv2 support. 55*6f625747SDouglas Raillard 56*6f625747SDouglas Raillard- Drivers to enable standard initialization of ARM System IP, for example 57*6f625747SDouglas Raillard Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network 58*6f625747SDouglas Raillard Interconnect (NIC) and TrustZone Controller (TZC). 59*6f625747SDouglas Raillard 60*6f625747SDouglas Raillard- SMC (Secure Monitor Call) handling, conforming to the 61*6f625747SDouglas Raillard `SMC Calling Convention`_ using an EL3 runtime services framework. 62*6f625747SDouglas Raillard 63*6f625747SDouglas Raillard- `PSCI`_ library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle 64*6f625747SDouglas Raillard and System Shutdown/Reset/Suspend use-cases. 65*6f625747SDouglas Raillard This library is pre-integrated with the provided AArch64 EL3 Runtime 66*6f625747SDouglas Raillard Software, and is also suitable for integration into other EL3 Runtime 67*6f625747SDouglas Raillard Software. 68*6f625747SDouglas Raillard 69*6f625747SDouglas Raillard- A minimal AArch32 Secure Payload to demonstrate `PSCI`_ library integration 70*6f625747SDouglas Raillard on platforms with AArch32 EL3 Runtime Software. 71*6f625747SDouglas Raillard 72*6f625747SDouglas Raillard- Secure Monitor library code such as world switching, EL1 context management 73*6f625747SDouglas Raillard and interrupt routing. 74*6f625747SDouglas Raillard When using the provided AArch64 EL3 Runtime Software, this must be 75*6f625747SDouglas Raillard integrated with a Secure-EL1 Payload Dispatcher (SPD) component to 76*6f625747SDouglas Raillard customize the interaction with a Secure-EL1 Payload (SP), for example a 77*6f625747SDouglas Raillard Secure OS. 78*6f625747SDouglas Raillard 79*6f625747SDouglas Raillard- A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure 80*6f625747SDouglas Raillard Monitor functionality and Secure-EL1 interaction with PSCI. 81*6f625747SDouglas Raillard 82*6f625747SDouglas Raillard- AArch64 SPDs for the `OP-TEE Secure OS`_ and `NVidia Trusted Little Kernel`_. 83*6f625747SDouglas Raillard 84*6f625747SDouglas Raillard- A Trusted Board Boot implementation, conforming to all mandatory TBBR 85*6f625747SDouglas Raillard requirements. This includes image authentication using certificates, a 86*6f625747SDouglas Raillard Firmware Update (or recovery mode) boot flow, and packaging of the various 87*6f625747SDouglas Raillard firmware images into a Firmware Image Package (FIP) to be loaded from 88*6f625747SDouglas Raillard non-volatile storage. 89*6f625747SDouglas Raillard The TBBR implementation is currently only supported in the AArch64 build. 90*6f625747SDouglas Raillard 91*6f625747SDouglas Raillard- Support for alternative boot flows. Some platforms have their own boot 92*6f625747SDouglas Raillard firmware and only require the AArch64 EL3 Runtime Software provided by this 93*6f625747SDouglas Raillard project. Other platforms require minimal initialization before booting 94*6f625747SDouglas Raillard into an arbitrary EL3 payload. 95*6f625747SDouglas Raillard 96*6f625747SDouglas RaillardFor a full description of functionality and implementation details, please 97*6f625747SDouglas Raillardsee the `Firmware Design`_ and supporting documentation. The `Change Log`_ 98*6f625747SDouglas Raillardprovides details of changes made since the last release. 99*6f625747SDouglas Raillard 100*6f625747SDouglas RaillardPlatforms 101*6f625747SDouglas Raillard~~~~~~~~~ 102*6f625747SDouglas Raillard 103*6f625747SDouglas RaillardThe AArch64 build of this release has been tested on variants r0, r1 and r2 104*6f625747SDouglas Raillardof the `Juno ARM Development Platform`_ with `Linaro Release 16.06`_. 105*6f625747SDouglas Raillard 106*6f625747SDouglas RaillardThe AArch64 build of this release has been tested on the following ARM 107*6f625747SDouglas Raillard`FVP`_\ s (64-bit host machine only, with `Linaro Release 16.06`_): 108*6f625747SDouglas Raillard 109*6f625747SDouglas Raillard- ``Foundation_Platform`` (Version 10.1, Build 10.1.32) 110*6f625747SDouglas Raillard- ``FVP_Base_AEMv8A-AEMv8A`` (Version 7.7, Build 0.8.7701) 111*6f625747SDouglas Raillard- ``FVP_Base_Cortex-A57x4-A53x4`` (Version 7.7, Build 0.8.7701) 112*6f625747SDouglas Raillard- ``FVP_Base_Cortex-A57x1-A53x1`` (Version 7.7, Build 0.8.7701) 113*6f625747SDouglas Raillard- ``FVP_Base_Cortex-A57x2-A53x4`` (Version 7.7, Build 0.8.7701) 114*6f625747SDouglas Raillard 115*6f625747SDouglas RaillardThe AArch32 build of this release has been tested on the following ARM 116*6f625747SDouglas Raillard`FVP`_\ s (64-bit host machine only, with `Linaro Release 16.06`_): 117*6f625747SDouglas Raillard 118*6f625747SDouglas Raillard- ``FVP_Base_AEMv8A-AEMv8A`` (Version 7.7, Build 0.8.7701) 119*6f625747SDouglas Raillard- ``FVP_Base_Cortex-A32x4`` (Version 10.1, Build 10.1.32) 120*6f625747SDouglas Raillard 121*6f625747SDouglas RaillardThe Foundation FVP can be downloaded free of charge. The Base FVPs can be 122*6f625747SDouglas Raillardlicensed from ARM: see `www.arm.com/fvp`_. 123*6f625747SDouglas Raillard 124*6f625747SDouglas RaillardThis release also contains the following platform support: 125*6f625747SDouglas Raillard 126*6f625747SDouglas Raillard- MediaTek MT6795 and MT8173 SoCs 127*6f625747SDouglas Raillard- NVidia T210 and T132 SoCs 128*6f625747SDouglas Raillard- QEMU emulator 129*6f625747SDouglas Raillard- RockChip RK3368 and RK3399 SoCs 130*6f625747SDouglas Raillard- Xilinx Zynq UltraScale + MPSoC 131*6f625747SDouglas Raillard 132*6f625747SDouglas RaillardStill to Come 133*6f625747SDouglas Raillard~~~~~~~~~~~~~ 134*6f625747SDouglas Raillard 135*6f625747SDouglas Raillard- AArch32 TBBR support and ongoing TBBR alignment. 136*6f625747SDouglas Raillard 137*6f625747SDouglas Raillard- More platform support. 138*6f625747SDouglas Raillard 139*6f625747SDouglas Raillard- Ongoing support for new architectural features, CPUs and System IP. 140*6f625747SDouglas Raillard 141*6f625747SDouglas Raillard- Ongoing `PSCI`_ alignment and feature support. 142*6f625747SDouglas Raillard 143*6f625747SDouglas Raillard- Ongoing security hardening, optimization and quality improvements. 144*6f625747SDouglas Raillard 145*6f625747SDouglas RaillardFor a full list of detailed issues in the current code, please see the 146*6f625747SDouglas Raillard`Change Log`_ and the `GitHub issue tracker`_. 147*6f625747SDouglas Raillard 148*6f625747SDouglas RaillardGetting Started 149*6f625747SDouglas Raillard--------------- 150*6f625747SDouglas Raillard 151*6f625747SDouglas RaillardGet the Trusted Firmware source code from 152*6f625747SDouglas Raillard`GitHub`_. 153*6f625747SDouglas Raillard 154*6f625747SDouglas RaillardSee the `User Guide`_ for instructions on how to install, build and use 155*6f625747SDouglas Raillardthe Trusted Firmware with the ARM `FVP`_\ s. 156*6f625747SDouglas Raillard 157*6f625747SDouglas RaillardSee the `Firmware Design`_ for information on how the ARM Trusted Firmware works. 158*6f625747SDouglas Raillard 159*6f625747SDouglas RaillardSee the `Porting Guide`_ as well for information about how to use this 160*6f625747SDouglas Raillardsoftware on another ARMv8-A platform. 161*6f625747SDouglas Raillard 162*6f625747SDouglas RaillardSee the `Contributing Guidelines`_ for information on how to contribute to this 163*6f625747SDouglas Raillardproject and the `Acknowledgments`_ file for a list of contributors to the 164*6f625747SDouglas Raillardproject. 165*6f625747SDouglas Raillard 166*6f625747SDouglas RaillardFeedback and support 167*6f625747SDouglas Raillard~~~~~~~~~~~~~~~~~~~~ 168*6f625747SDouglas Raillard 169*6f625747SDouglas RaillardARM welcomes any feedback on the Trusted Firmware. Please send feedback using 170*6f625747SDouglas Raillardthe `GitHub issue tracker`_. 171*6f625747SDouglas Raillard 172*6f625747SDouglas RaillardARM licensees may contact ARM directly via their partner managers. 173*6f625747SDouglas Raillard 174*6f625747SDouglas Raillard-------------- 175*6f625747SDouglas Raillard 176*6f625747SDouglas Raillard*Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.* 177*6f625747SDouglas Raillard 178*6f625747SDouglas Raillard.. _ARMv8-A: http://www.arm.com/products/processors/armv8-architecture.php 179*6f625747SDouglas Raillard.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php 180*6f625747SDouglas Raillard.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 181*6f625747SDouglas Raillard.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html 182*6f625747SDouglas Raillard.. _license: ./license.rst 183*6f625747SDouglas Raillard.. _Contributing Guidelines: ./contributing.rst 184*6f625747SDouglas Raillard.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os 185*6f625747SDouglas Raillard.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary 186*6f625747SDouglas Raillard.. _Firmware Design: ./docs/firmware-design.rst 187*6f625747SDouglas Raillard.. _Change Log: ./docs/change-log.rst 188*6f625747SDouglas Raillard.. _Juno ARM Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php 189*6f625747SDouglas Raillard.. _Linaro Release 16.06: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606 190*6f625747SDouglas Raillard.. _FVP: http://www.arm.com/fvp 191*6f625747SDouglas Raillard.. _www.arm.com/fvp: http://www.arm.com/fvp 192*6f625747SDouglas Raillard.. _GitHub issue tracker: https://github.com/ARM-software/tf-issues/issues 193*6f625747SDouglas Raillard.. _GitHub: https://www.github.com/ARM-software/arm-trusted-firmware 194*6f625747SDouglas Raillard.. _User Guide: ./docs/user-guide.rst 195*6f625747SDouglas Raillard.. _Porting Guide: ./docs/porting-guide.rst 196*6f625747SDouglas Raillard.. _Acknowledgments: ./acknowledgements.rst 197