1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Top-level SMC handler for ZynqMP power management calls and 10 * IPI setup functions for communication with PMU. 11 */ 12 13 #include <errno.h> 14 15 #include <common/runtime_svc.h> 16 #if ZYNQMP_WDT_RESTART 17 #include <arch_helpers.h> 18 #include <drivers/arm/gicv2.h> 19 #include <lib/mmio.h> 20 #include <lib/spinlock.h> 21 #include <plat/common/platform.h> 22 #endif 23 24 #include <plat_private.h> 25 #include "pm_client.h" 26 #include "pm_ipi.h" 27 #include "zynqmp_pm_api_sys.h" 28 #include "zynqmp_pm_defs.h" 29 30 /* pm_up = !0 - UP, pm_up = 0 - DOWN */ 31 static int32_t pm_up, ipi_irq_flag; 32 33 #if ZYNQMP_WDT_RESTART 34 static spinlock_t inc_lock; 35 static int active_cores = 0; 36 #endif 37 38 /** 39 * pm_context - Structure which contains data for power management 40 * @api_version version of PM API, must match with one on PMU side 41 * @payload payload array used to store received 42 * data from ipi buffer registers 43 */ 44 static struct { 45 uint32_t api_version; 46 uint32_t payload[PAYLOAD_ARG_CNT]; 47 } pm_ctx; 48 49 #if ZYNQMP_WDT_RESTART 50 /** 51 * trigger_wdt_restart() - Trigger warm restart event to APU cores 52 * 53 * This function triggers SGI for all active APU CPUs. SGI handler then 54 * power down CPU and call system reset. 55 */ 56 static void trigger_wdt_restart(void) 57 { 58 uint32_t core_count = 0; 59 uint32_t core_status[3]; 60 uint32_t target_cpu_list = 0; 61 int i; 62 63 for (i = 0; i < 4; i++) { 64 pm_get_node_status(NODE_APU_0 + i, core_status); 65 if (core_status[0] == 1) { 66 core_count++; 67 target_cpu_list |= (1 << i); 68 } 69 } 70 71 spin_lock(&inc_lock); 72 active_cores = core_count; 73 spin_unlock(&inc_lock); 74 75 INFO("Active Cores: %d\n", active_cores); 76 77 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { 78 if (target_cpu_list & (1 << i)) { 79 /* trigger SGI to active cores */ 80 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); 81 } 82 } 83 } 84 85 /** 86 * ttc_fiq_handler() - TTC Handler for timer event 87 * @id number of the highest priority pending interrupt of the type 88 * that this handler was registered for 89 * @flags security state, bit[0] 90 * @handler pointer to 'cpu_context' structure of the current CPU for the 91 * security state specified in the 'flags' parameter 92 * @cookie unused 93 * 94 * Function registered as INTR_TYPE_EL3 interrupt handler 95 * 96 * When WDT event is received in PMU, PMU needs to notify master to do cleanup 97 * if required. PMU sets up timer and starts timer to overflow in zero time upon 98 * WDT event. ATF handles this timer event and takes necessary action required 99 * for warm restart. 100 * 101 * In presence of non-secure software layers (EL1/2) sets the interrupt 102 * at registered entrance in GIC and informs that PMU responsed or demands 103 * action. 104 */ 105 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, 106 void *cookie) 107 { 108 INFO("BL31: Got TTC FIQ\n"); 109 110 plat_ic_end_of_interrupt(id); 111 112 /* Clear TTC interrupt by reading interrupt register */ 113 mmio_read_32(TTC3_INTR_REGISTER_1); 114 115 /* Disable the timer interrupts */ 116 mmio_write_32(TTC3_INTR_ENABLE_1, 0); 117 118 trigger_wdt_restart(); 119 120 return 0; 121 } 122 123 /** 124 * zynqmp_sgi7_irq() - Handler for SGI7 IRQ 125 * @id number of the highest priority pending interrupt of the type 126 * that this handler was registered for 127 * @flags security state, bit[0] 128 * @handler pointer to 'cpu_context' structure of the current CPU for the 129 * security state specified in the 'flags' parameter 130 * @cookie unused 131 * 132 * Function registered as INTR_TYPE_EL3 interrupt handler 133 * 134 * On receiving WDT event from PMU, ATF generates SGI7 to all running CPUs. 135 * In response to SGI7 interrupt, each CPUs do clean up if required and last 136 * running CPU calls system restart. 137 */ 138 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 139 void *handle, void *cookie) 140 { 141 int i; 142 uint32_t value; 143 144 /* enter wfi and stay there */ 145 INFO("Entering wfi\n"); 146 147 spin_lock(&inc_lock); 148 active_cores--; 149 150 for (i = 0; i < 4; i++) { 151 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, 152 0xffffffff); 153 } 154 155 dsb(); 156 157 spin_unlock(&inc_lock); 158 159 if (active_cores == 0) { 160 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value); 161 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; 162 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value); 163 } 164 165 /* enter wfi and stay there */ 166 while (1) 167 wfi(); 168 } 169 170 /** 171 * pm_wdt_restart_setup() - Setup warm restart interrupts 172 * 173 * This function sets up handler for SGI7 and TTC interrupts 174 * used for warm restart. 175 */ 176 static int pm_wdt_restart_setup(void) 177 { 178 int ret; 179 180 /* register IRQ handler for SGI7 */ 181 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); 182 if (ret) { 183 WARN("BL31: registering SGI7 interrupt failed\n"); 184 goto err; 185 } 186 187 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); 188 if (ret) 189 WARN("BL31: registering TTC3 interrupt failed\n"); 190 191 err: 192 return ret; 193 } 194 #endif 195 196 /** 197 * pm_setup() - PM service setup 198 * 199 * @return On success, the initialization function must return 0. 200 * Any other return value will cause the framework to ignore 201 * the service 202 * 203 * Initialization functions for ZynqMP power management for 204 * communicaton with PMU. 205 * 206 * Called from sip_svc_setup initialization function with the 207 * rt_svc_init signature. 208 */ 209 int32_t pm_setup(void) 210 { 211 enum pm_ret_status err; 212 213 pm_ipi_init(primary_proc); 214 215 err = pm_get_api_version(&pm_ctx.api_version); 216 if (err != PM_RET_SUCCESS) { 217 ERROR("BL31: Failed to read Platform Management API version. " 218 "Return: %d\n", err); 219 return -EINVAL; 220 } 221 if (pm_ctx.api_version < PM_VERSION) { 222 ERROR("BL31: Platform Management API version error. Expected: " 223 "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, 224 PM_VERSION_MINOR, pm_ctx.api_version >> 16, 225 pm_ctx.api_version & 0xFFFFU); 226 return -EINVAL; 227 } 228 229 int32_t status = 0, ret = 0; 230 #if ZYNQMP_WDT_RESTART 231 status = pm_wdt_restart_setup(); 232 if (status) 233 WARN("BL31: warm-restart setup failed\n"); 234 #endif 235 236 if (status >= 0) { 237 INFO("BL31: PM Service Init Complete: API v%d.%d\n", 238 PM_VERSION_MAJOR, PM_VERSION_MINOR); 239 ret = 0; 240 } else { 241 INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); 242 ret = status; 243 } 244 245 pm_up = !status; 246 247 return ret; 248 } 249 250 /** 251 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. 252 * @smc_fid - Function Identifier 253 * @x1 - x4 - Arguments 254 * @cookie - Unused 255 * @handler - Pointer to caller's context structure 256 * 257 * @return - Unused 258 * 259 * Determines that smc_fid is valid and supported PM SMC Function ID from the 260 * list of pm_api_ids, otherwise completes the request with 261 * the unknown SMC Function ID 262 * 263 * The SMC calls for PM service are forwarded from SIP Service SMC handler 264 * function with rt_svc_handle signature 265 */ 266 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 267 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 268 { 269 enum pm_ret_status ret; 270 uint32_t payload[PAYLOAD_ARG_CNT]; 271 272 uint32_t pm_arg[5]; 273 uint32_t result[PAYLOAD_ARG_CNT] = {0}; 274 uint32_t api_id; 275 276 /* Handle case where PM wasn't initialized properly */ 277 if (pm_up == 0) 278 SMC_RET1(handle, SMC_UNK); 279 280 pm_arg[0] = (uint32_t)x1; 281 pm_arg[1] = (uint32_t)(x1 >> 32); 282 pm_arg[2] = (uint32_t)x2; 283 pm_arg[3] = (uint32_t)(x2 >> 32); 284 pm_arg[4] = (uint32_t)x3; 285 286 api_id = smc_fid & FUNCID_NUM_MASK; 287 288 switch (api_id) { 289 /* PM API Functions */ 290 case PM_SELF_SUSPEND: 291 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 292 pm_arg[3]); 293 SMC_RET1(handle, (uint64_t)ret); 294 295 case PM_REQ_SUSPEND: 296 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 297 pm_arg[3]); 298 SMC_RET1(handle, (uint64_t)ret); 299 300 case PM_REQ_WAKEUP: 301 { 302 /* Use address flag is encoded in the 1st bit of the low-word */ 303 uint32_t set_addr = pm_arg[1] & 0x1U; 304 uint64_t address = (uint64_t)pm_arg[2] << 32U; 305 306 address |= pm_arg[1] & (~0x1U); 307 ret = pm_req_wakeup(pm_arg[0], set_addr, address, 308 pm_arg[3]); 309 SMC_RET1(handle, (uint64_t)ret); 310 } 311 312 case PM_FORCE_POWERDOWN: 313 ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); 314 SMC_RET1(handle, (uint64_t)ret); 315 316 case PM_ABORT_SUSPEND: 317 ret = pm_abort_suspend(pm_arg[0]); 318 SMC_RET1(handle, (uint64_t)ret); 319 320 case PM_SET_WAKEUP_SOURCE: 321 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); 322 SMC_RET1(handle, (uint64_t)ret); 323 324 case PM_SYSTEM_SHUTDOWN: 325 ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); 326 SMC_RET1(handle, (uint64_t)ret); 327 328 case PM_REQ_NODE: 329 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 330 SMC_RET1(handle, (uint64_t)ret); 331 332 case PM_SET_REQUIREMENT: 333 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], 334 pm_arg[3]); 335 SMC_RET1(handle, (uint64_t)ret); 336 337 case PM_GET_API_VERSION: 338 if (ipi_irq_flag == 0U) { 339 /* 340 * Enable IPI IRQ 341 * assume the rich OS is OK to handle callback IRQs now. 342 * Even if we were wrong, it would not enable the IRQ in 343 * the GIC. 344 */ 345 pm_ipi_irq_enable(primary_proc); 346 ipi_irq_flag = 1U; 347 } 348 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 349 ((uint64_t)pm_ctx.api_version << 32)); 350 case PM_FPGA_LOAD: 351 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 352 SMC_RET1(handle, (uint64_t)ret); 353 354 case PM_FPGA_GET_STATUS: 355 { 356 uint32_t value = 0U; 357 358 ret = pm_fpga_get_status(&value); 359 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 360 } 361 362 case PM_SECURE_RSA_AES: 363 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2], 364 pm_arg[3]); 365 SMC_RET1(handle, (uint64_t)ret); 366 367 case PM_GET_CALLBACK_DATA: 368 ret = pm_get_callbackdata(result, ARRAY_SIZE(result)); 369 if (ret != PM_RET_SUCCESS) { 370 result[0] = ret; 371 } 372 373 SMC_RET2(handle, 374 (uint64_t)result[0] | ((uint64_t)result[1] << 32), 375 (uint64_t)result[2] | ((uint64_t)result[3] << 32)); 376 case PM_IOCTL: 377 { 378 uint32_t value = 0U; 379 380 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], 381 pm_arg[3], &value); 382 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 383 } 384 385 case PM_QUERY_DATA: 386 { 387 uint32_t data[4] = { 0 }; 388 389 pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], 390 pm_arg[3], data); 391 SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32), 392 (uint64_t)data[2] | ((uint64_t)data[3] << 32)); 393 } 394 395 case PM_CLOCK_ENABLE: 396 ret = pm_clock_enable(pm_arg[0]); 397 SMC_RET1(handle, (uint64_t)ret); 398 399 case PM_CLOCK_DISABLE: 400 ret = pm_clock_disable(pm_arg[0]); 401 SMC_RET1(handle, (uint64_t)ret); 402 403 case PM_CLOCK_GETSTATE: 404 { 405 uint32_t value = 0U; 406 407 ret = pm_clock_getstate(pm_arg[0], &value); 408 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 409 } 410 411 case PM_CLOCK_SETDIVIDER: 412 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]); 413 SMC_RET1(handle, (uint64_t)ret); 414 415 case PM_CLOCK_GETDIVIDER: 416 { 417 uint32_t value = 0U; 418 419 ret = pm_clock_getdivider(pm_arg[0], &value); 420 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); 421 } 422 423 case PM_CLOCK_SETRATE: 424 ret = pm_clock_setrate(pm_arg[0], 425 ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]); 426 427 SMC_RET1(handle, (uint64_t)ret); 428 429 case PM_CLOCK_GETRATE: 430 { 431 uint64_t value = 0; 432 433 ret = pm_clock_getrate(pm_arg[0], &value); 434 SMC_RET2(handle, (uint64_t)ret | 435 (((uint64_t)value & 0xFFFFFFFFU) << 32U), 436 (value >> 32U) & 0xFFFFFFFFU); 437 438 } 439 440 case PM_CLOCK_SETPARENT: 441 ret = pm_clock_setparent(pm_arg[0], pm_arg[1]); 442 SMC_RET1(handle, (uint64_t)ret); 443 444 case PM_CLOCK_GETPARENT: 445 { 446 uint32_t value = 0U; 447 448 ret = pm_clock_getparent(pm_arg[0], &value); 449 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 450 } 451 452 case PM_GET_TRUSTZONE_VERSION: 453 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 454 ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); 455 456 case PM_SET_SUSPEND_MODE: 457 ret = pm_set_suspend_mode(pm_arg[0]); 458 SMC_RET1(handle, (uint64_t)ret); 459 460 case PM_SECURE_SHA: 461 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2], 462 pm_arg[3]); 463 SMC_RET1(handle, (uint64_t)ret); 464 465 case PM_SECURE_RSA: 466 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2], 467 pm_arg[3]); 468 SMC_RET1(handle, (uint64_t)ret); 469 470 case PM_SECURE_IMAGE: 471 { 472 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], 473 pm_arg[3], &result[0]); 474 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), 475 result[1]); 476 } 477 478 case PM_FPGA_READ: 479 { 480 uint32_t value = 0U; 481 482 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 483 &value); 484 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 485 } 486 487 case PM_SECURE_AES: 488 { 489 uint32_t value = 0U; 490 491 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value); 492 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 493 } 494 495 case PM_PLL_SET_PARAMETER: 496 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]); 497 SMC_RET1(handle, (uint64_t)ret); 498 499 case PM_PLL_GET_PARAMETER: 500 { 501 uint32_t value = 0U; 502 503 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value); 504 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U)); 505 } 506 507 case PM_PLL_SET_MODE: 508 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]); 509 SMC_RET1(handle, (uint64_t)ret); 510 511 case PM_PLL_GET_MODE: 512 { 513 uint32_t mode = 0U; 514 515 ret = pm_pll_get_mode(pm_arg[0], &mode); 516 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U)); 517 } 518 519 case PM_REGISTER_ACCESS: 520 { 521 uint32_t value = 0U; 522 523 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], 524 pm_arg[3], &value); 525 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 526 } 527 528 case PM_EFUSE_ACCESS: 529 { 530 uint32_t value = 0U; 531 532 #if defined(ZYNQMP_SECURE_EFUSES) 533 if (is_caller_non_secure(flags)) { 534 SMC_RET1(handle, 535 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | 536 (uint64_t)PM_RET_ERROR_ACCESS); 537 } 538 #endif 539 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value); 540 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U); 541 } 542 543 case PM_FPGA_GET_VERSION: 544 case PM_FPGA_GET_FEATURE_LIST: 545 { 546 uint32_t ret_payload[PAYLOAD_ARG_CNT]; 547 548 PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, 549 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 550 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); 551 SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U, 552 (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U); 553 } 554 555 case PM_FEATURE_CHECK: 556 { 557 uint32_t version = 0; 558 uint32_t bit_mask[2] = {0}; 559 560 ret = pm_feature_check(pm_arg[0], &version, bit_mask, 561 ARRAY_SIZE(bit_mask)); 562 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U), 563 (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)); 564 } 565 566 default: 567 /* Send request to the PMU */ 568 PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1], 569 pm_arg[2], pm_arg[3], pm_arg[4]); 570 ret = pm_ipi_send_sync(primary_proc, payload, result, 571 PAYLOAD_ARG_CNT); 572 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U), 573 (uint64_t)result[1] | ((uint64_t)result[2] << 32U)); 574 } 575 } 576