1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023-2025, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Top-level SMC handler for ZynqMP power management calls and 10 * IPI setup functions for communication with PMU. 11 */ 12 13 #include <errno.h> 14 15 #include <arch_helpers.h> 16 #include <common/runtime_svc.h> 17 #include <drivers/arm/gicv2.h> 18 #include <lib/mmio.h> 19 #include <lib/spinlock.h> 20 #include <plat/common/platform.h> 21 #include <plat_pm_common.h> 22 23 #include <plat_private.h> 24 #include "pm_client.h" 25 #include "pm_ipi.h" 26 #include "pm_svc_main.h" 27 #include "zynqmp_pm_api_sys.h" 28 #include "zynqmp_pm_defs.h" 29 30 /* pm_up = !0 - UP, pm_up = 0 - DOWN */ 31 static int32_t pm_up, ipi_irq_flag; 32 33 #if ZYNQMP_WDT_RESTART 34 static spinlock_t inc_lock; 35 static int active_cores = 0; 36 #endif 37 38 /** 39 * typedef pm_ctx_t - Structure which contains data for power management. 40 * @api_version: version of PM API, must match with one on PMU side. 41 * @payload: payload array used to store received. 42 * data from ipi buffer registers. 43 * 44 */ 45 typedef struct { 46 uint32_t api_version; 47 uint32_t payload[PAYLOAD_ARG_CNT]; 48 } pm_ctx_t; 49 50 static pm_ctx_t pm_ctx; 51 52 #if ZYNQMP_WDT_RESTART 53 /** 54 * trigger_wdt_restart() - Trigger warm restart event to APU cores. 55 * 56 * This function triggers SGI for all active APU CPUs. SGI handler then 57 * power down CPU and call system reset. 58 * 59 */ 60 static void trigger_wdt_restart(void) 61 { 62 uint32_t core_count = 0; 63 uint32_t core_status[3]; 64 uint32_t target_cpu_list = 0; 65 int i; 66 67 for (i = 0; i < 4; i++) { 68 pm_get_node_status(NODE_APU_0 + i, core_status, SECURE); 69 if (core_status[0] == 1) { 70 core_count++; 71 target_cpu_list |= (1 << i); 72 } 73 } 74 75 spin_lock(&inc_lock); 76 active_cores = core_count; 77 spin_unlock(&inc_lock); 78 79 INFO("Active Cores: %d\n", active_cores); 80 81 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { 82 if (target_cpu_list & (1 << i)) { 83 /* trigger SGI to active cores */ 84 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); 85 } 86 } 87 } 88 89 /** 90 * ttc_fiq_handler() - TTC Handler for timer event. 91 * @id: number of the highest priority pending interrupt of the type 92 * that this handler was registered for. 93 * @flags: security state, bit[0]. 94 * @handle: pointer to 'cpu_context' structure of the current CPU for the 95 * security state specified in the 'flags' parameter. 96 * @cookie: unused. 97 * 98 * Function registered as INTR_TYPE_EL3 interrupt handler. 99 * 100 * When WDT event is received in PMU, PMU needs to notify master to do cleanup 101 * if required. PMU sets up timer and starts timer to overflow in zero time upon 102 * WDT event. TF-A handles this timer event and takes necessary action required 103 * for warm restart. 104 * 105 * In presence of non-secure software layers (EL1/2) sets the interrupt 106 * at registered entrance in GIC and informs that PMU responded or demands 107 * action. 108 * 109 * Return: 0 on success. 110 * 111 */ 112 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, 113 void *cookie) 114 { 115 INFO("BL31: Got TTC FIQ\n"); 116 117 plat_ic_end_of_interrupt(id); 118 119 /* Clear TTC interrupt by reading interrupt register */ 120 mmio_read_32(TTC3_INTR_REGISTER_1); 121 122 /* Disable the timer interrupts */ 123 mmio_write_32(TTC3_INTR_ENABLE_1, 0); 124 125 trigger_wdt_restart(); 126 127 return 0; 128 } 129 130 /** 131 * zynqmp_sgi7_irq() - Handler for SGI7 IRQ. 132 * @id: number of the highest priority pending interrupt of the type 133 * that this handler was registered for. 134 * @flags: security state, bit[0]. 135 * @handle: pointer to 'cpu_context' structure of the current CPU for the 136 * security state specified in the 'flags' parameter. 137 * @cookie: unused. 138 * 139 * Function registered as INTR_TYPE_EL3 interrupt handler 140 * 141 * On receiving WDT event from PMU, TF-A generates SGI7 to all running CPUs. 142 * In response to SGI7 interrupt, each CPUs do clean up if required and last 143 * running CPU calls system restart. 144 * 145 * Return: This function does not return a value and it enters into wfi. 146 */ 147 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 148 void *handle, void *cookie) 149 { 150 int i; 151 uint32_t value; 152 153 /* enter wfi and stay there */ 154 INFO("Entering wfi\n"); 155 156 spin_lock(&inc_lock); 157 active_cores--; 158 159 for (i = 0; i < 4; i++) { 160 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, 161 0xffffffff); 162 } 163 164 dsb(); 165 166 spin_unlock(&inc_lock); 167 168 if (active_cores == 0) { 169 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value, SECURE); 170 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; 171 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value, SECURE); 172 } 173 174 /* enter wfi and stay there */ 175 while (1) 176 wfi(); 177 } 178 179 /** 180 * pm_wdt_restart_setup() - Setup warm restart interrupts. 181 * 182 * Return: Returns status, 0 on success or error+reason. 183 * 184 * This function sets up handler for SGI7 and TTC interrupts 185 * used for warm restart. 186 */ 187 static int pm_wdt_restart_setup(void) 188 { 189 int ret; 190 191 /* register IRQ handler for SGI7 */ 192 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); 193 if (ret) { 194 WARN("BL31: registering SGI7 interrupt failed\n"); 195 goto err; 196 } 197 198 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); 199 if (ret) 200 WARN("BL31: registering TTC3 interrupt failed\n"); 201 202 err: 203 return ret; 204 } 205 #endif 206 207 /** 208 * pm_setup() - PM service setup. 209 * 210 * Return: On success, the initialization function must return 0. 211 * Any other return value will cause the framework to ignore 212 * the service. 213 * 214 * Initialization functions for ZynqMP power management for 215 * communicaton with PMU. 216 * 217 * Called from sip_svc_setup initialization function with the 218 * rt_svc_init signature. 219 * 220 */ 221 int32_t pm_setup(void) 222 { 223 enum pm_ret_status err; 224 int32_t ret = -EINVAL; 225 226 pm_ipi_init(primary_proc); 227 228 err = pm_get_api_version(&pm_ctx.api_version, SECURE); 229 if (err != PM_RET_SUCCESS) { 230 ERROR("BL31: Failed to read Platform Management API version. " 231 "Return: %d\n", err); 232 goto exit_label; 233 } 234 if (pm_ctx.api_version < PM_VERSION) { 235 ERROR("BL31: Platform Management API version error. Expected: " 236 "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, 237 PM_VERSION_MINOR, pm_ctx.api_version >> 16, 238 pm_ctx.api_version & 0xFFFFU); 239 goto exit_label; 240 } 241 242 int32_t status = 0; 243 #if ZYNQMP_WDT_RESTART 244 status = pm_wdt_restart_setup(); 245 if (status) 246 WARN("BL31: warm-restart setup failed\n"); 247 #endif 248 249 if (status >= 0) { 250 INFO("BL31: PM Service Init Complete: API v%d.%d\n", 251 PM_VERSION_MAJOR, PM_VERSION_MINOR); 252 ret = 0; 253 } else { 254 INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); 255 ret = status; 256 } 257 258 pm_up = (status == 0); 259 260 exit_label: 261 return ret; 262 } 263 264 /** 265 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. 266 * @smc_fid: Function Identifier. 267 * @x1: Arguments. 268 * @x2: Arguments. 269 * @x3: Arguments. 270 * @x4: Arguments. 271 * @cookie: Unused. 272 * @handle: Pointer to caller's context structure. 273 * @flags: SECURE or NON_SECURE 274 * 275 * Determines that smc_fid is valid and supported PM SMC Function ID from the 276 * list of pm_api_ids, otherwise completes the request with 277 * the unknown SMC Function ID. 278 * 279 * The SMC calls for PM service are forwarded from SIP Service SMC handler 280 * function with rt_svc_handle signature. 281 * 282 * Return: Unused. 283 * 284 */ 285 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 286 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 287 { 288 (void)x4; 289 (void)cookie; 290 enum pm_ret_status ret; 291 uint32_t payload[PAYLOAD_ARG_CNT]; 292 293 uint32_t pm_arg[5]; 294 uint32_t result[RET_PAYLOAD_ARG_CNT] = {0}; 295 uint32_t api_id; 296 uint32_t security_flag = NON_SECURE; 297 bool status = false, status_tmp = false; 298 299 /* Handle case where PM wasn't initialized properly */ 300 if (pm_up == 0) 301 SMC_RET1(handle, SMC_UNK); 302 303 /* 304 * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as secure (0) 305 * if smc called is secure 306 * 307 * Add redundant macro call to immune the code from glitches 308 */ 309 SECURE_REDUNDANT_CALL(status, status_tmp, is_caller_secure, flags); 310 if ((status != false) && (status_tmp != false)) { 311 security_flag = SECURE; 312 } 313 314 pm_arg[0] = (uint32_t)x1; 315 pm_arg[1] = (uint32_t)(x1 >> 32); 316 pm_arg[2] = (uint32_t)x2; 317 pm_arg[3] = (uint32_t)(x2 >> 32); 318 pm_arg[4] = (uint32_t)x3; 319 320 api_id = smc_fid & FUNCID_NUM_MASK; 321 322 switch (api_id) { 323 /* PM API Functions */ 324 case PM_SELF_SUSPEND: 325 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 326 pm_arg[3], security_flag); 327 SMC_RET1(handle, (uint64_t)ret); 328 329 case PM_REQ_SUSPEND: 330 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 331 pm_arg[3], security_flag); 332 SMC_RET1(handle, (uint64_t)ret); 333 334 case PM_REQ_WAKEUP: 335 { 336 /* Use address flag is encoded in the 1st bit of the low-word */ 337 uint32_t set_addr = pm_arg[1] & 0x1U; 338 uint64_t address = (uint64_t)pm_arg[2] << 32U; 339 340 address |= (uint64_t)(pm_arg[1] & (~0x1U)); 341 ret = pm_req_wakeup(pm_arg[0], set_addr, address, 342 pm_arg[3], security_flag); 343 SMC_RET1(handle, (uint64_t)ret); 344 } 345 346 case PM_FORCE_POWERDOWN: 347 ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag); 348 SMC_RET1(handle, (uint64_t)ret); 349 350 case PM_SET_WAKEUP_SOURCE: 351 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2], security_flag); 352 SMC_RET1(handle, (uint64_t)ret); 353 354 case PM_SYSTEM_SHUTDOWN: 355 ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag); 356 SMC_RET1(handle, (uint64_t)ret); 357 358 case PM_REQ_NODE: 359 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], security_flag); 360 SMC_RET1(handle, (uint64_t)ret); 361 362 case PM_SET_REQUIREMENT: 363 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], 364 pm_arg[3], security_flag); 365 SMC_RET1(handle, (uint64_t)ret); 366 367 case PM_GET_API_VERSION: 368 if ((uint32_t)ipi_irq_flag == 0U) { 369 /* 370 * Enable IPI IRQ 371 * assume the rich OS is OK to handle callback IRQs now. 372 * Even if we were wrong, it would not enable the IRQ in 373 * the GIC. 374 */ 375 pm_ipi_irq_enable(primary_proc); 376 ipi_irq_flag = 1U; 377 } 378 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 379 ((uint64_t)pm_ctx.api_version << 32)); 380 case PM_FPGA_LOAD: 381 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], security_flag); 382 SMC_RET1(handle, (uint64_t)ret); 383 384 case PM_FPGA_GET_STATUS: 385 { 386 uint32_t value = 0U; 387 388 ret = pm_fpga_get_status(&value, security_flag); 389 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 390 } 391 392 case PM_SECURE_RSA_AES: 393 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2], 394 pm_arg[3], security_flag); 395 SMC_RET1(handle, (uint64_t)ret); 396 397 case PM_GET_CALLBACK_DATA: 398 ret = pm_get_callbackdata(result, ARRAY_SIZE(result)); 399 if (ret != PM_RET_SUCCESS) { 400 result[0] = ret; 401 } 402 403 SMC_RET2(handle, 404 ((uint64_t)result[0] | ((uint64_t)result[1] << 32)), 405 ((uint64_t)result[2] | ((uint64_t)result[3] << 32))); 406 case PM_IOCTL: 407 { 408 uint32_t value = 0U; 409 410 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], 411 pm_arg[3], &value, security_flag); 412 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 413 } 414 415 case PM_QUERY_DATA: 416 { 417 uint32_t data[4] = { 0 }; 418 419 pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], 420 pm_arg[3], data, security_flag); 421 SMC_RET2(handle, ((uint64_t)data[0] | ((uint64_t)data[1] << 32)), 422 ((uint64_t)data[2] | ((uint64_t)data[3] << 32))); 423 } 424 425 case PM_CLOCK_ENABLE: 426 ret = pm_clock_enable(pm_arg[0], security_flag); 427 SMC_RET1(handle, (uint64_t)ret); 428 429 case PM_CLOCK_DISABLE: 430 ret = pm_clock_disable(pm_arg[0], security_flag); 431 SMC_RET1(handle, (uint64_t)ret); 432 433 case PM_CLOCK_GETSTATE: 434 { 435 uint32_t value = 0U; 436 437 ret = pm_clock_getstate(pm_arg[0], &value, security_flag); 438 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 439 } 440 441 case PM_CLOCK_SETDIVIDER: 442 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1], security_flag); 443 SMC_RET1(handle, (uint64_t)ret); 444 445 case PM_CLOCK_GETDIVIDER: 446 { 447 uint32_t value = 0U; 448 449 ret = pm_clock_getdivider(pm_arg[0], &value, security_flag); 450 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 451 } 452 453 case PM_CLOCK_SETPARENT: 454 ret = pm_clock_setparent(pm_arg[0], pm_arg[1], security_flag); 455 SMC_RET1(handle, (uint64_t)ret); 456 457 case PM_CLOCK_GETPARENT: 458 { 459 uint32_t value = 0U; 460 461 ret = pm_clock_getparent(pm_arg[0], &value, security_flag); 462 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 463 } 464 465 case PM_GET_TRUSTZONE_VERSION: 466 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 467 ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); 468 469 case PM_SET_SUSPEND_MODE: 470 ret = pm_set_suspend_mode(pm_arg[0]); 471 SMC_RET1(handle, (uint64_t)ret); 472 473 case PM_SECURE_SHA: 474 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2], 475 pm_arg[3], security_flag); 476 SMC_RET1(handle, (uint64_t)ret); 477 478 case PM_SECURE_RSA: 479 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2], 480 pm_arg[3], security_flag); 481 SMC_RET1(handle, (uint64_t)ret); 482 483 case PM_SECURE_IMAGE: 484 { 485 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], 486 pm_arg[3], &result[0], security_flag); 487 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)), 488 result[1]); 489 } 490 491 case PM_FPGA_READ: 492 { 493 uint32_t value = 0U; 494 495 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 496 &value, security_flag); 497 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 498 } 499 500 case PM_SECURE_AES: 501 { 502 uint32_t value = 0U; 503 504 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value, security_flag); 505 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 506 } 507 508 case PM_PLL_SET_PARAMETER: 509 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2], 510 security_flag); 511 SMC_RET1(handle, (uint64_t)ret); 512 513 case PM_PLL_GET_PARAMETER: 514 { 515 uint32_t value = 0U; 516 517 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value, 518 security_flag); 519 SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)value << 32U))); 520 } 521 522 case PM_PLL_SET_MODE: 523 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1], security_flag); 524 SMC_RET1(handle, (uint64_t)ret); 525 526 case PM_PLL_GET_MODE: 527 { 528 uint32_t mode = 0U; 529 530 ret = pm_pll_get_mode(pm_arg[0], &mode, security_flag); 531 SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)mode << 32U))); 532 } 533 534 case PM_REGISTER_ACCESS: 535 { 536 uint32_t value = 0U; 537 538 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], 539 pm_arg[3], &value, security_flag); 540 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 541 } 542 543 case PM_EFUSE_ACCESS: 544 { 545 uint32_t value = 0U; 546 547 #if defined(ZYNQMP_SECURE_EFUSES) 548 if (is_caller_non_secure(flags)) { 549 SMC_RET1(handle, 550 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | 551 (uint64_t)PM_RET_ERROR_ACCESS); 552 } 553 #endif 554 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value, security_flag); 555 SMC_RET1(handle, (uint64_t)ret | (((uint64_t)value) << 32U)); 556 } 557 558 case PM_FPGA_GET_VERSION: 559 case PM_FPGA_GET_FEATURE_LIST: 560 { 561 uint32_t ret_payload[PAYLOAD_ARG_CNT]; 562 563 PM_PACK_PAYLOAD5(payload, security_flag, smc_fid & FUNCID_NUM_MASK, 564 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 565 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); 566 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)ret_payload[0] << 32U)), 567 ((uint64_t)ret_payload[1] | ((uint64_t)ret_payload[2] << 32U))); 568 } 569 570 case PM_FEATURE_CHECK: 571 { 572 uint32_t version_type = 0; 573 uint32_t bit_mask[2] = {0}; 574 575 ret = pm_feature_check(pm_arg[0], &version_type, bit_mask, 576 (uint8_t)ARRAY_SIZE(bit_mask), 577 security_flag); 578 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)), 579 ((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U))); 580 } 581 582 default: 583 /* Send request to the PMU */ 584 PM_PACK_PAYLOAD6(payload, security_flag, api_id, pm_arg[0], 585 pm_arg[1], pm_arg[2], pm_arg[3], pm_arg[4]); 586 ret = pm_ipi_send_sync(primary_proc, payload, result, 587 RET_PAYLOAD_ARG_CNT); 588 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)), 589 ((uint64_t)result[1] | ((uint64_t)result[2] << 32U))); 590 } 591 } 592