1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * ZynqMP system level PM-API functions for pin control. 10 */ 11 12 #include <string.h> 13 14 #include <arch_helpers.h> 15 #include <plat/common/platform.h> 16 17 #include "pm_api_pinctrl.h" 18 #include "pm_client.h" 19 #include "pm_common.h" 20 #include "pm_ipi.h" 21 #include "zynqmp_pm_api_sys.h" 22 23 struct pinctrl_function { 24 char name[FUNCTION_NAME_LEN]; 25 uint16_t group_base; 26 uint8_t group_size; 27 uint8_t regval; 28 }; 29 30 /* Max groups for one pin */ 31 #define MAX_PIN_GROUPS (13U) 32 33 struct zynqmp_pin_group { 34 uint16_t (*groups)[]; 35 }; 36 37 static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { 38 [PINCTRL_FUNC_CAN0] = { 39 .name = "can0", 40 .regval = 0x20, 41 .group_base = PINCTRL_GRP_CAN0_0, 42 .group_size = PINCTRL_GRP_CAN0_18 - PINCTRL_GRP_CAN0_0 + 1U, 43 }, 44 [PINCTRL_FUNC_CAN1] = { 45 .name = "can1", 46 .regval = 0x20, 47 .group_base = PINCTRL_GRP_CAN1_0, 48 .group_size = PINCTRL_GRP_CAN1_19 - PINCTRL_GRP_CAN1_0 + 1U, 49 }, 50 [PINCTRL_FUNC_ETHERNET0] = { 51 .name = "ethernet0", 52 .regval = 0x02, 53 .group_base = PINCTRL_GRP_ETHERNET0_0, 54 .group_size = PINCTRL_GRP_ETHERNET0_0 - PINCTRL_GRP_ETHERNET0_0 + 1U, 55 }, 56 [PINCTRL_FUNC_ETHERNET1] = { 57 .name = "ethernet1", 58 .regval = 0x02, 59 .group_base = PINCTRL_GRP_ETHERNET1_0, 60 .group_size = PINCTRL_GRP_ETHERNET1_0 - PINCTRL_GRP_ETHERNET1_0 + 1U, 61 }, 62 [PINCTRL_FUNC_ETHERNET2] = { 63 .name = "ethernet2", 64 .regval = 0x02, 65 .group_base = PINCTRL_GRP_ETHERNET2_0, 66 .group_size = PINCTRL_GRP_ETHERNET2_0 - PINCTRL_GRP_ETHERNET2_0 + 1U, 67 }, 68 [PINCTRL_FUNC_ETHERNET3] = { 69 .name = "ethernet3", 70 .regval = 0x02, 71 .group_base = PINCTRL_GRP_ETHERNET3_0, 72 .group_size = PINCTRL_GRP_ETHERNET3_0 - PINCTRL_GRP_ETHERNET3_0 + 1U, 73 }, 74 [PINCTRL_FUNC_GEMTSU0] = { 75 .name = "gemtsu0", 76 .regval = 0x02, 77 .group_base = PINCTRL_GRP_GEMTSU0_0, 78 .group_size = PINCTRL_GRP_GEMTSU0_2 - PINCTRL_GRP_GEMTSU0_0 + 1U, 79 }, 80 [PINCTRL_FUNC_GPIO0] = { 81 .name = "gpio0", 82 .regval = 0x00, 83 .group_base = PINCTRL_GRP_GPIO0_0, 84 .group_size = PINCTRL_GRP_GPIO0_77 - PINCTRL_GRP_GPIO0_0 + 1U, 85 }, 86 [PINCTRL_FUNC_I2C0] = { 87 .name = "i2c0", 88 .regval = 0x40, 89 .group_base = PINCTRL_GRP_I2C0_0, 90 .group_size = PINCTRL_GRP_I2C0_18 - PINCTRL_GRP_I2C0_0 + 1U, 91 }, 92 [PINCTRL_FUNC_I2C1] = { 93 .name = "i2c1", 94 .regval = 0x40, 95 .group_base = PINCTRL_GRP_I2C1_0, 96 .group_size = PINCTRL_GRP_I2C1_19 - PINCTRL_GRP_I2C1_0 + 1U, 97 }, 98 [PINCTRL_FUNC_MDIO0] = { 99 .name = "mdio0", 100 .regval = 0x60, 101 .group_base = PINCTRL_GRP_MDIO0_0, 102 .group_size = PINCTRL_GRP_MDIO0_0 - PINCTRL_GRP_MDIO0_0 + 1U, 103 }, 104 [PINCTRL_FUNC_MDIO1] = { 105 .name = "mdio1", 106 .regval = 0x80, 107 .group_base = PINCTRL_GRP_MDIO1_0, 108 .group_size = PINCTRL_GRP_MDIO1_1 - PINCTRL_GRP_MDIO1_0 + 1U, 109 }, 110 [PINCTRL_FUNC_MDIO2] = { 111 .name = "mdio2", 112 .regval = 0xa0, 113 .group_base = PINCTRL_GRP_MDIO2_0, 114 .group_size = PINCTRL_GRP_MDIO2_0 - PINCTRL_GRP_MDIO2_0 + 1U, 115 }, 116 [PINCTRL_FUNC_MDIO3] = { 117 .name = "mdio3", 118 .regval = 0xc0, 119 .group_base = PINCTRL_GRP_MDIO3_0, 120 .group_size = PINCTRL_GRP_MDIO3_0 - PINCTRL_GRP_MDIO3_0 + 1U, 121 }, 122 [PINCTRL_FUNC_QSPI0] = { 123 .name = "qspi0", 124 .regval = 0x02, 125 .group_base = PINCTRL_GRP_QSPI0_0, 126 .group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U, 127 }, 128 [PINCTRL_FUNC_QSPI_FBCLK] = { 129 .name = "qspi_fbclk", 130 .regval = 0x02, 131 .group_base = PINCTRL_GRP_QSPI_FBCLK, 132 .group_size = PINCTRL_GRP_QSPI_FBCLK - PINCTRL_GRP_QSPI_FBCLK + 1U, 133 }, 134 [PINCTRL_FUNC_QSPI_SS] = { 135 .name = "qspi_ss", 136 .regval = 0x02, 137 .group_base = PINCTRL_GRP_QSPI_SS, 138 .group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U, 139 }, 140 [PINCTRL_FUNC_SPI0] = { 141 .name = "spi0", 142 .regval = 0x80, 143 .group_base = PINCTRL_GRP_SPI0_0, 144 .group_size = PINCTRL_GRP_SPI0_5 - PINCTRL_GRP_SPI0_0 + 1U, 145 }, 146 [PINCTRL_FUNC_SPI1] = { 147 .name = "spi1", 148 .regval = 0x80, 149 .group_base = PINCTRL_GRP_SPI1_0, 150 .group_size = PINCTRL_GRP_SPI1_5 - PINCTRL_GRP_SPI1_0 + 1U, 151 }, 152 [PINCTRL_FUNC_SPI0_SS] = { 153 .name = "spi0_ss", 154 .regval = 0x80, 155 .group_base = PINCTRL_GRP_SPI0_0_SS0, 156 .group_size = PINCTRL_GRP_SPI0_5_SS2 - PINCTRL_GRP_SPI0_0_SS0 + 1U, 157 }, 158 [PINCTRL_FUNC_SPI1_SS] = { 159 .name = "spi1_ss", 160 .regval = 0x80, 161 .group_base = PINCTRL_GRP_SPI1_0_SS0, 162 .group_size = PINCTRL_GRP_SPI1_5_SS2 - PINCTRL_GRP_SPI1_0_SS0 + 1U, 163 }, 164 [PINCTRL_FUNC_SDIO0] = { 165 .name = "sdio0", 166 .regval = 0x08, 167 .group_base = PINCTRL_GRP_SDIO0_0, 168 .group_size = PINCTRL_GRP_SDIO0_1BIT_2_7 - PINCTRL_GRP_SDIO0_0 + 1U, 169 }, 170 [PINCTRL_FUNC_SDIO0_PC] = { 171 .name = "sdio0_pc", 172 .regval = 0x08, 173 .group_base = PINCTRL_GRP_SDIO0_0_PC, 174 .group_size = PINCTRL_GRP_SDIO0_2_PC - PINCTRL_GRP_SDIO0_0_PC + 1U, 175 }, 176 [PINCTRL_FUNC_SDIO0_CD] = { 177 .name = "sdio0_cd", 178 .regval = 0x08, 179 .group_base = PINCTRL_GRP_SDIO0_0_CD, 180 .group_size = PINCTRL_GRP_SDIO0_2_CD - PINCTRL_GRP_SDIO0_0_CD + 1U, 181 }, 182 [PINCTRL_FUNC_SDIO0_WP] = { 183 .name = "sdio0_wp", 184 .regval = 0x08, 185 .group_base = PINCTRL_GRP_SDIO0_0_WP, 186 .group_size = PINCTRL_GRP_SDIO0_2_WP - PINCTRL_GRP_SDIO0_0_WP + 1U, 187 }, 188 [PINCTRL_FUNC_SDIO1] = { 189 .name = "sdio1", 190 .regval = 0x10, 191 .group_base = PINCTRL_GRP_SDIO1_0, 192 .group_size = PINCTRL_GRP_SDIO1_1BIT_1_3 - PINCTRL_GRP_SDIO1_0 + 1U, 193 }, 194 [PINCTRL_FUNC_SDIO1_PC] = { 195 .name = "sdio1_pc", 196 .regval = 0x10, 197 .group_base = PINCTRL_GRP_SDIO1_0_PC, 198 .group_size = PINCTRL_GRP_SDIO1_1_PC - PINCTRL_GRP_SDIO1_0_PC + 1U, 199 }, 200 [PINCTRL_FUNC_SDIO1_CD] = { 201 .name = "sdio1_cd", 202 .regval = 0x10, 203 .group_base = PINCTRL_GRP_SDIO1_0_CD, 204 .group_size = PINCTRL_GRP_SDIO1_1_CD - PINCTRL_GRP_SDIO1_0_CD + 1U, 205 }, 206 [PINCTRL_FUNC_SDIO1_WP] = { 207 .name = "sdio1_wp", 208 .regval = 0x10, 209 .group_base = PINCTRL_GRP_SDIO1_0_WP, 210 .group_size = PINCTRL_GRP_SDIO1_1_WP - PINCTRL_GRP_SDIO1_0_WP + 1U, 211 }, 212 [PINCTRL_FUNC_NAND0] = { 213 .name = "nand0", 214 .regval = 0x04, 215 .group_base = PINCTRL_GRP_NAND0_0, 216 .group_size = PINCTRL_GRP_NAND0_0 - PINCTRL_GRP_NAND0_0 + 1U, 217 }, 218 [PINCTRL_FUNC_NAND0_CE] = { 219 .name = "nand0_ce", 220 .regval = 0x04, 221 .group_base = PINCTRL_GRP_NAND0_0_CE, 222 .group_size = PINCTRL_GRP_NAND0_1_CE - PINCTRL_GRP_NAND0_0_CE + 1U, 223 }, 224 [PINCTRL_FUNC_NAND0_RB] = { 225 .name = "nand0_rb", 226 .regval = 0x04, 227 .group_base = PINCTRL_GRP_NAND0_0_RB, 228 .group_size = PINCTRL_GRP_NAND0_1_RB - PINCTRL_GRP_NAND0_0_RB + 1U, 229 }, 230 [PINCTRL_FUNC_NAND0_DQS] = { 231 .name = "nand0_dqs", 232 .regval = 0x04, 233 .group_base = PINCTRL_GRP_NAND0_0_DQS, 234 .group_size = PINCTRL_GRP_NAND0_1_DQS - PINCTRL_GRP_NAND0_0_DQS + 1U, 235 }, 236 [PINCTRL_FUNC_TTC0_CLK] = { 237 .name = "ttc0_clk", 238 .regval = 0xa0, 239 .group_base = PINCTRL_GRP_TTC0_0_CLK, 240 .group_size = PINCTRL_GRP_TTC0_8_CLK - PINCTRL_GRP_TTC0_0_CLK + 1U, 241 }, 242 [PINCTRL_FUNC_TTC0_WAV] = { 243 .name = "ttc0_wav", 244 .regval = 0xa0, 245 .group_base = PINCTRL_GRP_TTC0_0_WAV, 246 .group_size = PINCTRL_GRP_TTC0_8_WAV - PINCTRL_GRP_TTC0_0_WAV + 1U, 247 }, 248 [PINCTRL_FUNC_TTC1_CLK] = { 249 .name = "ttc1_clk", 250 .regval = 0xa0, 251 .group_base = PINCTRL_GRP_TTC1_0_CLK, 252 .group_size = PINCTRL_GRP_TTC1_8_CLK - PINCTRL_GRP_TTC1_0_CLK + 1U, 253 }, 254 [PINCTRL_FUNC_TTC1_WAV] = { 255 .name = "ttc1_wav", 256 .regval = 0xa0, 257 .group_base = PINCTRL_GRP_TTC1_0_WAV, 258 .group_size = PINCTRL_GRP_TTC1_8_WAV - PINCTRL_GRP_TTC1_0_WAV + 1U, 259 }, 260 [PINCTRL_FUNC_TTC2_CLK] = { 261 .name = "ttc2_clk", 262 .regval = 0xa0, 263 .group_base = PINCTRL_GRP_TTC2_0_CLK, 264 .group_size = PINCTRL_GRP_TTC2_8_CLK - PINCTRL_GRP_TTC2_0_CLK + 1U, 265 }, 266 [PINCTRL_FUNC_TTC2_WAV] = { 267 .name = "ttc2_wav", 268 .regval = 0xa0, 269 .group_base = PINCTRL_GRP_TTC2_0_WAV, 270 .group_size = PINCTRL_GRP_TTC2_8_WAV - PINCTRL_GRP_TTC2_0_WAV + 1U, 271 }, 272 [PINCTRL_FUNC_TTC3_CLK] = { 273 .name = "ttc3_clk", 274 .regval = 0xa0, 275 .group_base = PINCTRL_GRP_TTC3_0_CLK, 276 .group_size = PINCTRL_GRP_TTC3_8_CLK - PINCTRL_GRP_TTC3_0_CLK + 1U, 277 }, 278 [PINCTRL_FUNC_TTC3_WAV] = { 279 .name = "ttc3_wav", 280 .regval = 0xa0, 281 .group_base = PINCTRL_GRP_TTC3_0_WAV, 282 .group_size = PINCTRL_GRP_TTC3_8_WAV - PINCTRL_GRP_TTC3_0_WAV + 1U, 283 }, 284 [PINCTRL_FUNC_UART0] = { 285 .name = "uart0", 286 .regval = 0xc0, 287 .group_base = PINCTRL_GRP_UART0_0, 288 .group_size = PINCTRL_GRP_UART0_18 - PINCTRL_GRP_UART0_0 + 1U, 289 }, 290 [PINCTRL_FUNC_UART1] = { 291 .name = "uart1", 292 .regval = 0xc0, 293 .group_base = PINCTRL_GRP_UART1_0, 294 .group_size = PINCTRL_GRP_UART1_18 - PINCTRL_GRP_UART1_0 + 1U, 295 }, 296 [PINCTRL_FUNC_USB0] = { 297 .name = "usb0", 298 .regval = 0x04, 299 .group_base = PINCTRL_GRP_USB0_0, 300 .group_size = PINCTRL_GRP_USB0_0 - PINCTRL_GRP_USB0_0 + 1U, 301 }, 302 [PINCTRL_FUNC_USB1] = { 303 .name = "usb1", 304 .regval = 0x04, 305 .group_base = PINCTRL_GRP_USB1_0, 306 .group_size = PINCTRL_GRP_USB1_0 - PINCTRL_GRP_USB1_0 + 1U, 307 }, 308 [PINCTRL_FUNC_SWDT0_CLK] = { 309 .name = "swdt0_clk", 310 .regval = 0x60, 311 .group_base = PINCTRL_GRP_SWDT0_0_CLK, 312 .group_size = PINCTRL_GRP_SWDT0_12_CLK - PINCTRL_GRP_SWDT0_0_CLK + 1U, 313 }, 314 [PINCTRL_FUNC_SWDT0_RST] = { 315 .name = "swdt0_rst", 316 .regval = 0x60, 317 .group_base = PINCTRL_GRP_SWDT0_0_RST, 318 .group_size = PINCTRL_GRP_SWDT0_12_RST - PINCTRL_GRP_SWDT0_0_RST + 1U, 319 }, 320 [PINCTRL_FUNC_SWDT1_CLK] = { 321 .name = "swdt1_clk", 322 .regval = 0x60, 323 .group_base = PINCTRL_GRP_SWDT1_0_CLK, 324 .group_size = PINCTRL_GRP_SWDT1_12_CLK - PINCTRL_GRP_SWDT1_0_CLK + 1U, 325 }, 326 [PINCTRL_FUNC_SWDT1_RST] = { 327 .name = "swdt1_rst", 328 .regval = 0x60, 329 .group_base = PINCTRL_GRP_SWDT1_0_RST, 330 .group_size = PINCTRL_GRP_SWDT1_12_RST - PINCTRL_GRP_SWDT1_0_RST + 1U, 331 }, 332 [PINCTRL_FUNC_PMU0] = { 333 .name = "pmu0", 334 .regval = 0x08, 335 .group_base = PINCTRL_GRP_PMU0_0, 336 .group_size = PINCTRL_GRP_PMU0_11 - PINCTRL_GRP_PMU0_0 + 1U, 337 }, 338 [PINCTRL_FUNC_PCIE0] = { 339 .name = "pcie0", 340 .regval = 0x04, 341 .group_base = PINCTRL_GRP_PCIE0_0, 342 .group_size = PINCTRL_GRP_PCIE0_7 - PINCTRL_GRP_PCIE0_0 + 1U, 343 }, 344 [PINCTRL_FUNC_CSU0] = { 345 .name = "csu0", 346 .regval = 0x18, 347 .group_base = PINCTRL_GRP_CSU0_0, 348 .group_size = PINCTRL_GRP_CSU0_11 - PINCTRL_GRP_CSU0_0 + 1U, 349 }, 350 [PINCTRL_FUNC_DPAUX0] = { 351 .name = "dpaux0", 352 .regval = 0x18, 353 .group_base = PINCTRL_GRP_DPAUX0_0, 354 .group_size = PINCTRL_GRP_DPAUX0_3 - PINCTRL_GRP_DPAUX0_0 + 1U, 355 }, 356 [PINCTRL_FUNC_PJTAG0] = { 357 .name = "pjtag0", 358 .regval = 0x60, 359 .group_base = PINCTRL_GRP_PJTAG0_0, 360 .group_size = PINCTRL_GRP_PJTAG0_5 - PINCTRL_GRP_PJTAG0_0 + 1U, 361 }, 362 [PINCTRL_FUNC_TRACE0] = { 363 .name = "trace0", 364 .regval = 0xe0, 365 .group_base = PINCTRL_GRP_TRACE0_0, 366 .group_size = PINCTRL_GRP_TRACE0_2 - PINCTRL_GRP_TRACE0_0 + 1U, 367 }, 368 [PINCTRL_FUNC_TRACE0_CLK] = { 369 .name = "trace0_clk", 370 .regval = 0xe0, 371 .group_base = PINCTRL_GRP_TRACE0_0_CLK, 372 .group_size = PINCTRL_GRP_TRACE0_2_CLK - PINCTRL_GRP_TRACE0_0_CLK + 1U, 373 }, 374 [PINCTRL_FUNC_TESTSCAN0] = { 375 .name = "testscan0", 376 .regval = 0x10, 377 .group_base = PINCTRL_GRP_TESTSCAN0_0, 378 .group_size = PINCTRL_GRP_TESTSCAN0_0 - PINCTRL_GRP_TESTSCAN0_0 + 1U, 379 }, 380 }; 381 382 static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { 383 [PINCTRL_PIN_0] = { 384 .groups = &((uint16_t []) { 385 PINCTRL_GRP_QSPI0_0, 386 PINCTRL_GRP_RESERVED, 387 PINCTRL_GRP_RESERVED, 388 PINCTRL_GRP_TESTSCAN0_0, 389 PINCTRL_GRP_RESERVED, 390 PINCTRL_GRP_GPIO0_0, 391 PINCTRL_GRP_CAN1_0, 392 PINCTRL_GRP_I2C1_0, 393 PINCTRL_GRP_PJTAG0_0, 394 PINCTRL_GRP_SPI0_0, 395 PINCTRL_GRP_TTC3_0_CLK, 396 PINCTRL_GRP_UART1_0, 397 PINCTRL_GRP_TRACE0_0_CLK, 398 END_OF_GROUPS, 399 }), 400 }, 401 [PINCTRL_PIN_1] = { 402 .groups = &((uint16_t []) { 403 PINCTRL_GRP_QSPI0_0, 404 PINCTRL_GRP_RESERVED, 405 PINCTRL_GRP_RESERVED, 406 PINCTRL_GRP_TESTSCAN0_0, 407 PINCTRL_GRP_RESERVED, 408 PINCTRL_GRP_GPIO0_1, 409 PINCTRL_GRP_CAN1_0, 410 PINCTRL_GRP_I2C1_0, 411 PINCTRL_GRP_PJTAG0_0, 412 PINCTRL_GRP_SPI0_0_SS2, 413 PINCTRL_GRP_TTC3_0_WAV, 414 PINCTRL_GRP_UART1_0, 415 PINCTRL_GRP_TRACE0_0_CLK, 416 END_OF_GROUPS, 417 }), 418 }, 419 [PINCTRL_PIN_2] = { 420 .groups = &((uint16_t []) { 421 PINCTRL_GRP_QSPI0_0, 422 PINCTRL_GRP_RESERVED, 423 PINCTRL_GRP_RESERVED, 424 PINCTRL_GRP_TESTSCAN0_0, 425 PINCTRL_GRP_RESERVED, 426 PINCTRL_GRP_GPIO0_2, 427 PINCTRL_GRP_CAN0_0, 428 PINCTRL_GRP_I2C0_0, 429 PINCTRL_GRP_PJTAG0_0, 430 PINCTRL_GRP_SPI0_0_SS1, 431 PINCTRL_GRP_TTC2_0_CLK, 432 PINCTRL_GRP_UART0_0, 433 PINCTRL_GRP_TRACE0_0, 434 END_OF_GROUPS, 435 }), 436 }, 437 [PINCTRL_PIN_3] = { 438 .groups = &((uint16_t []) { 439 PINCTRL_GRP_QSPI0_0, 440 PINCTRL_GRP_RESERVED, 441 PINCTRL_GRP_RESERVED, 442 PINCTRL_GRP_TESTSCAN0_0, 443 PINCTRL_GRP_RESERVED, 444 PINCTRL_GRP_GPIO0_3, 445 PINCTRL_GRP_CAN0_0, 446 PINCTRL_GRP_I2C0_0, 447 PINCTRL_GRP_PJTAG0_0, 448 PINCTRL_GRP_SPI0_0_SS0, 449 PINCTRL_GRP_TTC2_0_WAV, 450 PINCTRL_GRP_UART0_0, 451 PINCTRL_GRP_TRACE0_0, 452 END_OF_GROUPS, 453 }), 454 }, 455 [PINCTRL_PIN_4] = { 456 .groups = &((uint16_t []) { 457 PINCTRL_GRP_QSPI0_0, 458 PINCTRL_GRP_RESERVED, 459 PINCTRL_GRP_RESERVED, 460 PINCTRL_GRP_TESTSCAN0_0, 461 PINCTRL_GRP_RESERVED, 462 PINCTRL_GRP_GPIO0_4, 463 PINCTRL_GRP_CAN1_1, 464 PINCTRL_GRP_I2C1_1, 465 PINCTRL_GRP_SWDT1_0_CLK, 466 PINCTRL_GRP_SPI0_0, 467 PINCTRL_GRP_TTC1_0_CLK, 468 PINCTRL_GRP_UART1_1, 469 PINCTRL_GRP_TRACE0_0, 470 END_OF_GROUPS, 471 }), 472 }, 473 [PINCTRL_PIN_5] = { 474 .groups = &((uint16_t []) { 475 PINCTRL_GRP_QSPI_SS, 476 PINCTRL_GRP_RESERVED, 477 PINCTRL_GRP_RESERVED, 478 PINCTRL_GRP_TESTSCAN0_0, 479 PINCTRL_GRP_RESERVED, 480 PINCTRL_GRP_GPIO0_5, 481 PINCTRL_GRP_CAN1_1, 482 PINCTRL_GRP_I2C1_1, 483 PINCTRL_GRP_SWDT1_0_RST, 484 PINCTRL_GRP_SPI0_0, 485 PINCTRL_GRP_TTC1_0_WAV, 486 PINCTRL_GRP_UART1_1, 487 PINCTRL_GRP_TRACE0_0, 488 END_OF_GROUPS, 489 }), 490 }, 491 [PINCTRL_PIN_6] = { 492 .groups = &((uint16_t []) { 493 PINCTRL_GRP_QSPI_FBCLK, 494 PINCTRL_GRP_RESERVED, 495 PINCTRL_GRP_RESERVED, 496 PINCTRL_GRP_TESTSCAN0_0, 497 PINCTRL_GRP_RESERVED, 498 PINCTRL_GRP_GPIO0_6, 499 PINCTRL_GRP_CAN0_1, 500 PINCTRL_GRP_I2C0_1, 501 PINCTRL_GRP_SWDT0_0_CLK, 502 PINCTRL_GRP_SPI1_0, 503 PINCTRL_GRP_TTC0_0_CLK, 504 PINCTRL_GRP_UART0_1, 505 PINCTRL_GRP_TRACE0_0, 506 END_OF_GROUPS, 507 }), 508 }, 509 [PINCTRL_PIN_7] = { 510 .groups = &((uint16_t []) { 511 PINCTRL_GRP_QSPI_SS, 512 PINCTRL_GRP_RESERVED, 513 PINCTRL_GRP_RESERVED, 514 PINCTRL_GRP_TESTSCAN0_0, 515 PINCTRL_GRP_RESERVED, 516 PINCTRL_GRP_GPIO0_7, 517 PINCTRL_GRP_CAN0_1, 518 PINCTRL_GRP_I2C0_1, 519 PINCTRL_GRP_SWDT0_0_RST, 520 PINCTRL_GRP_SPI1_0_SS2, 521 PINCTRL_GRP_TTC0_0_WAV, 522 PINCTRL_GRP_UART0_1, 523 PINCTRL_GRP_TRACE0_0, 524 END_OF_GROUPS, 525 }), 526 }, 527 [PINCTRL_PIN_8] = { 528 .groups = &((uint16_t []) { 529 PINCTRL_GRP_QSPI0_0, 530 PINCTRL_GRP_RESERVED, 531 PINCTRL_GRP_RESERVED, 532 PINCTRL_GRP_TESTSCAN0_0, 533 PINCTRL_GRP_RESERVED, 534 PINCTRL_GRP_GPIO0_8, 535 PINCTRL_GRP_CAN1_2, 536 PINCTRL_GRP_I2C1_2, 537 PINCTRL_GRP_SWDT1_1_CLK, 538 PINCTRL_GRP_SPI1_0_SS1, 539 PINCTRL_GRP_TTC3_1_CLK, 540 PINCTRL_GRP_UART1_2, 541 PINCTRL_GRP_TRACE0_0, 542 END_OF_GROUPS, 543 }), 544 }, 545 [PINCTRL_PIN_9] = { 546 .groups = &((uint16_t []) { 547 PINCTRL_GRP_QSPI0_0, 548 PINCTRL_GRP_NAND0_0_CE, 549 PINCTRL_GRP_RESERVED, 550 PINCTRL_GRP_TESTSCAN0_0, 551 PINCTRL_GRP_RESERVED, 552 PINCTRL_GRP_GPIO0_9, 553 PINCTRL_GRP_CAN1_2, 554 PINCTRL_GRP_I2C1_2, 555 PINCTRL_GRP_SWDT1_1_RST, 556 PINCTRL_GRP_SPI1_0_SS0, 557 PINCTRL_GRP_TTC3_1_WAV, 558 PINCTRL_GRP_UART1_2, 559 PINCTRL_GRP_TRACE0_0, 560 END_OF_GROUPS, 561 }), 562 }, 563 [PINCTRL_PIN_10] = { 564 .groups = &((uint16_t []) { 565 PINCTRL_GRP_QSPI0_0, 566 PINCTRL_GRP_NAND0_0_RB, 567 PINCTRL_GRP_RESERVED, 568 PINCTRL_GRP_TESTSCAN0_0, 569 PINCTRL_GRP_RESERVED, 570 PINCTRL_GRP_GPIO0_10, 571 PINCTRL_GRP_CAN0_2, 572 PINCTRL_GRP_I2C0_2, 573 PINCTRL_GRP_SWDT0_1_CLK, 574 PINCTRL_GRP_SPI1_0, 575 PINCTRL_GRP_TTC2_1_CLK, 576 PINCTRL_GRP_UART0_2, 577 PINCTRL_GRP_TRACE0_0, 578 END_OF_GROUPS, 579 }), 580 }, 581 [PINCTRL_PIN_11] = { 582 .groups = &((uint16_t []) { 583 PINCTRL_GRP_QSPI0_0, 584 PINCTRL_GRP_NAND0_0_RB, 585 PINCTRL_GRP_RESERVED, 586 PINCTRL_GRP_TESTSCAN0_0, 587 PINCTRL_GRP_RESERVED, 588 PINCTRL_GRP_GPIO0_11, 589 PINCTRL_GRP_CAN0_2, 590 PINCTRL_GRP_I2C0_2, 591 PINCTRL_GRP_SWDT0_1_RST, 592 PINCTRL_GRP_SPI1_0, 593 PINCTRL_GRP_TTC2_1_WAV, 594 PINCTRL_GRP_UART0_2, 595 PINCTRL_GRP_TRACE0_0, 596 END_OF_GROUPS, 597 }), 598 }, 599 [PINCTRL_PIN_12] = { 600 .groups = &((uint16_t []) { 601 PINCTRL_GRP_QSPI0_0, 602 PINCTRL_GRP_NAND0_0_DQS, 603 PINCTRL_GRP_RESERVED, 604 PINCTRL_GRP_TESTSCAN0_0, 605 PINCTRL_GRP_RESERVED, 606 PINCTRL_GRP_GPIO0_12, 607 PINCTRL_GRP_CAN1_3, 608 PINCTRL_GRP_I2C1_3, 609 PINCTRL_GRP_PJTAG0_1, 610 PINCTRL_GRP_SPI0_1, 611 PINCTRL_GRP_TTC1_1_CLK, 612 PINCTRL_GRP_UART1_3, 613 PINCTRL_GRP_TRACE0_0, 614 END_OF_GROUPS, 615 }), 616 }, 617 [PINCTRL_PIN_13] = { 618 .groups = &((uint16_t []) { 619 PINCTRL_GRP_RESERVED, 620 PINCTRL_GRP_NAND0_0, 621 PINCTRL_GRP_SDIO0_0, 622 PINCTRL_GRP_TESTSCAN0_0, 623 PINCTRL_GRP_RESERVED, 624 PINCTRL_GRP_GPIO0_13, 625 PINCTRL_GRP_CAN1_3, 626 PINCTRL_GRP_I2C1_3, 627 PINCTRL_GRP_PJTAG0_1, 628 PINCTRL_GRP_SPI0_1_SS2, 629 PINCTRL_GRP_TTC1_1_WAV, 630 PINCTRL_GRP_UART1_3, 631 PINCTRL_GRP_TRACE0_0, 632 PINCTRL_GRP_SDIO0_4BIT_0_0, 633 PINCTRL_GRP_SDIO0_1BIT_0_0, 634 END_OF_GROUPS, 635 }), 636 }, 637 [PINCTRL_PIN_14] = { 638 .groups = &((uint16_t []) { 639 PINCTRL_GRP_RESERVED, 640 PINCTRL_GRP_NAND0_0, 641 PINCTRL_GRP_SDIO0_0, 642 PINCTRL_GRP_TESTSCAN0_0, 643 PINCTRL_GRP_RESERVED, 644 PINCTRL_GRP_GPIO0_14, 645 PINCTRL_GRP_CAN0_3, 646 PINCTRL_GRP_I2C0_3, 647 PINCTRL_GRP_PJTAG0_1, 648 PINCTRL_GRP_SPI0_1_SS1, 649 PINCTRL_GRP_TTC0_1_CLK, 650 PINCTRL_GRP_UART0_3, 651 PINCTRL_GRP_TRACE0_0, 652 PINCTRL_GRP_SDIO0_4BIT_0_0, 653 PINCTRL_GRP_SDIO0_1BIT_0_1, 654 END_OF_GROUPS, 655 }), 656 }, 657 [PINCTRL_PIN_15] = { 658 .groups = &((uint16_t []) { 659 PINCTRL_GRP_RESERVED, 660 PINCTRL_GRP_NAND0_0, 661 PINCTRL_GRP_SDIO0_0, 662 PINCTRL_GRP_TESTSCAN0_0, 663 PINCTRL_GRP_RESERVED, 664 PINCTRL_GRP_GPIO0_15, 665 PINCTRL_GRP_CAN0_3, 666 PINCTRL_GRP_I2C0_3, 667 PINCTRL_GRP_PJTAG0_1, 668 PINCTRL_GRP_SPI0_1_SS0, 669 PINCTRL_GRP_TTC0_1_WAV, 670 PINCTRL_GRP_UART0_3, 671 PINCTRL_GRP_TRACE0_0, 672 PINCTRL_GRP_SDIO0_4BIT_0_0, 673 PINCTRL_GRP_SDIO0_1BIT_0_2, 674 END_OF_GROUPS, 675 }), 676 }, 677 [PINCTRL_PIN_16] = { 678 .groups = &((uint16_t []) { 679 PINCTRL_GRP_RESERVED, 680 PINCTRL_GRP_NAND0_0, 681 PINCTRL_GRP_SDIO0_0, 682 PINCTRL_GRP_TESTSCAN0_0, 683 PINCTRL_GRP_RESERVED, 684 PINCTRL_GRP_GPIO0_16, 685 PINCTRL_GRP_CAN1_4, 686 PINCTRL_GRP_I2C1_4, 687 PINCTRL_GRP_SWDT1_2_CLK, 688 PINCTRL_GRP_SPI0_1, 689 PINCTRL_GRP_TTC3_2_CLK, 690 PINCTRL_GRP_UART1_4, 691 PINCTRL_GRP_TRACE0_0, 692 PINCTRL_GRP_SDIO0_4BIT_0_0, 693 PINCTRL_GRP_SDIO0_1BIT_0_3, 694 END_OF_GROUPS, 695 }), 696 }, 697 [PINCTRL_PIN_17] = { 698 .groups = &((uint16_t []) { 699 PINCTRL_GRP_RESERVED, 700 PINCTRL_GRP_NAND0_0, 701 PINCTRL_GRP_SDIO0_0, 702 PINCTRL_GRP_TESTSCAN0_0, 703 PINCTRL_GRP_RESERVED, 704 PINCTRL_GRP_GPIO0_17, 705 PINCTRL_GRP_CAN1_4, 706 PINCTRL_GRP_I2C1_4, 707 PINCTRL_GRP_SWDT1_2_RST, 708 PINCTRL_GRP_SPI0_1, 709 PINCTRL_GRP_TTC3_2_WAV, 710 PINCTRL_GRP_UART1_4, 711 PINCTRL_GRP_TRACE0_0, 712 PINCTRL_GRP_SDIO0_4BIT_0_1, 713 PINCTRL_GRP_SDIO0_1BIT_0_4, 714 END_OF_GROUPS, 715 }), 716 }, 717 [PINCTRL_PIN_18] = { 718 .groups = &((uint16_t []) { 719 PINCTRL_GRP_RESERVED, 720 PINCTRL_GRP_NAND0_0, 721 PINCTRL_GRP_SDIO0_0, 722 PINCTRL_GRP_TESTSCAN0_0, 723 PINCTRL_GRP_CSU0_0, 724 PINCTRL_GRP_GPIO0_18, 725 PINCTRL_GRP_CAN0_4, 726 PINCTRL_GRP_I2C0_4, 727 PINCTRL_GRP_SWDT0_2_CLK, 728 PINCTRL_GRP_SPI1_1, 729 PINCTRL_GRP_TTC2_2_CLK, 730 PINCTRL_GRP_UART0_4, 731 PINCTRL_GRP_RESERVED, 732 PINCTRL_GRP_SDIO0_4BIT_0_1, 733 PINCTRL_GRP_SDIO0_1BIT_0_5, 734 END_OF_GROUPS, 735 }), 736 }, 737 [PINCTRL_PIN_19] = { 738 .groups = &((uint16_t []) { 739 PINCTRL_GRP_RESERVED, 740 PINCTRL_GRP_NAND0_0, 741 PINCTRL_GRP_SDIO0_0, 742 PINCTRL_GRP_TESTSCAN0_0, 743 PINCTRL_GRP_CSU0_1, 744 PINCTRL_GRP_GPIO0_19, 745 PINCTRL_GRP_CAN0_4, 746 PINCTRL_GRP_I2C0_4, 747 PINCTRL_GRP_SWDT0_2_RST, 748 PINCTRL_GRP_SPI1_1_SS2, 749 PINCTRL_GRP_TTC2_2_WAV, 750 PINCTRL_GRP_UART0_4, 751 PINCTRL_GRP_RESERVED, 752 PINCTRL_GRP_SDIO0_4BIT_0_1, 753 PINCTRL_GRP_SDIO0_1BIT_0_6, 754 END_OF_GROUPS, 755 }), 756 }, 757 [PINCTRL_PIN_20] = { 758 .groups = &((uint16_t []) { 759 PINCTRL_GRP_RESERVED, 760 PINCTRL_GRP_NAND0_0, 761 PINCTRL_GRP_SDIO0_0, 762 PINCTRL_GRP_TESTSCAN0_0, 763 PINCTRL_GRP_CSU0_2, 764 PINCTRL_GRP_GPIO0_20, 765 PINCTRL_GRP_CAN1_5, 766 PINCTRL_GRP_I2C1_5, 767 PINCTRL_GRP_SWDT1_3_CLK, 768 PINCTRL_GRP_SPI1_1_SS1, 769 PINCTRL_GRP_TTC1_2_CLK, 770 PINCTRL_GRP_UART1_5, 771 PINCTRL_GRP_RESERVED, 772 PINCTRL_GRP_SDIO0_4BIT_0_1, 773 PINCTRL_GRP_SDIO0_1BIT_0_7, 774 END_OF_GROUPS, 775 }), 776 }, 777 [PINCTRL_PIN_21] = { 778 .groups = &((uint16_t []) { 779 PINCTRL_GRP_RESERVED, 780 PINCTRL_GRP_NAND0_0, 781 PINCTRL_GRP_SDIO0_0, 782 PINCTRL_GRP_TESTSCAN0_0, 783 PINCTRL_GRP_CSU0_3, 784 PINCTRL_GRP_GPIO0_21, 785 PINCTRL_GRP_CAN1_5, 786 PINCTRL_GRP_I2C1_5, 787 PINCTRL_GRP_SWDT1_3_RST, 788 PINCTRL_GRP_SPI1_1_SS0, 789 PINCTRL_GRP_TTC1_2_WAV, 790 PINCTRL_GRP_UART1_5, 791 PINCTRL_GRP_RESERVED, 792 PINCTRL_GRP_SDIO0_4BIT_0_0, 793 PINCTRL_GRP_SDIO0_4BIT_0_1, 794 PINCTRL_GRP_SDIO0_1BIT_0_0, 795 PINCTRL_GRP_SDIO0_1BIT_0_1, 796 PINCTRL_GRP_SDIO0_1BIT_0_2, 797 PINCTRL_GRP_SDIO0_1BIT_0_3, 798 PINCTRL_GRP_SDIO0_1BIT_0_4, 799 PINCTRL_GRP_SDIO0_1BIT_0_5, 800 PINCTRL_GRP_SDIO0_1BIT_0_6, 801 PINCTRL_GRP_SDIO0_1BIT_0_7, 802 END_OF_GROUPS, 803 }), 804 }, 805 [PINCTRL_PIN_22] = { 806 .groups = &((uint16_t []) { 807 PINCTRL_GRP_RESERVED, 808 PINCTRL_GRP_NAND0_0, 809 PINCTRL_GRP_SDIO0_0, 810 PINCTRL_GRP_TESTSCAN0_0, 811 PINCTRL_GRP_CSU0_4, 812 PINCTRL_GRP_GPIO0_22, 813 PINCTRL_GRP_CAN0_5, 814 PINCTRL_GRP_I2C0_5, 815 PINCTRL_GRP_SWDT0_3_CLK, 816 PINCTRL_GRP_SPI1_1, 817 PINCTRL_GRP_TTC0_2_CLK, 818 PINCTRL_GRP_UART0_5, 819 PINCTRL_GRP_RESERVED, 820 PINCTRL_GRP_SDIO0_4BIT_0_0, 821 PINCTRL_GRP_SDIO0_4BIT_0_1, 822 PINCTRL_GRP_SDIO0_1BIT_0_0, 823 PINCTRL_GRP_SDIO0_1BIT_0_1, 824 PINCTRL_GRP_SDIO0_1BIT_0_2, 825 PINCTRL_GRP_SDIO0_1BIT_0_3, 826 PINCTRL_GRP_SDIO0_1BIT_0_4, 827 PINCTRL_GRP_SDIO0_1BIT_0_5, 828 PINCTRL_GRP_SDIO0_1BIT_0_6, 829 PINCTRL_GRP_SDIO0_1BIT_0_7, 830 END_OF_GROUPS, 831 }), 832 }, 833 [PINCTRL_PIN_23] = { 834 .groups = &((uint16_t []) { 835 PINCTRL_GRP_RESERVED, 836 PINCTRL_GRP_NAND0_0, 837 PINCTRL_GRP_SDIO0_0_PC, 838 PINCTRL_GRP_TESTSCAN0_0, 839 PINCTRL_GRP_CSU0_5, 840 PINCTRL_GRP_GPIO0_23, 841 PINCTRL_GRP_CAN0_5, 842 PINCTRL_GRP_I2C0_5, 843 PINCTRL_GRP_SWDT0_3_RST, 844 PINCTRL_GRP_SPI1_1, 845 PINCTRL_GRP_TTC0_2_WAV, 846 PINCTRL_GRP_UART0_5, 847 PINCTRL_GRP_RESERVED, 848 END_OF_GROUPS, 849 }), 850 }, 851 [PINCTRL_PIN_24] = { 852 .groups = &((uint16_t []) { 853 PINCTRL_GRP_RESERVED, 854 PINCTRL_GRP_NAND0_0, 855 PINCTRL_GRP_SDIO0_0_CD, 856 PINCTRL_GRP_TESTSCAN0_0, 857 PINCTRL_GRP_CSU0_6, 858 PINCTRL_GRP_GPIO0_24, 859 PINCTRL_GRP_CAN1_6, 860 PINCTRL_GRP_I2C1_6, 861 PINCTRL_GRP_SWDT1_4_CLK, 862 PINCTRL_GRP_RESERVED, 863 PINCTRL_GRP_TTC3_3_CLK, 864 PINCTRL_GRP_UART1_6, 865 PINCTRL_GRP_RESERVED, 866 END_OF_GROUPS, 867 }), 868 }, 869 [PINCTRL_PIN_25] = { 870 .groups = &((uint16_t []) { 871 PINCTRL_GRP_RESERVED, 872 PINCTRL_GRP_NAND0_0, 873 PINCTRL_GRP_SDIO0_0_WP, 874 PINCTRL_GRP_TESTSCAN0_0, 875 PINCTRL_GRP_CSU0_7, 876 PINCTRL_GRP_GPIO0_25, 877 PINCTRL_GRP_CAN1_6, 878 PINCTRL_GRP_I2C1_6, 879 PINCTRL_GRP_SWDT1_4_RST, 880 PINCTRL_GRP_RESERVED, 881 PINCTRL_GRP_TTC3_3_WAV, 882 PINCTRL_GRP_UART1_6, 883 PINCTRL_GRP_RESERVED, 884 END_OF_GROUPS, 885 }), 886 }, 887 [PINCTRL_PIN_26] = { 888 .groups = &((uint16_t []) { 889 PINCTRL_GRP_ETHERNET0_0, 890 PINCTRL_GRP_GEMTSU0_0, 891 PINCTRL_GRP_NAND0_1_CE, 892 PINCTRL_GRP_PMU0_0, 893 PINCTRL_GRP_TESTSCAN0_0, 894 PINCTRL_GRP_CSU0_8, 895 PINCTRL_GRP_GPIO0_26, 896 PINCTRL_GRP_CAN0_6, 897 PINCTRL_GRP_I2C0_6, 898 PINCTRL_GRP_PJTAG0_2, 899 PINCTRL_GRP_SPI0_2, 900 PINCTRL_GRP_TTC2_3_CLK, 901 PINCTRL_GRP_UART0_6, 902 PINCTRL_GRP_TRACE0_1, 903 END_OF_GROUPS, 904 }), 905 }, 906 [PINCTRL_PIN_27] = { 907 .groups = &((uint16_t []) { 908 PINCTRL_GRP_ETHERNET0_0, 909 PINCTRL_GRP_NAND0_1_RB, 910 PINCTRL_GRP_PMU0_1, 911 PINCTRL_GRP_TESTSCAN0_0, 912 PINCTRL_GRP_DPAUX0_0, 913 PINCTRL_GRP_GPIO0_27, 914 PINCTRL_GRP_CAN0_6, 915 PINCTRL_GRP_I2C0_6, 916 PINCTRL_GRP_PJTAG0_2, 917 PINCTRL_GRP_SPI0_2_SS2, 918 PINCTRL_GRP_TTC2_3_WAV, 919 PINCTRL_GRP_UART0_6, 920 PINCTRL_GRP_TRACE0_1, 921 END_OF_GROUPS, 922 }), 923 }, 924 [PINCTRL_PIN_28] = { 925 .groups = &((uint16_t []) { 926 PINCTRL_GRP_ETHERNET0_0, 927 PINCTRL_GRP_NAND0_1_RB, 928 PINCTRL_GRP_PMU0_2, 929 PINCTRL_GRP_TESTSCAN0_0, 930 PINCTRL_GRP_DPAUX0_0, 931 PINCTRL_GRP_GPIO0_28, 932 PINCTRL_GRP_CAN1_7, 933 PINCTRL_GRP_I2C1_7, 934 PINCTRL_GRP_PJTAG0_2, 935 PINCTRL_GRP_SPI0_2_SS1, 936 PINCTRL_GRP_TTC1_3_CLK, 937 PINCTRL_GRP_UART1_7, 938 PINCTRL_GRP_TRACE0_1, 939 END_OF_GROUPS, 940 }), 941 }, 942 [PINCTRL_PIN_29] = { 943 .groups = &((uint16_t []) { 944 PINCTRL_GRP_ETHERNET0_0, 945 PINCTRL_GRP_PCIE0_0, 946 PINCTRL_GRP_PMU0_3, 947 PINCTRL_GRP_TESTSCAN0_0, 948 PINCTRL_GRP_DPAUX0_1, 949 PINCTRL_GRP_GPIO0_29, 950 PINCTRL_GRP_CAN1_7, 951 PINCTRL_GRP_I2C1_7, 952 PINCTRL_GRP_PJTAG0_2, 953 PINCTRL_GRP_SPI0_2_SS0, 954 PINCTRL_GRP_TTC1_3_WAV, 955 PINCTRL_GRP_UART1_7, 956 PINCTRL_GRP_TRACE0_1, 957 END_OF_GROUPS, 958 }), 959 }, 960 [PINCTRL_PIN_30] = { 961 .groups = &((uint16_t []) { 962 PINCTRL_GRP_ETHERNET0_0, 963 PINCTRL_GRP_PCIE0_1, 964 PINCTRL_GRP_PMU0_4, 965 PINCTRL_GRP_TESTSCAN0_0, 966 PINCTRL_GRP_DPAUX0_1, 967 PINCTRL_GRP_GPIO0_30, 968 PINCTRL_GRP_CAN0_7, 969 PINCTRL_GRP_I2C0_7, 970 PINCTRL_GRP_SWDT0_4_CLK, 971 PINCTRL_GRP_SPI0_2, 972 PINCTRL_GRP_TTC0_3_CLK, 973 PINCTRL_GRP_UART0_7, 974 PINCTRL_GRP_TRACE0_1, 975 END_OF_GROUPS, 976 }), 977 }, 978 [PINCTRL_PIN_31] = { 979 .groups = &((uint16_t []) { 980 PINCTRL_GRP_ETHERNET0_0, 981 PINCTRL_GRP_PCIE0_2, 982 PINCTRL_GRP_PMU0_5, 983 PINCTRL_GRP_TESTSCAN0_0, 984 PINCTRL_GRP_CSU0_9, 985 PINCTRL_GRP_GPIO0_31, 986 PINCTRL_GRP_CAN0_7, 987 PINCTRL_GRP_I2C0_7, 988 PINCTRL_GRP_SWDT0_4_RST, 989 PINCTRL_GRP_SPI0_2, 990 PINCTRL_GRP_TTC0_3_WAV, 991 PINCTRL_GRP_UART0_7, 992 PINCTRL_GRP_TRACE0_1, 993 END_OF_GROUPS, 994 }), 995 }, 996 [PINCTRL_PIN_32] = { 997 .groups = &((uint16_t []) { 998 PINCTRL_GRP_ETHERNET0_0, 999 PINCTRL_GRP_NAND0_1_DQS, 1000 PINCTRL_GRP_PMU0_6, 1001 PINCTRL_GRP_TESTSCAN0_0, 1002 PINCTRL_GRP_CSU0_10, 1003 PINCTRL_GRP_GPIO0_32, 1004 PINCTRL_GRP_CAN1_8, 1005 PINCTRL_GRP_I2C1_8, 1006 PINCTRL_GRP_SWDT1_5_CLK, 1007 PINCTRL_GRP_SPI1_2, 1008 PINCTRL_GRP_TTC3_4_CLK, 1009 PINCTRL_GRP_UART1_8, 1010 PINCTRL_GRP_TRACE0_1, 1011 END_OF_GROUPS, 1012 }), 1013 }, 1014 [PINCTRL_PIN_33] = { 1015 .groups = &((uint16_t []) { 1016 PINCTRL_GRP_ETHERNET0_0, 1017 PINCTRL_GRP_PCIE0_3, 1018 PINCTRL_GRP_PMU0_7, 1019 PINCTRL_GRP_TESTSCAN0_0, 1020 PINCTRL_GRP_CSU0_11, 1021 PINCTRL_GRP_GPIO0_33, 1022 PINCTRL_GRP_CAN1_8, 1023 PINCTRL_GRP_I2C1_8, 1024 PINCTRL_GRP_SWDT1_5_RST, 1025 PINCTRL_GRP_SPI1_2_SS2, 1026 PINCTRL_GRP_TTC3_4_WAV, 1027 PINCTRL_GRP_UART1_8, 1028 PINCTRL_GRP_TRACE0_1, 1029 END_OF_GROUPS, 1030 }), 1031 }, 1032 [PINCTRL_PIN_34] = { 1033 .groups = &((uint16_t []) { 1034 PINCTRL_GRP_ETHERNET0_0, 1035 PINCTRL_GRP_PCIE0_4, 1036 PINCTRL_GRP_PMU0_8, 1037 PINCTRL_GRP_TESTSCAN0_0, 1038 PINCTRL_GRP_DPAUX0_2, 1039 PINCTRL_GRP_GPIO0_34, 1040 PINCTRL_GRP_CAN0_8, 1041 PINCTRL_GRP_I2C0_8, 1042 PINCTRL_GRP_SWDT0_5_CLK, 1043 PINCTRL_GRP_SPI1_2_SS1, 1044 PINCTRL_GRP_TTC2_4_CLK, 1045 PINCTRL_GRP_UART0_8, 1046 PINCTRL_GRP_TRACE0_1, 1047 END_OF_GROUPS, 1048 }), 1049 }, 1050 [PINCTRL_PIN_35] = { 1051 .groups = &((uint16_t []) { 1052 PINCTRL_GRP_ETHERNET0_0, 1053 PINCTRL_GRP_PCIE0_5, 1054 PINCTRL_GRP_PMU0_9, 1055 PINCTRL_GRP_TESTSCAN0_0, 1056 PINCTRL_GRP_DPAUX0_2, 1057 PINCTRL_GRP_GPIO0_35, 1058 PINCTRL_GRP_CAN0_8, 1059 PINCTRL_GRP_I2C0_8, 1060 PINCTRL_GRP_SWDT0_5_RST, 1061 PINCTRL_GRP_SPI1_2_SS0, 1062 PINCTRL_GRP_TTC2_4_WAV, 1063 PINCTRL_GRP_UART0_8, 1064 PINCTRL_GRP_TRACE0_1, 1065 END_OF_GROUPS, 1066 }), 1067 }, 1068 [PINCTRL_PIN_36] = { 1069 .groups = &((uint16_t []) { 1070 PINCTRL_GRP_ETHERNET0_0, 1071 PINCTRL_GRP_PCIE0_6, 1072 PINCTRL_GRP_PMU0_10, 1073 PINCTRL_GRP_TESTSCAN0_0, 1074 PINCTRL_GRP_DPAUX0_3, 1075 PINCTRL_GRP_GPIO0_36, 1076 PINCTRL_GRP_CAN1_9, 1077 PINCTRL_GRP_I2C1_9, 1078 PINCTRL_GRP_SWDT1_6_CLK, 1079 PINCTRL_GRP_SPI1_2, 1080 PINCTRL_GRP_TTC1_4_CLK, 1081 PINCTRL_GRP_UART1_9, 1082 PINCTRL_GRP_TRACE0_1, 1083 END_OF_GROUPS, 1084 }), 1085 }, 1086 [PINCTRL_PIN_37] = { 1087 .groups = &((uint16_t []) { 1088 PINCTRL_GRP_ETHERNET0_0, 1089 PINCTRL_GRP_PCIE0_7, 1090 PINCTRL_GRP_PMU0_11, 1091 PINCTRL_GRP_TESTSCAN0_0, 1092 PINCTRL_GRP_DPAUX0_3, 1093 PINCTRL_GRP_GPIO0_37, 1094 PINCTRL_GRP_CAN1_9, 1095 PINCTRL_GRP_I2C1_9, 1096 PINCTRL_GRP_SWDT1_6_RST, 1097 PINCTRL_GRP_SPI1_2, 1098 PINCTRL_GRP_TTC1_4_WAV, 1099 PINCTRL_GRP_UART1_9, 1100 PINCTRL_GRP_TRACE0_1, 1101 END_OF_GROUPS, 1102 }), 1103 }, 1104 [PINCTRL_PIN_38] = { 1105 .groups = &((uint16_t []) { 1106 PINCTRL_GRP_ETHERNET1_0, 1107 PINCTRL_GRP_RESERVED, 1108 PINCTRL_GRP_SDIO0_1, 1109 PINCTRL_GRP_RESERVED, 1110 PINCTRL_GRP_RESERVED, 1111 PINCTRL_GRP_GPIO0_38, 1112 PINCTRL_GRP_CAN0_9, 1113 PINCTRL_GRP_I2C0_9, 1114 PINCTRL_GRP_PJTAG0_3, 1115 PINCTRL_GRP_SPI0_3, 1116 PINCTRL_GRP_TTC0_4_CLK, 1117 PINCTRL_GRP_UART0_9, 1118 PINCTRL_GRP_TRACE0_1_CLK, 1119 PINCTRL_GRP_SDIO0_4BIT_1_0, 1120 PINCTRL_GRP_SDIO0_4BIT_1_1, 1121 PINCTRL_GRP_SDIO0_1BIT_1_0, 1122 PINCTRL_GRP_SDIO0_1BIT_1_1, 1123 PINCTRL_GRP_SDIO0_1BIT_1_2, 1124 PINCTRL_GRP_SDIO0_1BIT_1_3, 1125 PINCTRL_GRP_SDIO0_1BIT_1_4, 1126 PINCTRL_GRP_SDIO0_1BIT_1_5, 1127 PINCTRL_GRP_SDIO0_1BIT_1_6, 1128 PINCTRL_GRP_SDIO0_1BIT_1_7, 1129 END_OF_GROUPS, 1130 }), 1131 }, 1132 [PINCTRL_PIN_39] = { 1133 .groups = &((uint16_t []) { 1134 PINCTRL_GRP_ETHERNET1_0, 1135 PINCTRL_GRP_RESERVED, 1136 PINCTRL_GRP_SDIO0_1_CD, 1137 PINCTRL_GRP_SDIO1_0, 1138 PINCTRL_GRP_RESERVED, 1139 PINCTRL_GRP_GPIO0_39, 1140 PINCTRL_GRP_CAN0_9, 1141 PINCTRL_GRP_I2C0_9, 1142 PINCTRL_GRP_PJTAG0_3, 1143 PINCTRL_GRP_SPI0_3_SS2, 1144 PINCTRL_GRP_TTC0_4_WAV, 1145 PINCTRL_GRP_UART0_9, 1146 PINCTRL_GRP_TRACE0_1_CLK, 1147 PINCTRL_GRP_SDIO1_4BIT_0_0, 1148 PINCTRL_GRP_SDIO1_1BIT_0_0, 1149 END_OF_GROUPS, 1150 }), 1151 }, 1152 [PINCTRL_PIN_40] = { 1153 .groups = &((uint16_t []) { 1154 PINCTRL_GRP_ETHERNET1_0, 1155 PINCTRL_GRP_RESERVED, 1156 PINCTRL_GRP_SDIO0_1, 1157 PINCTRL_GRP_SDIO1_0, 1158 PINCTRL_GRP_RESERVED, 1159 PINCTRL_GRP_GPIO0_40, 1160 PINCTRL_GRP_CAN1_10, 1161 PINCTRL_GRP_I2C1_10, 1162 PINCTRL_GRP_PJTAG0_3, 1163 PINCTRL_GRP_SPI0_3_SS1, 1164 PINCTRL_GRP_TTC3_5_CLK, 1165 PINCTRL_GRP_UART1_10, 1166 PINCTRL_GRP_TRACE0_1, 1167 PINCTRL_GRP_SDIO0_4BIT_1_0, 1168 PINCTRL_GRP_SDIO0_4BIT_1_1, 1169 PINCTRL_GRP_SDIO0_1BIT_1_0, 1170 PINCTRL_GRP_SDIO0_1BIT_1_1, 1171 PINCTRL_GRP_SDIO0_1BIT_1_2, 1172 PINCTRL_GRP_SDIO0_1BIT_1_3, 1173 PINCTRL_GRP_SDIO0_1BIT_1_4, 1174 PINCTRL_GRP_SDIO0_1BIT_1_5, 1175 PINCTRL_GRP_SDIO0_1BIT_1_6, 1176 PINCTRL_GRP_SDIO0_1BIT_1_7, 1177 PINCTRL_GRP_SDIO1_4BIT_0_0, 1178 PINCTRL_GRP_SDIO1_1BIT_0_1, 1179 END_OF_GROUPS, 1180 }), 1181 }, 1182 [PINCTRL_PIN_41] = { 1183 .groups = &((uint16_t []) { 1184 PINCTRL_GRP_ETHERNET1_0, 1185 PINCTRL_GRP_RESERVED, 1186 PINCTRL_GRP_SDIO0_1, 1187 PINCTRL_GRP_SDIO1_0, 1188 PINCTRL_GRP_RESERVED, 1189 PINCTRL_GRP_GPIO0_41, 1190 PINCTRL_GRP_CAN1_10, 1191 PINCTRL_GRP_I2C1_10, 1192 PINCTRL_GRP_PJTAG0_3, 1193 PINCTRL_GRP_SPI0_3_SS0, 1194 PINCTRL_GRP_TTC3_5_WAV, 1195 PINCTRL_GRP_UART1_10, 1196 PINCTRL_GRP_TRACE0_1, 1197 PINCTRL_GRP_SDIO0_4BIT_1_0, 1198 PINCTRL_GRP_SDIO0_1BIT_1_0, 1199 PINCTRL_GRP_SDIO1_4BIT_0_0, 1200 PINCTRL_GRP_SDIO1_1BIT_0_2, 1201 END_OF_GROUPS, 1202 }), 1203 }, 1204 [PINCTRL_PIN_42] = { 1205 .groups = &((uint16_t []) { 1206 PINCTRL_GRP_ETHERNET1_0, 1207 PINCTRL_GRP_RESERVED, 1208 PINCTRL_GRP_SDIO0_1, 1209 PINCTRL_GRP_SDIO1_0, 1210 PINCTRL_GRP_RESERVED, 1211 PINCTRL_GRP_GPIO0_42, 1212 PINCTRL_GRP_CAN0_10, 1213 PINCTRL_GRP_I2C0_10, 1214 PINCTRL_GRP_SWDT0_6_CLK, 1215 PINCTRL_GRP_SPI0_3, 1216 PINCTRL_GRP_TTC2_5_CLK, 1217 PINCTRL_GRP_UART0_10, 1218 PINCTRL_GRP_TRACE0_1, 1219 PINCTRL_GRP_SDIO0_1, 1220 PINCTRL_GRP_SDIO0_4BIT_1_0, 1221 PINCTRL_GRP_SDIO0_1BIT_1_1, 1222 PINCTRL_GRP_SDIO1_4BIT_0_0, 1223 PINCTRL_GRP_SDIO1_1BIT_0_3, 1224 END_OF_GROUPS, 1225 }), 1226 }, 1227 [PINCTRL_PIN_43] = { 1228 .groups = &((uint16_t []) { 1229 PINCTRL_GRP_ETHERNET1_0, 1230 PINCTRL_GRP_RESERVED, 1231 PINCTRL_GRP_SDIO0_1, 1232 PINCTRL_GRP_SDIO1_0_PC, 1233 PINCTRL_GRP_RESERVED, 1234 PINCTRL_GRP_GPIO0_43, 1235 PINCTRL_GRP_CAN0_10, 1236 PINCTRL_GRP_I2C0_10, 1237 PINCTRL_GRP_SWDT0_6_RST, 1238 PINCTRL_GRP_SPI0_3, 1239 PINCTRL_GRP_TTC2_5_WAV, 1240 PINCTRL_GRP_UART0_10, 1241 PINCTRL_GRP_TRACE0_1, 1242 PINCTRL_GRP_SDIO0_4BIT_1_0, 1243 PINCTRL_GRP_SDIO0_1BIT_1_2, 1244 END_OF_GROUPS, 1245 }), 1246 }, 1247 [PINCTRL_PIN_44] = { 1248 .groups = &((uint16_t []) { 1249 PINCTRL_GRP_ETHERNET1_0, 1250 PINCTRL_GRP_RESERVED, 1251 PINCTRL_GRP_SDIO0_1, 1252 PINCTRL_GRP_SDIO1_0_WP, 1253 PINCTRL_GRP_RESERVED, 1254 PINCTRL_GRP_GPIO0_44, 1255 PINCTRL_GRP_CAN1_11, 1256 PINCTRL_GRP_I2C1_11, 1257 PINCTRL_GRP_SWDT1_7_CLK, 1258 PINCTRL_GRP_SPI1_3, 1259 PINCTRL_GRP_TTC1_5_CLK, 1260 PINCTRL_GRP_UART1_11, 1261 PINCTRL_GRP_RESERVED, 1262 PINCTRL_GRP_SDIO0_4BIT_1_0, 1263 PINCTRL_GRP_SDIO0_1BIT_1_3, 1264 END_OF_GROUPS, 1265 }), 1266 }, 1267 [PINCTRL_PIN_45] = { 1268 .groups = &((uint16_t []) { 1269 PINCTRL_GRP_ETHERNET1_0, 1270 PINCTRL_GRP_RESERVED, 1271 PINCTRL_GRP_SDIO0_1, 1272 PINCTRL_GRP_SDIO1_0_CD, 1273 PINCTRL_GRP_RESERVED, 1274 PINCTRL_GRP_GPIO0_45, 1275 PINCTRL_GRP_CAN1_11, 1276 PINCTRL_GRP_I2C1_11, 1277 PINCTRL_GRP_SWDT1_7_RST, 1278 PINCTRL_GRP_SPI1_3_SS2, 1279 PINCTRL_GRP_TTC1_5_WAV, 1280 PINCTRL_GRP_UART1_11, 1281 PINCTRL_GRP_RESERVED, 1282 PINCTRL_GRP_SDIO0_4BIT_1_1, 1283 PINCTRL_GRP_SDIO0_1BIT_1_4, 1284 END_OF_GROUPS, 1285 }), 1286 }, 1287 [PINCTRL_PIN_46] = { 1288 .groups = &((uint16_t []) { 1289 PINCTRL_GRP_ETHERNET1_0, 1290 PINCTRL_GRP_RESERVED, 1291 PINCTRL_GRP_SDIO0_1, 1292 PINCTRL_GRP_SDIO1_0, 1293 PINCTRL_GRP_RESERVED, 1294 PINCTRL_GRP_GPIO0_46, 1295 PINCTRL_GRP_CAN0_11, 1296 PINCTRL_GRP_I2C0_11, 1297 PINCTRL_GRP_SWDT0_7_CLK, 1298 PINCTRL_GRP_SPI1_3_SS1, 1299 PINCTRL_GRP_TTC0_5_CLK, 1300 PINCTRL_GRP_UART0_11, 1301 PINCTRL_GRP_RESERVED, 1302 PINCTRL_GRP_SDIO0_4BIT_1_1, 1303 PINCTRL_GRP_SDIO0_1BIT_1_5, 1304 PINCTRL_GRP_SDIO1_4BIT_0_1, 1305 PINCTRL_GRP_SDIO1_1BIT_0_4, 1306 END_OF_GROUPS, 1307 }), 1308 }, 1309 [PINCTRL_PIN_47] = { 1310 .groups = &((uint16_t []) { 1311 PINCTRL_GRP_ETHERNET1_0, 1312 PINCTRL_GRP_RESERVED, 1313 PINCTRL_GRP_SDIO0_1, 1314 PINCTRL_GRP_SDIO1_0, 1315 PINCTRL_GRP_RESERVED, 1316 PINCTRL_GRP_GPIO0_47, 1317 PINCTRL_GRP_CAN0_11, 1318 PINCTRL_GRP_I2C0_11, 1319 PINCTRL_GRP_SWDT0_7_RST, 1320 PINCTRL_GRP_SPI1_3_SS0, 1321 PINCTRL_GRP_TTC0_5_WAV, 1322 PINCTRL_GRP_UART0_11, 1323 PINCTRL_GRP_RESERVED, 1324 PINCTRL_GRP_SDIO0_4BIT_1_1, 1325 PINCTRL_GRP_SDIO0_1BIT_1_6, 1326 PINCTRL_GRP_SDIO1_4BIT_0_1, 1327 PINCTRL_GRP_SDIO1_1BIT_0_5, 1328 END_OF_GROUPS, 1329 }), 1330 }, 1331 [PINCTRL_PIN_48] = { 1332 .groups = &((uint16_t []) { 1333 PINCTRL_GRP_ETHERNET1_0, 1334 PINCTRL_GRP_RESERVED, 1335 PINCTRL_GRP_SDIO0_1, 1336 PINCTRL_GRP_SDIO1_0, 1337 PINCTRL_GRP_RESERVED, 1338 PINCTRL_GRP_GPIO0_48, 1339 PINCTRL_GRP_CAN1_12, 1340 PINCTRL_GRP_I2C1_12, 1341 PINCTRL_GRP_SWDT1_8_CLK, 1342 PINCTRL_GRP_SPI1_3, 1343 PINCTRL_GRP_TTC3_6_CLK, 1344 PINCTRL_GRP_UART1_12, 1345 PINCTRL_GRP_RESERVED, 1346 PINCTRL_GRP_SDIO0_4BIT_1_1, 1347 PINCTRL_GRP_SDIO0_1BIT_1_7, 1348 PINCTRL_GRP_SDIO1_4BIT_0_1, 1349 PINCTRL_GRP_SDIO1_1BIT_0_6, 1350 END_OF_GROUPS, 1351 }), 1352 }, 1353 [PINCTRL_PIN_49] = { 1354 .groups = &((uint16_t []) { 1355 PINCTRL_GRP_ETHERNET1_0, 1356 PINCTRL_GRP_RESERVED, 1357 PINCTRL_GRP_SDIO0_1_PC, 1358 PINCTRL_GRP_SDIO1_0, 1359 PINCTRL_GRP_RESERVED, 1360 PINCTRL_GRP_GPIO0_49, 1361 PINCTRL_GRP_CAN1_12, 1362 PINCTRL_GRP_I2C1_12, 1363 PINCTRL_GRP_SWDT1_8_RST, 1364 PINCTRL_GRP_SPI1_3, 1365 PINCTRL_GRP_TTC3_6_WAV, 1366 PINCTRL_GRP_UART1_12, 1367 PINCTRL_GRP_RESERVED, 1368 PINCTRL_GRP_SDIO1_4BIT_0_1, 1369 PINCTRL_GRP_SDIO1_1BIT_0_7, 1370 END_OF_GROUPS, 1371 }), 1372 }, 1373 [PINCTRL_PIN_50] = { 1374 .groups = &((uint16_t []) { 1375 PINCTRL_GRP_GEMTSU0_1, 1376 PINCTRL_GRP_RESERVED, 1377 PINCTRL_GRP_SDIO0_1_WP, 1378 PINCTRL_GRP_SDIO1_0, 1379 PINCTRL_GRP_RESERVED, 1380 PINCTRL_GRP_GPIO0_50, 1381 PINCTRL_GRP_CAN0_12, 1382 PINCTRL_GRP_I2C0_12, 1383 PINCTRL_GRP_SWDT0_8_CLK, 1384 PINCTRL_GRP_MDIO1_0, 1385 PINCTRL_GRP_TTC2_6_CLK, 1386 PINCTRL_GRP_UART0_12, 1387 PINCTRL_GRP_RESERVED, 1388 PINCTRL_GRP_SDIO1_4BIT_0_0, 1389 PINCTRL_GRP_SDIO1_4BIT_0_1, 1390 PINCTRL_GRP_SDIO1_1BIT_0_0, 1391 PINCTRL_GRP_SDIO1_1BIT_0_1, 1392 PINCTRL_GRP_SDIO1_1BIT_0_2, 1393 PINCTRL_GRP_SDIO1_1BIT_0_3, 1394 PINCTRL_GRP_SDIO1_1BIT_0_4, 1395 PINCTRL_GRP_SDIO1_1BIT_0_5, 1396 PINCTRL_GRP_SDIO1_1BIT_0_6, 1397 PINCTRL_GRP_SDIO1_1BIT_0_7, 1398 END_OF_GROUPS, 1399 }), 1400 }, 1401 [PINCTRL_PIN_51] = { 1402 .groups = &((uint16_t []) { 1403 PINCTRL_GRP_GEMTSU0_2, 1404 PINCTRL_GRP_RESERVED, 1405 PINCTRL_GRP_RESERVED, 1406 PINCTRL_GRP_SDIO1_0, 1407 PINCTRL_GRP_RESERVED, 1408 PINCTRL_GRP_GPIO0_51, 1409 PINCTRL_GRP_CAN0_12, 1410 PINCTRL_GRP_I2C0_12, 1411 PINCTRL_GRP_SWDT0_8_RST, 1412 PINCTRL_GRP_MDIO1_0, 1413 PINCTRL_GRP_TTC2_6_WAV, 1414 PINCTRL_GRP_UART0_12, 1415 PINCTRL_GRP_RESERVED, 1416 PINCTRL_GRP_SDIO1_4BIT_0_0, 1417 PINCTRL_GRP_SDIO1_4BIT_0_1, 1418 PINCTRL_GRP_SDIO1_1BIT_0_0, 1419 PINCTRL_GRP_SDIO1_1BIT_0_1, 1420 PINCTRL_GRP_SDIO1_1BIT_0_2, 1421 PINCTRL_GRP_SDIO1_1BIT_0_3, 1422 PINCTRL_GRP_SDIO1_1BIT_0_4, 1423 PINCTRL_GRP_SDIO1_1BIT_0_5, 1424 PINCTRL_GRP_SDIO1_1BIT_0_6, 1425 PINCTRL_GRP_SDIO1_1BIT_0_7, 1426 END_OF_GROUPS, 1427 }), 1428 }, 1429 [PINCTRL_PIN_52] = { 1430 .groups = &((uint16_t []) { 1431 PINCTRL_GRP_ETHERNET2_0, 1432 PINCTRL_GRP_USB0_0, 1433 PINCTRL_GRP_RESERVED, 1434 PINCTRL_GRP_RESERVED, 1435 PINCTRL_GRP_RESERVED, 1436 PINCTRL_GRP_GPIO0_52, 1437 PINCTRL_GRP_CAN1_13, 1438 PINCTRL_GRP_I2C1_13, 1439 PINCTRL_GRP_PJTAG0_4, 1440 PINCTRL_GRP_SPI0_4, 1441 PINCTRL_GRP_TTC1_6_CLK, 1442 PINCTRL_GRP_UART1_13, 1443 PINCTRL_GRP_TRACE0_2_CLK, 1444 END_OF_GROUPS, 1445 }), 1446 }, 1447 [PINCTRL_PIN_53] = { 1448 .groups = &((uint16_t []) { 1449 PINCTRL_GRP_ETHERNET2_0, 1450 PINCTRL_GRP_USB0_0, 1451 PINCTRL_GRP_RESERVED, 1452 PINCTRL_GRP_RESERVED, 1453 PINCTRL_GRP_RESERVED, 1454 PINCTRL_GRP_GPIO0_53, 1455 PINCTRL_GRP_CAN1_13, 1456 PINCTRL_GRP_I2C1_13, 1457 PINCTRL_GRP_PJTAG0_4, 1458 PINCTRL_GRP_SPI0_4_SS2, 1459 PINCTRL_GRP_TTC1_6_WAV, 1460 PINCTRL_GRP_UART1_13, 1461 PINCTRL_GRP_TRACE0_2_CLK, 1462 END_OF_GROUPS, 1463 }), 1464 }, 1465 [PINCTRL_PIN_54] = { 1466 .groups = &((uint16_t []) { 1467 PINCTRL_GRP_ETHERNET2_0, 1468 PINCTRL_GRP_USB0_0, 1469 PINCTRL_GRP_RESERVED, 1470 PINCTRL_GRP_RESERVED, 1471 PINCTRL_GRP_RESERVED, 1472 PINCTRL_GRP_GPIO0_54, 1473 PINCTRL_GRP_CAN0_13, 1474 PINCTRL_GRP_I2C0_13, 1475 PINCTRL_GRP_PJTAG0_4, 1476 PINCTRL_GRP_SPI0_4_SS1, 1477 PINCTRL_GRP_TTC0_6_CLK, 1478 PINCTRL_GRP_UART0_13, 1479 PINCTRL_GRP_TRACE0_2, 1480 END_OF_GROUPS, 1481 }), 1482 }, 1483 [PINCTRL_PIN_55] = { 1484 .groups = &((uint16_t []) { 1485 PINCTRL_GRP_ETHERNET2_0, 1486 PINCTRL_GRP_USB0_0, 1487 PINCTRL_GRP_RESERVED, 1488 PINCTRL_GRP_RESERVED, 1489 PINCTRL_GRP_RESERVED, 1490 PINCTRL_GRP_GPIO0_55, 1491 PINCTRL_GRP_CAN0_13, 1492 PINCTRL_GRP_I2C0_13, 1493 PINCTRL_GRP_PJTAG0_4, 1494 PINCTRL_GRP_SPI0_4_SS0, 1495 PINCTRL_GRP_TTC0_6_WAV, 1496 PINCTRL_GRP_UART0_13, 1497 PINCTRL_GRP_TRACE0_2, 1498 END_OF_GROUPS, 1499 }), 1500 }, 1501 [PINCTRL_PIN_56] = { 1502 .groups = &((uint16_t []) { 1503 PINCTRL_GRP_ETHERNET2_0, 1504 PINCTRL_GRP_USB0_0, 1505 PINCTRL_GRP_RESERVED, 1506 PINCTRL_GRP_RESERVED, 1507 PINCTRL_GRP_RESERVED, 1508 PINCTRL_GRP_GPIO0_56, 1509 PINCTRL_GRP_CAN1_14, 1510 PINCTRL_GRP_I2C1_14, 1511 PINCTRL_GRP_SWDT1_9_CLK, 1512 PINCTRL_GRP_SPI0_4, 1513 PINCTRL_GRP_TTC3_7_CLK, 1514 PINCTRL_GRP_UART1_14, 1515 PINCTRL_GRP_TRACE0_2, 1516 END_OF_GROUPS, 1517 }), 1518 }, 1519 [PINCTRL_PIN_57] = { 1520 .groups = &((uint16_t []) { 1521 PINCTRL_GRP_ETHERNET2_0, 1522 PINCTRL_GRP_USB0_0, 1523 PINCTRL_GRP_RESERVED, 1524 PINCTRL_GRP_RESERVED, 1525 PINCTRL_GRP_RESERVED, 1526 PINCTRL_GRP_GPIO0_57, 1527 PINCTRL_GRP_CAN1_14, 1528 PINCTRL_GRP_I2C1_14, 1529 PINCTRL_GRP_SWDT1_9_RST, 1530 PINCTRL_GRP_SPI0_4, 1531 PINCTRL_GRP_TTC3_7_WAV, 1532 PINCTRL_GRP_UART1_14, 1533 PINCTRL_GRP_TRACE0_2, 1534 END_OF_GROUPS, 1535 }), 1536 }, 1537 [PINCTRL_PIN_58] = { 1538 .groups = &((uint16_t []) { 1539 PINCTRL_GRP_ETHERNET2_0, 1540 PINCTRL_GRP_USB0_0, 1541 PINCTRL_GRP_RESERVED, 1542 PINCTRL_GRP_RESERVED, 1543 PINCTRL_GRP_RESERVED, 1544 PINCTRL_GRP_GPIO0_58, 1545 PINCTRL_GRP_CAN0_14, 1546 PINCTRL_GRP_I2C0_14, 1547 PINCTRL_GRP_PJTAG0_5, 1548 PINCTRL_GRP_SPI1_4, 1549 PINCTRL_GRP_TTC2_7_CLK, 1550 PINCTRL_GRP_UART0_14, 1551 PINCTRL_GRP_TRACE0_2, 1552 END_OF_GROUPS, 1553 }), 1554 }, 1555 [PINCTRL_PIN_59] = { 1556 .groups = &((uint16_t []) { 1557 PINCTRL_GRP_ETHERNET2_0, 1558 PINCTRL_GRP_USB0_0, 1559 PINCTRL_GRP_RESERVED, 1560 PINCTRL_GRP_RESERVED, 1561 PINCTRL_GRP_RESERVED, 1562 PINCTRL_GRP_GPIO0_59, 1563 PINCTRL_GRP_CAN0_14, 1564 PINCTRL_GRP_I2C0_14, 1565 PINCTRL_GRP_PJTAG0_5, 1566 PINCTRL_GRP_SPI1_4_SS2, 1567 PINCTRL_GRP_TTC2_7_WAV, 1568 PINCTRL_GRP_UART0_14, 1569 PINCTRL_GRP_TRACE0_2, 1570 END_OF_GROUPS, 1571 }), 1572 }, 1573 [PINCTRL_PIN_60] = { 1574 .groups = &((uint16_t []) { 1575 PINCTRL_GRP_ETHERNET2_0, 1576 PINCTRL_GRP_USB0_0, 1577 PINCTRL_GRP_RESERVED, 1578 PINCTRL_GRP_RESERVED, 1579 PINCTRL_GRP_RESERVED, 1580 PINCTRL_GRP_GPIO0_60, 1581 PINCTRL_GRP_CAN1_15, 1582 PINCTRL_GRP_I2C1_15, 1583 PINCTRL_GRP_PJTAG0_5, 1584 PINCTRL_GRP_SPI1_4_SS1, 1585 PINCTRL_GRP_TTC1_7_CLK, 1586 PINCTRL_GRP_UART1_15, 1587 PINCTRL_GRP_TRACE0_2, 1588 END_OF_GROUPS, 1589 }), 1590 }, 1591 [PINCTRL_PIN_61] = { 1592 .groups = &((uint16_t []) { 1593 PINCTRL_GRP_ETHERNET2_0, 1594 PINCTRL_GRP_USB0_0, 1595 PINCTRL_GRP_RESERVED, 1596 PINCTRL_GRP_RESERVED, 1597 PINCTRL_GRP_RESERVED, 1598 PINCTRL_GRP_GPIO0_61, 1599 PINCTRL_GRP_CAN1_15, 1600 PINCTRL_GRP_I2C1_15, 1601 PINCTRL_GRP_PJTAG0_5, 1602 PINCTRL_GRP_SPI1_4_SS0, 1603 PINCTRL_GRP_TTC1_7_WAV, 1604 PINCTRL_GRP_UART1_15, 1605 PINCTRL_GRP_TRACE0_2, 1606 END_OF_GROUPS, 1607 }), 1608 }, 1609 [PINCTRL_PIN_62] = { 1610 .groups = &((uint16_t []) { 1611 PINCTRL_GRP_ETHERNET2_0, 1612 PINCTRL_GRP_USB0_0, 1613 PINCTRL_GRP_RESERVED, 1614 PINCTRL_GRP_RESERVED, 1615 PINCTRL_GRP_RESERVED, 1616 PINCTRL_GRP_GPIO0_62, 1617 PINCTRL_GRP_CAN0_15, 1618 PINCTRL_GRP_I2C0_15, 1619 PINCTRL_GRP_SWDT0_9_CLK, 1620 PINCTRL_GRP_SPI1_4, 1621 PINCTRL_GRP_TTC0_7_CLK, 1622 PINCTRL_GRP_UART0_15, 1623 PINCTRL_GRP_TRACE0_2, 1624 END_OF_GROUPS, 1625 }), 1626 }, 1627 [PINCTRL_PIN_63] = { 1628 .groups = &((uint16_t []) { 1629 PINCTRL_GRP_ETHERNET2_0, 1630 PINCTRL_GRP_USB0_0, 1631 PINCTRL_GRP_RESERVED, 1632 PINCTRL_GRP_RESERVED, 1633 PINCTRL_GRP_RESERVED, 1634 PINCTRL_GRP_GPIO0_63, 1635 PINCTRL_GRP_CAN0_15, 1636 PINCTRL_GRP_I2C0_15, 1637 PINCTRL_GRP_SWDT0_9_RST, 1638 PINCTRL_GRP_SPI1_4, 1639 PINCTRL_GRP_TTC0_7_WAV, 1640 PINCTRL_GRP_UART0_15, 1641 PINCTRL_GRP_TRACE0_2, 1642 END_OF_GROUPS, 1643 }), 1644 }, 1645 [PINCTRL_PIN_64] = { 1646 .groups = &((uint16_t []) { 1647 PINCTRL_GRP_ETHERNET3_0, 1648 PINCTRL_GRP_USB1_0, 1649 PINCTRL_GRP_SDIO0_2, 1650 PINCTRL_GRP_RESERVED, 1651 PINCTRL_GRP_RESERVED, 1652 PINCTRL_GRP_GPIO0_64, 1653 PINCTRL_GRP_CAN1_16, 1654 PINCTRL_GRP_I2C1_16, 1655 PINCTRL_GRP_SWDT1_10_CLK, 1656 PINCTRL_GRP_SPI0_5, 1657 PINCTRL_GRP_TTC3_8_CLK, 1658 PINCTRL_GRP_UART1_16, 1659 PINCTRL_GRP_TRACE0_2, 1660 PINCTRL_GRP_SDIO0_4BIT_2_0, 1661 PINCTRL_GRP_SDIO0_4BIT_2_1, 1662 PINCTRL_GRP_SDIO0_1BIT_2_0, 1663 PINCTRL_GRP_SDIO0_1BIT_2_1, 1664 PINCTRL_GRP_SDIO0_1BIT_2_2, 1665 PINCTRL_GRP_SDIO0_1BIT_2_3, 1666 PINCTRL_GRP_SDIO0_1BIT_2_4, 1667 PINCTRL_GRP_SDIO0_1BIT_2_5, 1668 PINCTRL_GRP_SDIO0_1BIT_2_6, 1669 PINCTRL_GRP_SDIO0_1BIT_2_7, 1670 END_OF_GROUPS, 1671 }), 1672 }, 1673 [PINCTRL_PIN_65] = { 1674 .groups = &((uint16_t []) { 1675 PINCTRL_GRP_ETHERNET3_0, 1676 PINCTRL_GRP_USB1_0, 1677 PINCTRL_GRP_SDIO0_2_CD, 1678 PINCTRL_GRP_RESERVED, 1679 PINCTRL_GRP_RESERVED, 1680 PINCTRL_GRP_GPIO0_65, 1681 PINCTRL_GRP_CAN1_16, 1682 PINCTRL_GRP_I2C1_16, 1683 PINCTRL_GRP_SWDT1_10_RST, 1684 PINCTRL_GRP_SPI0_5_SS2, 1685 PINCTRL_GRP_TTC3_8_WAV, 1686 PINCTRL_GRP_UART1_16, 1687 PINCTRL_GRP_TRACE0_2, 1688 END_OF_GROUPS, 1689 }), 1690 }, 1691 [PINCTRL_PIN_66] = { 1692 .groups = &((uint16_t []) { 1693 PINCTRL_GRP_ETHERNET3_0, 1694 PINCTRL_GRP_USB1_0, 1695 PINCTRL_GRP_SDIO0_2, 1696 PINCTRL_GRP_RESERVED, 1697 PINCTRL_GRP_RESERVED, 1698 PINCTRL_GRP_GPIO0_66, 1699 PINCTRL_GRP_CAN0_16, 1700 PINCTRL_GRP_I2C0_16, 1701 PINCTRL_GRP_SWDT0_10_CLK, 1702 PINCTRL_GRP_SPI0_5_SS1, 1703 PINCTRL_GRP_TTC2_8_CLK, 1704 PINCTRL_GRP_UART0_16, 1705 PINCTRL_GRP_TRACE0_2, 1706 PINCTRL_GRP_SDIO0_4BIT_2_0, 1707 PINCTRL_GRP_SDIO0_4BIT_2_1, 1708 PINCTRL_GRP_SDIO0_1BIT_2_0, 1709 PINCTRL_GRP_SDIO0_1BIT_2_1, 1710 PINCTRL_GRP_SDIO0_1BIT_2_2, 1711 PINCTRL_GRP_SDIO0_1BIT_2_3, 1712 PINCTRL_GRP_SDIO0_1BIT_2_4, 1713 PINCTRL_GRP_SDIO0_1BIT_2_5, 1714 PINCTRL_GRP_SDIO0_1BIT_2_6, 1715 PINCTRL_GRP_SDIO0_1BIT_2_7, 1716 END_OF_GROUPS, 1717 }), 1718 }, 1719 [PINCTRL_PIN_67] = { 1720 .groups = &((uint16_t []) { 1721 PINCTRL_GRP_ETHERNET3_0, 1722 PINCTRL_GRP_USB1_0, 1723 PINCTRL_GRP_SDIO0_2, 1724 PINCTRL_GRP_RESERVED, 1725 PINCTRL_GRP_RESERVED, 1726 PINCTRL_GRP_GPIO0_67, 1727 PINCTRL_GRP_CAN0_16, 1728 PINCTRL_GRP_I2C0_16, 1729 PINCTRL_GRP_SWDT0_10_RST, 1730 PINCTRL_GRP_SPI0_5_SS0, 1731 PINCTRL_GRP_TTC2_8_WAV, 1732 PINCTRL_GRP_UART0_16, 1733 PINCTRL_GRP_TRACE0_2, 1734 PINCTRL_GRP_SDIO0_4BIT_2_0, 1735 PINCTRL_GRP_SDIO0_1BIT_2_0, 1736 END_OF_GROUPS, 1737 }), 1738 }, 1739 [PINCTRL_PIN_68] = { 1740 .groups = &((uint16_t []) { 1741 PINCTRL_GRP_ETHERNET3_0, 1742 PINCTRL_GRP_USB1_0, 1743 PINCTRL_GRP_SDIO0_2, 1744 PINCTRL_GRP_RESERVED, 1745 PINCTRL_GRP_RESERVED, 1746 PINCTRL_GRP_GPIO0_68, 1747 PINCTRL_GRP_CAN1_17, 1748 PINCTRL_GRP_I2C1_17, 1749 PINCTRL_GRP_SWDT1_11_CLK, 1750 PINCTRL_GRP_SPI0_5, 1751 PINCTRL_GRP_TTC1_8_CLK, 1752 PINCTRL_GRP_UART1_17, 1753 PINCTRL_GRP_TRACE0_2, 1754 PINCTRL_GRP_SDIO0_4BIT_2_0, 1755 PINCTRL_GRP_SDIO0_1BIT_2_1, 1756 END_OF_GROUPS, 1757 }), 1758 }, 1759 [PINCTRL_PIN_69] = { 1760 .groups = &((uint16_t []) { 1761 PINCTRL_GRP_ETHERNET3_0, 1762 PINCTRL_GRP_USB1_0, 1763 PINCTRL_GRP_SDIO0_2, 1764 PINCTRL_GRP_SDIO1_1_WP, 1765 PINCTRL_GRP_RESERVED, 1766 PINCTRL_GRP_GPIO0_69, 1767 PINCTRL_GRP_CAN1_17, 1768 PINCTRL_GRP_I2C1_17, 1769 PINCTRL_GRP_SWDT1_11_RST, 1770 PINCTRL_GRP_SPI0_5, 1771 PINCTRL_GRP_TTC1_8_WAV, 1772 PINCTRL_GRP_UART1_17, 1773 PINCTRL_GRP_TRACE0_2, 1774 PINCTRL_GRP_SDIO0_4BIT_2_0, 1775 PINCTRL_GRP_SDIO0_1BIT_2_2, 1776 END_OF_GROUPS, 1777 }), 1778 }, 1779 [PINCTRL_PIN_70] = { 1780 .groups = &((uint16_t []) { 1781 PINCTRL_GRP_ETHERNET3_0, 1782 PINCTRL_GRP_USB1_0, 1783 PINCTRL_GRP_SDIO0_2, 1784 PINCTRL_GRP_SDIO1_1_PC, 1785 PINCTRL_GRP_RESERVED, 1786 PINCTRL_GRP_GPIO0_70, 1787 PINCTRL_GRP_CAN0_17, 1788 PINCTRL_GRP_I2C0_17, 1789 PINCTRL_GRP_SWDT0_11_CLK, 1790 PINCTRL_GRP_SPI1_5, 1791 PINCTRL_GRP_TTC0_8_CLK, 1792 PINCTRL_GRP_UART0_17, 1793 PINCTRL_GRP_RESERVED, 1794 PINCTRL_GRP_SDIO0_4BIT_2_0, 1795 PINCTRL_GRP_SDIO0_1BIT_2_3, 1796 END_OF_GROUPS, 1797 }), 1798 }, 1799 [PINCTRL_PIN_71] = { 1800 .groups = &((uint16_t []) { 1801 PINCTRL_GRP_ETHERNET3_0, 1802 PINCTRL_GRP_USB1_0, 1803 PINCTRL_GRP_SDIO0_2, 1804 PINCTRL_GRP_SDIO1_4BIT_1_0, 1805 PINCTRL_GRP_RESERVED, 1806 PINCTRL_GRP_GPIO0_71, 1807 PINCTRL_GRP_CAN0_17, 1808 PINCTRL_GRP_I2C0_17, 1809 PINCTRL_GRP_SWDT0_11_RST, 1810 PINCTRL_GRP_SPI1_5_SS2, 1811 PINCTRL_GRP_TTC0_8_WAV, 1812 PINCTRL_GRP_UART0_17, 1813 PINCTRL_GRP_RESERVED, 1814 PINCTRL_GRP_SDIO0_2, 1815 PINCTRL_GRP_SDIO0_4BIT_2_1, 1816 PINCTRL_GRP_SDIO0_1BIT_2_4, 1817 PINCTRL_GRP_SDIO1_1BIT_1_0, 1818 END_OF_GROUPS, 1819 }), 1820 }, 1821 [PINCTRL_PIN_72] = { 1822 .groups = &((uint16_t []) { 1823 PINCTRL_GRP_ETHERNET3_0, 1824 PINCTRL_GRP_USB1_0, 1825 PINCTRL_GRP_SDIO0_2, 1826 PINCTRL_GRP_SDIO1_4BIT_1_0, 1827 PINCTRL_GRP_RESERVED, 1828 PINCTRL_GRP_GPIO0_72, 1829 PINCTRL_GRP_CAN1_18, 1830 PINCTRL_GRP_I2C1_18, 1831 PINCTRL_GRP_SWDT1_12_CLK, 1832 PINCTRL_GRP_SPI1_5_SS1, 1833 PINCTRL_GRP_RESERVED, 1834 PINCTRL_GRP_UART1_18, 1835 PINCTRL_GRP_RESERVED, 1836 PINCTRL_GRP_SDIO0_4BIT_2_1, 1837 PINCTRL_GRP_SDIO0_1BIT_2_5, 1838 PINCTRL_GRP_SDIO1_1BIT_1_1, 1839 END_OF_GROUPS, 1840 }), 1841 }, 1842 [PINCTRL_PIN_73] = { 1843 .groups = &((uint16_t []) { 1844 PINCTRL_GRP_ETHERNET3_0, 1845 PINCTRL_GRP_USB1_0, 1846 PINCTRL_GRP_SDIO0_2, 1847 PINCTRL_GRP_SDIO1_4BIT_1_0, 1848 PINCTRL_GRP_RESERVED, 1849 PINCTRL_GRP_GPIO0_73, 1850 PINCTRL_GRP_CAN1_18, 1851 PINCTRL_GRP_I2C1_18, 1852 PINCTRL_GRP_SWDT1_12_RST, 1853 PINCTRL_GRP_SPI1_5_SS0, 1854 PINCTRL_GRP_RESERVED, 1855 PINCTRL_GRP_UART1_18, 1856 PINCTRL_GRP_RESERVED, 1857 PINCTRL_GRP_SDIO0_4BIT_2_1, 1858 PINCTRL_GRP_SDIO0_1BIT_2_6, 1859 PINCTRL_GRP_SDIO1_1BIT_1_2, 1860 END_OF_GROUPS, 1861 }), 1862 }, 1863 [PINCTRL_PIN_74] = { 1864 .groups = &((uint16_t []) { 1865 PINCTRL_GRP_ETHERNET3_0, 1866 PINCTRL_GRP_USB1_0, 1867 PINCTRL_GRP_SDIO0_2, 1868 PINCTRL_GRP_SDIO1_4BIT_1_0, 1869 PINCTRL_GRP_RESERVED, 1870 PINCTRL_GRP_GPIO0_74, 1871 PINCTRL_GRP_CAN0_18, 1872 PINCTRL_GRP_I2C0_18, 1873 PINCTRL_GRP_SWDT0_12_CLK, 1874 PINCTRL_GRP_SPI1_5, 1875 PINCTRL_GRP_RESERVED, 1876 PINCTRL_GRP_UART0_18, 1877 PINCTRL_GRP_RESERVED, 1878 PINCTRL_GRP_SDIO0_4BIT_2_1, 1879 PINCTRL_GRP_SDIO0_1BIT_2_7, 1880 PINCTRL_GRP_SDIO1_1BIT_1_3, 1881 END_OF_GROUPS, 1882 }), 1883 }, 1884 [PINCTRL_PIN_75] = { 1885 .groups = &((uint16_t []) { 1886 PINCTRL_GRP_ETHERNET3_0, 1887 PINCTRL_GRP_USB1_0, 1888 PINCTRL_GRP_SDIO0_2_PC, 1889 PINCTRL_GRP_SDIO1_4BIT_1_0, 1890 PINCTRL_GRP_RESERVED, 1891 PINCTRL_GRP_GPIO0_75, 1892 PINCTRL_GRP_CAN0_18, 1893 PINCTRL_GRP_I2C0_18, 1894 PINCTRL_GRP_SWDT0_12_RST, 1895 PINCTRL_GRP_SPI1_5, 1896 PINCTRL_GRP_RESERVED, 1897 PINCTRL_GRP_UART0_18, 1898 PINCTRL_GRP_RESERVED, 1899 PINCTRL_GRP_SDIO1_1BIT_1_0, 1900 PINCTRL_GRP_SDIO1_1BIT_1_1, 1901 PINCTRL_GRP_SDIO1_1BIT_1_2, 1902 PINCTRL_GRP_SDIO1_1BIT_1_3, 1903 END_OF_GROUPS, 1904 }), 1905 }, 1906 [PINCTRL_PIN_76] = { 1907 .groups = &((uint16_t []) { 1908 PINCTRL_GRP_RESERVED, 1909 PINCTRL_GRP_RESERVED, 1910 PINCTRL_GRP_SDIO0_2_WP, 1911 PINCTRL_GRP_SDIO1_4BIT_1_0, 1912 PINCTRL_GRP_RESERVED, 1913 PINCTRL_GRP_GPIO0_76, 1914 PINCTRL_GRP_CAN1_19, 1915 PINCTRL_GRP_I2C1_19, 1916 PINCTRL_GRP_MDIO0_0, 1917 PINCTRL_GRP_MDIO1_1, 1918 PINCTRL_GRP_MDIO2_0, 1919 PINCTRL_GRP_MDIO3_0, 1920 PINCTRL_GRP_RESERVED, 1921 PINCTRL_GRP_SDIO1_1BIT_1_0, 1922 PINCTRL_GRP_SDIO1_1BIT_1_1, 1923 PINCTRL_GRP_SDIO1_1BIT_1_2, 1924 PINCTRL_GRP_SDIO1_1BIT_1_3, 1925 END_OF_GROUPS, 1926 }), 1927 }, 1928 [PINCTRL_PIN_77] = { 1929 .groups = &((uint16_t []) { 1930 PINCTRL_GRP_RESERVED, 1931 PINCTRL_GRP_RESERVED, 1932 PINCTRL_GRP_RESERVED, 1933 PINCTRL_GRP_SDIO1_1_CD, 1934 PINCTRL_GRP_RESERVED, 1935 PINCTRL_GRP_GPIO0_77, 1936 PINCTRL_GRP_CAN1_19, 1937 PINCTRL_GRP_I2C1_19, 1938 PINCTRL_GRP_MDIO0_0, 1939 PINCTRL_GRP_MDIO1_1, 1940 PINCTRL_GRP_MDIO2_0, 1941 PINCTRL_GRP_MDIO3_0, 1942 PINCTRL_GRP_RESERVED, 1943 END_OF_GROUPS, 1944 }), 1945 }, 1946 }; 1947 1948 /** 1949 * pm_api_pinctrl_get_num_pins() - PM call to request number of pins. 1950 * @npins: Number of pins. 1951 * 1952 * This function is used by master to get number of pins. 1953 * 1954 * Return: Returns success. 1955 * 1956 */ 1957 enum pm_ret_status pm_api_pinctrl_get_num_pins(uint32_t *npins) 1958 { 1959 *npins = MAX_PIN; 1960 1961 return PM_RET_SUCCESS; 1962 } 1963 1964 /** 1965 * pm_api_pinctrl_get_num_functions() - PM call to request number of functions. 1966 * @nfuncs: Number of functions. 1967 * 1968 * This function is used by master to get number of functions. 1969 * 1970 * Return: Returns success. 1971 * 1972 */ 1973 enum pm_ret_status pm_api_pinctrl_get_num_functions(uint32_t *nfuncs) 1974 { 1975 *nfuncs = MAX_FUNCTION; 1976 1977 return PM_RET_SUCCESS; 1978 } 1979 1980 /** 1981 * pm_api_pinctrl_get_num_func_groups() - PM call to request number of 1982 * function groups. 1983 * @fid: Function Id. 1984 * @ngroups: Number of function groups. 1985 * 1986 * This function is used by master to get number of function groups. 1987 * 1988 * Return: Returns success. 1989 * 1990 */ 1991 enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid, 1992 uint32_t *ngroups) 1993 { 1994 if (fid >= MAX_FUNCTION) { 1995 return PM_RET_ERROR_ARGS; 1996 } 1997 1998 *ngroups = pinctrl_functions[fid].group_size; 1999 2000 return PM_RET_SUCCESS; 2001 } 2002 2003 /** 2004 * pm_api_pinctrl_get_function_name() - PM call to request a function name. 2005 * @fid: Function ID. 2006 * @name: Name of function (max 16 bytes). 2007 * 2008 * This function is used by master to get name of function specified 2009 * by given function ID. 2010 * 2011 */ 2012 void pm_api_pinctrl_get_function_name(uint32_t fid, char *name) 2013 { 2014 if (fid >= MAX_FUNCTION) { 2015 memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); 2016 } else { 2017 memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); 2018 } 2019 } 2020 2021 /** 2022 * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function 2023 * groups of function Id. 2024 * @fid: Function ID. 2025 * @index: Index of next function groups. 2026 * @groups: Function groups. 2027 * 2028 * This function is used by master to get function groups specified 2029 * by given function Id. This API will return 6 function groups with 2030 * a single response. To get other function groups, master should call 2031 * same API in loop with new function groups index till error is returned. 2032 * 2033 * E.g First call should have index 0 which will return function groups 2034 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2035 * function groups 6, 7, 8, 9, 10 and 11 and so on. 2036 * 2037 * Return: Returns status, either success or error+reason. 2038 * 2039 */ 2040 enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid, 2041 uint32_t index, 2042 uint16_t *groups) 2043 { 2044 uint16_t grps; 2045 uint16_t end_of_grp_offset; 2046 uint16_t i; 2047 2048 if (fid >= MAX_FUNCTION) { 2049 return PM_RET_ERROR_ARGS; 2050 } 2051 2052 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2053 2054 grps = pinctrl_functions[fid].group_base; 2055 end_of_grp_offset = grps + pinctrl_functions[fid].group_size; 2056 2057 for (i = 0U; i < NUM_GROUPS_PER_RESP; i++) { 2058 if ((grps + index + i) >= end_of_grp_offset) { 2059 break; 2060 } 2061 groups[i] = (grps + index + i); 2062 } 2063 2064 return PM_RET_SUCCESS; 2065 } 2066 2067 /** 2068 * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin 2069 * groups of pin. 2070 * @pin: Pin. 2071 * @index: Index of next pin groups. 2072 * @groups: pin groups. 2073 * 2074 * This function is used by master to get pin groups specified 2075 * by given pin Id. This API will return 6 pin groups with 2076 * a single response. To get other pin groups, master should call 2077 * same API in loop with new pin groups index till error is returned. 2078 * 2079 * E.g First call should have index 0 which will return pin groups 2080 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2081 * pin groups 6, 7, 8, 9, 10 and 11 and so on. 2082 * 2083 * Return: Returns status, either success or error+reason. 2084 * 2085 */ 2086 enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin, 2087 uint32_t index, 2088 uint16_t *groups) 2089 { 2090 uint32_t i; 2091 uint16_t *grps; 2092 2093 if (pin >= MAX_PIN) { 2094 return PM_RET_ERROR_ARGS; 2095 } 2096 2097 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2098 2099 grps = *zynqmp_pin_groups[pin].groups; 2100 if (grps == NULL) { 2101 return PM_RET_SUCCESS; 2102 } 2103 2104 /* Skip groups till index */ 2105 for (i = 0; i < index; i++) { 2106 if (grps[i] == (uint16_t)END_OF_GROUPS) { 2107 return PM_RET_SUCCESS; 2108 } 2109 } 2110 2111 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { 2112 groups[i] = grps[index + i]; 2113 if (groups[i] == (uint16_t)END_OF_GROUPS) { 2114 break; 2115 } 2116 } 2117 2118 return PM_RET_SUCCESS; 2119 } 2120