1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <plat/common/platform.h> 15 16 #include "pm_api_pinctrl.h" 17 #include "pm_api_sys.h" 18 #include "pm_client.h" 19 #include "pm_common.h" 20 #include "pm_ipi.h" 21 22 #define PINCTRL_FUNCTION_MASK U(0xFE) 23 #define PINCTRL_VOLTAGE_STATUS_MASK U(0x01) 24 #define NFUNCS_PER_PIN U(13) 25 #define PINCTRL_NUM_MIOS U(78) 26 #define MAX_PIN_PER_REG U(26) 27 #define PINCTRL_BANK_ADDR_STEP U(28) 28 29 #define PINCTRL_DRVSTRN0_REG_OFFSET U(0) 30 #define PINCTRL_DRVSTRN1_REG_OFFSET U(4) 31 #define PINCTRL_SCHCMOS_REG_OFFSET U(8) 32 #define PINCTRL_PULLCTRL_REG_OFFSET U(12) 33 #define PINCTRL_PULLSTAT_REG_OFFSET U(16) 34 #define PINCTRL_SLEWCTRL_REG_OFFSET U(20) 35 #define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24) 36 37 #define IOU_SLCR_BANK1_CTRL5 U(0XFF180164) 38 39 #define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \ 40 ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \ 41 ((miopin) / MAX_PIN_PER_REG) + (reg)) 42 43 #define PINCTRL_PIN_OFFSET(_miopin) \ 44 ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG))) 45 46 #define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \ 47 (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1) 48 49 static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = { 50 0x02, 0x04, 0x08, 0x10, 0x18, 51 0x00, 0x20, 0x40, 0x60, 0x80, 52 0xA0, 0xC0, 0xE0 53 }; 54 55 struct pinctrl_function { 56 char name[FUNCTION_NAME_LEN]; 57 uint16_t (*groups)[]; 58 uint8_t regval; 59 }; 60 61 /* Max groups for one pin */ 62 #define MAX_PIN_GROUPS U(13) 63 64 struct zynqmp_pin_group { 65 uint16_t (*groups)[]; 66 }; 67 68 static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { 69 [PINCTRL_FUNC_CAN0] = { 70 .name = "can0", 71 .regval = 0x20, 72 .groups = &((uint16_t []) { 73 PINCTRL_GRP_CAN0_0, 74 PINCTRL_GRP_CAN0_1, 75 PINCTRL_GRP_CAN0_2, 76 PINCTRL_GRP_CAN0_3, 77 PINCTRL_GRP_CAN0_4, 78 PINCTRL_GRP_CAN0_5, 79 PINCTRL_GRP_CAN0_6, 80 PINCTRL_GRP_CAN0_7, 81 PINCTRL_GRP_CAN0_8, 82 PINCTRL_GRP_CAN0_9, 83 PINCTRL_GRP_CAN0_10, 84 PINCTRL_GRP_CAN0_11, 85 PINCTRL_GRP_CAN0_12, 86 PINCTRL_GRP_CAN0_13, 87 PINCTRL_GRP_CAN0_14, 88 PINCTRL_GRP_CAN0_15, 89 PINCTRL_GRP_CAN0_16, 90 PINCTRL_GRP_CAN0_17, 91 PINCTRL_GRP_CAN0_18, 92 END_OF_GROUPS, 93 }), 94 }, 95 [PINCTRL_FUNC_CAN1] = { 96 .name = "can1", 97 .regval = 0x20, 98 .groups = &((uint16_t []) { 99 PINCTRL_GRP_CAN1_0, 100 PINCTRL_GRP_CAN1_1, 101 PINCTRL_GRP_CAN1_2, 102 PINCTRL_GRP_CAN1_3, 103 PINCTRL_GRP_CAN1_4, 104 PINCTRL_GRP_CAN1_5, 105 PINCTRL_GRP_CAN1_6, 106 PINCTRL_GRP_CAN1_7, 107 PINCTRL_GRP_CAN1_8, 108 PINCTRL_GRP_CAN1_9, 109 PINCTRL_GRP_CAN1_10, 110 PINCTRL_GRP_CAN1_11, 111 PINCTRL_GRP_CAN1_12, 112 PINCTRL_GRP_CAN1_13, 113 PINCTRL_GRP_CAN1_14, 114 PINCTRL_GRP_CAN1_15, 115 PINCTRL_GRP_CAN1_16, 116 PINCTRL_GRP_CAN1_17, 117 PINCTRL_GRP_CAN1_18, 118 PINCTRL_GRP_CAN1_19, 119 END_OF_GROUPS, 120 }), 121 }, 122 [PINCTRL_FUNC_ETHERNET0] = { 123 .name = "ethernet0", 124 .regval = 0x02, 125 .groups = &((uint16_t []) { 126 PINCTRL_GRP_ETHERNET0_0, 127 END_OF_GROUPS, 128 }), 129 }, 130 [PINCTRL_FUNC_ETHERNET1] = { 131 .name = "ethernet1", 132 .regval = 0x02, 133 .groups = &((uint16_t []) { 134 PINCTRL_GRP_ETHERNET1_0, 135 END_OF_GROUPS, 136 }), 137 }, 138 [PINCTRL_FUNC_ETHERNET2] = { 139 .name = "ethernet2", 140 .regval = 0x02, 141 .groups = &((uint16_t []) { 142 PINCTRL_GRP_ETHERNET2_0, 143 END_OF_GROUPS, 144 }), 145 }, 146 [PINCTRL_FUNC_ETHERNET3] = { 147 .name = "ethernet3", 148 .regval = 0x02, 149 .groups = &((uint16_t []) { 150 PINCTRL_GRP_ETHERNET3_0, 151 END_OF_GROUPS, 152 }), 153 }, 154 [PINCTRL_FUNC_GEMTSU0] = { 155 .name = "gemtsu0", 156 .regval = 0x02, 157 .groups = &((uint16_t []) { 158 PINCTRL_GRP_GEMTSU0_0, 159 PINCTRL_GRP_GEMTSU0_1, 160 PINCTRL_GRP_GEMTSU0_2, 161 END_OF_GROUPS, 162 }), 163 }, 164 [PINCTRL_FUNC_GPIO0] = { 165 .name = "gpio0", 166 .regval = 0x00, 167 .groups = &((uint16_t []) { 168 PINCTRL_GRP_GPIO0_0, 169 PINCTRL_GRP_GPIO0_1, 170 PINCTRL_GRP_GPIO0_2, 171 PINCTRL_GRP_GPIO0_3, 172 PINCTRL_GRP_GPIO0_4, 173 PINCTRL_GRP_GPIO0_5, 174 PINCTRL_GRP_GPIO0_6, 175 PINCTRL_GRP_GPIO0_7, 176 PINCTRL_GRP_GPIO0_8, 177 PINCTRL_GRP_GPIO0_9, 178 PINCTRL_GRP_GPIO0_10, 179 PINCTRL_GRP_GPIO0_11, 180 PINCTRL_GRP_GPIO0_12, 181 PINCTRL_GRP_GPIO0_13, 182 PINCTRL_GRP_GPIO0_14, 183 PINCTRL_GRP_GPIO0_15, 184 PINCTRL_GRP_GPIO0_16, 185 PINCTRL_GRP_GPIO0_17, 186 PINCTRL_GRP_GPIO0_18, 187 PINCTRL_GRP_GPIO0_19, 188 PINCTRL_GRP_GPIO0_20, 189 PINCTRL_GRP_GPIO0_21, 190 PINCTRL_GRP_GPIO0_22, 191 PINCTRL_GRP_GPIO0_23, 192 PINCTRL_GRP_GPIO0_24, 193 PINCTRL_GRP_GPIO0_25, 194 PINCTRL_GRP_GPIO0_26, 195 PINCTRL_GRP_GPIO0_27, 196 PINCTRL_GRP_GPIO0_28, 197 PINCTRL_GRP_GPIO0_29, 198 PINCTRL_GRP_GPIO0_30, 199 PINCTRL_GRP_GPIO0_31, 200 PINCTRL_GRP_GPIO0_32, 201 PINCTRL_GRP_GPIO0_33, 202 PINCTRL_GRP_GPIO0_34, 203 PINCTRL_GRP_GPIO0_35, 204 PINCTRL_GRP_GPIO0_36, 205 PINCTRL_GRP_GPIO0_37, 206 PINCTRL_GRP_GPIO0_38, 207 PINCTRL_GRP_GPIO0_39, 208 PINCTRL_GRP_GPIO0_40, 209 PINCTRL_GRP_GPIO0_41, 210 PINCTRL_GRP_GPIO0_42, 211 PINCTRL_GRP_GPIO0_43, 212 PINCTRL_GRP_GPIO0_44, 213 PINCTRL_GRP_GPIO0_45, 214 PINCTRL_GRP_GPIO0_46, 215 PINCTRL_GRP_GPIO0_47, 216 PINCTRL_GRP_GPIO0_48, 217 PINCTRL_GRP_GPIO0_49, 218 PINCTRL_GRP_GPIO0_50, 219 PINCTRL_GRP_GPIO0_51, 220 PINCTRL_GRP_GPIO0_52, 221 PINCTRL_GRP_GPIO0_53, 222 PINCTRL_GRP_GPIO0_54, 223 PINCTRL_GRP_GPIO0_55, 224 PINCTRL_GRP_GPIO0_56, 225 PINCTRL_GRP_GPIO0_57, 226 PINCTRL_GRP_GPIO0_58, 227 PINCTRL_GRP_GPIO0_59, 228 PINCTRL_GRP_GPIO0_60, 229 PINCTRL_GRP_GPIO0_61, 230 PINCTRL_GRP_GPIO0_62, 231 PINCTRL_GRP_GPIO0_63, 232 PINCTRL_GRP_GPIO0_64, 233 PINCTRL_GRP_GPIO0_65, 234 PINCTRL_GRP_GPIO0_66, 235 PINCTRL_GRP_GPIO0_67, 236 PINCTRL_GRP_GPIO0_68, 237 PINCTRL_GRP_GPIO0_69, 238 PINCTRL_GRP_GPIO0_70, 239 PINCTRL_GRP_GPIO0_71, 240 PINCTRL_GRP_GPIO0_72, 241 PINCTRL_GRP_GPIO0_73, 242 PINCTRL_GRP_GPIO0_74, 243 PINCTRL_GRP_GPIO0_75, 244 PINCTRL_GRP_GPIO0_76, 245 PINCTRL_GRP_GPIO0_77, 246 END_OF_GROUPS, 247 }), 248 }, 249 [PINCTRL_FUNC_I2C0] = { 250 .name = "i2c0", 251 .regval = 0x40, 252 .groups = &((uint16_t []) { 253 PINCTRL_GRP_I2C0_0, 254 PINCTRL_GRP_I2C0_1, 255 PINCTRL_GRP_I2C0_2, 256 PINCTRL_GRP_I2C0_3, 257 PINCTRL_GRP_I2C0_4, 258 PINCTRL_GRP_I2C0_5, 259 PINCTRL_GRP_I2C0_6, 260 PINCTRL_GRP_I2C0_7, 261 PINCTRL_GRP_I2C0_8, 262 PINCTRL_GRP_I2C0_9, 263 PINCTRL_GRP_I2C0_10, 264 PINCTRL_GRP_I2C0_11, 265 PINCTRL_GRP_I2C0_12, 266 PINCTRL_GRP_I2C0_13, 267 PINCTRL_GRP_I2C0_14, 268 PINCTRL_GRP_I2C0_15, 269 PINCTRL_GRP_I2C0_16, 270 PINCTRL_GRP_I2C0_17, 271 PINCTRL_GRP_I2C0_18, 272 END_OF_GROUPS, 273 }), 274 }, 275 [PINCTRL_FUNC_I2C1] = { 276 .name = "i2c1", 277 .regval = 0x40, 278 .groups = &((uint16_t []) { 279 PINCTRL_GRP_I2C1_0, 280 PINCTRL_GRP_I2C1_1, 281 PINCTRL_GRP_I2C1_2, 282 PINCTRL_GRP_I2C1_3, 283 PINCTRL_GRP_I2C1_4, 284 PINCTRL_GRP_I2C1_5, 285 PINCTRL_GRP_I2C1_6, 286 PINCTRL_GRP_I2C1_7, 287 PINCTRL_GRP_I2C1_8, 288 PINCTRL_GRP_I2C1_9, 289 PINCTRL_GRP_I2C1_10, 290 PINCTRL_GRP_I2C1_11, 291 PINCTRL_GRP_I2C1_12, 292 PINCTRL_GRP_I2C1_13, 293 PINCTRL_GRP_I2C1_14, 294 PINCTRL_GRP_I2C1_15, 295 PINCTRL_GRP_I2C1_16, 296 PINCTRL_GRP_I2C1_17, 297 PINCTRL_GRP_I2C1_18, 298 PINCTRL_GRP_I2C1_19, 299 END_OF_GROUPS, 300 }), 301 }, 302 [PINCTRL_FUNC_MDIO0] = { 303 .name = "mdio0", 304 .regval = 0x60, 305 .groups = &((uint16_t []) { 306 PINCTRL_GRP_MDIO0_0, 307 END_OF_GROUPS, 308 }), 309 }, 310 [PINCTRL_FUNC_MDIO1] = { 311 .name = "mdio1", 312 .regval = 0x80, 313 .groups = &((uint16_t []) { 314 PINCTRL_GRP_MDIO1_0, 315 PINCTRL_GRP_MDIO1_1, 316 END_OF_GROUPS, 317 }), 318 }, 319 [PINCTRL_FUNC_MDIO2] = { 320 .name = "mdio2", 321 .regval = 0xa0, 322 .groups = &((uint16_t []) { 323 PINCTRL_GRP_MDIO2_0, 324 END_OF_GROUPS, 325 }), 326 }, 327 [PINCTRL_FUNC_MDIO3] = { 328 .name = "mdio3", 329 .regval = 0xc0, 330 .groups = &((uint16_t []) { 331 PINCTRL_GRP_MDIO3_0, 332 END_OF_GROUPS, 333 }), 334 }, 335 [PINCTRL_FUNC_QSPI0] = { 336 .name = "qspi0", 337 .regval = 0x02, 338 .groups = &((uint16_t []) { 339 PINCTRL_GRP_QSPI0_0, 340 END_OF_GROUPS, 341 }), 342 }, 343 [PINCTRL_FUNC_QSPI_FBCLK] = { 344 .name = "qspi_fbclk", 345 .regval = 0x02, 346 .groups = &((uint16_t []) { 347 PINCTRL_GRP_QSPI_FBCLK, 348 END_OF_GROUPS, 349 }), 350 }, 351 [PINCTRL_FUNC_QSPI_SS] = { 352 .name = "qspi_ss", 353 .regval = 0x02, 354 .groups = &((uint16_t []) { 355 PINCTRL_GRP_QSPI_SS, 356 END_OF_GROUPS, 357 }), 358 }, 359 [PINCTRL_FUNC_SPI0] = { 360 .name = "spi0", 361 .regval = 0x80, 362 .groups = &((uint16_t []) { 363 PINCTRL_GRP_SPI0_0, 364 PINCTRL_GRP_SPI0_1, 365 PINCTRL_GRP_SPI0_2, 366 PINCTRL_GRP_SPI0_3, 367 PINCTRL_GRP_SPI0_4, 368 PINCTRL_GRP_SPI0_5, 369 END_OF_GROUPS, 370 }), 371 }, 372 [PINCTRL_FUNC_SPI1] = { 373 .name = "spi1", 374 .regval = 0x80, 375 .groups = &((uint16_t []) { 376 PINCTRL_GRP_SPI1_0, 377 PINCTRL_GRP_SPI1_1, 378 PINCTRL_GRP_SPI1_2, 379 PINCTRL_GRP_SPI1_3, 380 PINCTRL_GRP_SPI1_4, 381 PINCTRL_GRP_SPI1_5, 382 END_OF_GROUPS, 383 }), 384 }, 385 [PINCTRL_FUNC_SPI0_SS] = { 386 .name = "spi0_ss", 387 .regval = 0x80, 388 .groups = &((uint16_t []) { 389 PINCTRL_GRP_SPI0_0_SS0, 390 PINCTRL_GRP_SPI0_0_SS1, 391 PINCTRL_GRP_SPI0_0_SS2, 392 PINCTRL_GRP_SPI0_1_SS0, 393 PINCTRL_GRP_SPI0_1_SS1, 394 PINCTRL_GRP_SPI0_1_SS2, 395 PINCTRL_GRP_SPI0_2_SS0, 396 PINCTRL_GRP_SPI0_2_SS1, 397 PINCTRL_GRP_SPI0_2_SS2, 398 PINCTRL_GRP_SPI0_3_SS0, 399 PINCTRL_GRP_SPI0_3_SS1, 400 PINCTRL_GRP_SPI0_3_SS2, 401 PINCTRL_GRP_SPI0_4_SS0, 402 PINCTRL_GRP_SPI0_4_SS1, 403 PINCTRL_GRP_SPI0_4_SS2, 404 PINCTRL_GRP_SPI0_5_SS0, 405 PINCTRL_GRP_SPI0_5_SS1, 406 PINCTRL_GRP_SPI0_5_SS2, 407 END_OF_GROUPS, 408 }), 409 }, 410 [PINCTRL_FUNC_SPI1_SS] = { 411 .name = "spi1_ss", 412 .regval = 0x80, 413 .groups = &((uint16_t []) { 414 PINCTRL_GRP_SPI1_0_SS0, 415 PINCTRL_GRP_SPI1_0_SS1, 416 PINCTRL_GRP_SPI1_0_SS2, 417 PINCTRL_GRP_SPI1_1_SS0, 418 PINCTRL_GRP_SPI1_1_SS1, 419 PINCTRL_GRP_SPI1_1_SS2, 420 PINCTRL_GRP_SPI1_2_SS0, 421 PINCTRL_GRP_SPI1_2_SS1, 422 PINCTRL_GRP_SPI1_2_SS2, 423 PINCTRL_GRP_SPI1_3_SS0, 424 PINCTRL_GRP_SPI1_3_SS1, 425 PINCTRL_GRP_SPI1_3_SS2, 426 PINCTRL_GRP_SPI1_4_SS0, 427 PINCTRL_GRP_SPI1_4_SS1, 428 PINCTRL_GRP_SPI1_4_SS2, 429 PINCTRL_GRP_SPI1_5_SS0, 430 PINCTRL_GRP_SPI1_5_SS1, 431 PINCTRL_GRP_SPI1_5_SS2, 432 END_OF_GROUPS, 433 }), 434 }, 435 [PINCTRL_FUNC_SDIO0] = { 436 .name = "sdio0", 437 .regval = 0x08, 438 .groups = &((uint16_t []) { 439 PINCTRL_GRP_SDIO0_0, 440 PINCTRL_GRP_SDIO0_1, 441 PINCTRL_GRP_SDIO0_2, 442 PINCTRL_GRP_SDIO0_4BIT_0_0, 443 PINCTRL_GRP_SDIO0_4BIT_0_1, 444 PINCTRL_GRP_SDIO0_4BIT_1_0, 445 PINCTRL_GRP_SDIO0_4BIT_1_1, 446 PINCTRL_GRP_SDIO0_4BIT_2_0, 447 PINCTRL_GRP_SDIO0_4BIT_2_1, 448 PINCTRL_GRP_SDIO0_1BIT_0_0, 449 PINCTRL_GRP_SDIO0_1BIT_0_1, 450 PINCTRL_GRP_SDIO0_1BIT_0_2, 451 PINCTRL_GRP_SDIO0_1BIT_0_3, 452 PINCTRL_GRP_SDIO0_1BIT_0_4, 453 PINCTRL_GRP_SDIO0_1BIT_0_5, 454 PINCTRL_GRP_SDIO0_1BIT_0_6, 455 PINCTRL_GRP_SDIO0_1BIT_0_7, 456 PINCTRL_GRP_SDIO0_1BIT_1_0, 457 PINCTRL_GRP_SDIO0_1BIT_1_1, 458 PINCTRL_GRP_SDIO0_1BIT_1_2, 459 PINCTRL_GRP_SDIO0_1BIT_1_3, 460 PINCTRL_GRP_SDIO0_1BIT_1_4, 461 PINCTRL_GRP_SDIO0_1BIT_1_5, 462 PINCTRL_GRP_SDIO0_1BIT_1_6, 463 PINCTRL_GRP_SDIO0_1BIT_1_7, 464 PINCTRL_GRP_SDIO0_1BIT_2_0, 465 PINCTRL_GRP_SDIO0_1BIT_2_1, 466 PINCTRL_GRP_SDIO0_1BIT_2_2, 467 PINCTRL_GRP_SDIO0_1BIT_2_3, 468 PINCTRL_GRP_SDIO0_1BIT_2_4, 469 PINCTRL_GRP_SDIO0_1BIT_2_5, 470 PINCTRL_GRP_SDIO0_1BIT_2_6, 471 PINCTRL_GRP_SDIO0_1BIT_2_7, 472 END_OF_GROUPS, 473 }), 474 }, 475 [PINCTRL_FUNC_SDIO0_PC] = { 476 .name = "sdio0_pc", 477 .regval = 0x08, 478 .groups = &((uint16_t []) { 479 PINCTRL_GRP_SDIO0_0_PC, 480 PINCTRL_GRP_SDIO0_1_PC, 481 PINCTRL_GRP_SDIO0_2_PC, 482 END_OF_GROUPS, 483 }), 484 }, 485 [PINCTRL_FUNC_SDIO0_CD] = { 486 .name = "sdio0_cd", 487 .regval = 0x08, 488 .groups = &((uint16_t []) { 489 PINCTRL_GRP_SDIO0_0_CD, 490 PINCTRL_GRP_SDIO0_1_CD, 491 PINCTRL_GRP_SDIO0_2_CD, 492 END_OF_GROUPS, 493 }), 494 }, 495 [PINCTRL_FUNC_SDIO0_WP] = { 496 .name = "sdio0_wp", 497 .regval = 0x08, 498 .groups = &((uint16_t []) { 499 PINCTRL_GRP_SDIO0_0_WP, 500 PINCTRL_GRP_SDIO0_1_WP, 501 PINCTRL_GRP_SDIO0_2_WP, 502 END_OF_GROUPS, 503 }), 504 }, 505 [PINCTRL_FUNC_SDIO1] = { 506 .name = "sdio1", 507 .regval = 0x10, 508 .groups = &((uint16_t []) { 509 PINCTRL_GRP_SDIO1_0, 510 PINCTRL_GRP_SDIO1_4BIT_0_0, 511 PINCTRL_GRP_SDIO1_4BIT_0_1, 512 PINCTRL_GRP_SDIO1_4BIT_1_0, 513 PINCTRL_GRP_SDIO1_1BIT_0_0, 514 PINCTRL_GRP_SDIO1_1BIT_0_1, 515 PINCTRL_GRP_SDIO1_1BIT_0_2, 516 PINCTRL_GRP_SDIO1_1BIT_0_3, 517 PINCTRL_GRP_SDIO1_1BIT_0_4, 518 PINCTRL_GRP_SDIO1_1BIT_0_5, 519 PINCTRL_GRP_SDIO1_1BIT_0_6, 520 PINCTRL_GRP_SDIO1_1BIT_0_7, 521 PINCTRL_GRP_SDIO1_1BIT_1_0, 522 PINCTRL_GRP_SDIO1_1BIT_1_1, 523 PINCTRL_GRP_SDIO1_1BIT_1_2, 524 PINCTRL_GRP_SDIO1_1BIT_1_3, 525 END_OF_GROUPS, 526 }), 527 }, 528 [PINCTRL_FUNC_SDIO1_PC] = { 529 .name = "sdio1_pc", 530 .regval = 0x10, 531 .groups = &((uint16_t []) { 532 PINCTRL_GRP_SDIO1_0_PC, 533 PINCTRL_GRP_SDIO1_1_PC, 534 END_OF_GROUPS, 535 }), 536 }, 537 [PINCTRL_FUNC_SDIO1_CD] = { 538 .name = "sdio1_cd", 539 .regval = 0x10, 540 .groups = &((uint16_t []) { 541 PINCTRL_GRP_SDIO1_0_CD, 542 PINCTRL_GRP_SDIO1_1_CD, 543 END_OF_GROUPS, 544 }), 545 }, 546 [PINCTRL_FUNC_SDIO1_WP] = { 547 .name = "sdio1_wp", 548 .regval = 0x10, 549 .groups = &((uint16_t []) { 550 PINCTRL_GRP_SDIO1_0_WP, 551 PINCTRL_GRP_SDIO1_1_WP, 552 END_OF_GROUPS, 553 }), 554 }, 555 [PINCTRL_FUNC_NAND0] = { 556 .name = "nand0", 557 .regval = 0x04, 558 .groups = &((uint16_t []) { 559 PINCTRL_GRP_NAND0_0, 560 END_OF_GROUPS, 561 }), 562 }, 563 [PINCTRL_FUNC_NAND0_CE] = { 564 .name = "nand0_ce", 565 .regval = 0x04, 566 .groups = &((uint16_t []) { 567 PINCTRL_GRP_NAND0_0_CE, 568 PINCTRL_GRP_NAND0_1_CE, 569 END_OF_GROUPS, 570 }), 571 }, 572 [PINCTRL_FUNC_NAND0_RB] = { 573 .name = "nand0_rb", 574 .regval = 0x04, 575 .groups = &((uint16_t []) { 576 PINCTRL_GRP_NAND0_0_RB, 577 PINCTRL_GRP_NAND0_1_RB, 578 END_OF_GROUPS, 579 }), 580 }, 581 [PINCTRL_FUNC_NAND0_DQS] = { 582 .name = "nand0_dqs", 583 .regval = 0x04, 584 .groups = &((uint16_t []) { 585 PINCTRL_GRP_NAND0_0_DQS, 586 PINCTRL_GRP_NAND0_1_DQS, 587 END_OF_GROUPS, 588 }), 589 }, 590 [PINCTRL_FUNC_TTC0_CLK] = { 591 .name = "ttc0_clk", 592 .regval = 0xa0, 593 .groups = &((uint16_t []) { 594 PINCTRL_GRP_TTC0_0_CLK, 595 PINCTRL_GRP_TTC0_1_CLK, 596 PINCTRL_GRP_TTC0_2_CLK, 597 PINCTRL_GRP_TTC0_3_CLK, 598 PINCTRL_GRP_TTC0_4_CLK, 599 PINCTRL_GRP_TTC0_5_CLK, 600 PINCTRL_GRP_TTC0_6_CLK, 601 PINCTRL_GRP_TTC0_7_CLK, 602 PINCTRL_GRP_TTC0_8_CLK, 603 END_OF_GROUPS, 604 }), 605 }, 606 [PINCTRL_FUNC_TTC0_WAV] = { 607 .name = "ttc0_wav", 608 .regval = 0xa0, 609 .groups = &((uint16_t []) { 610 PINCTRL_GRP_TTC0_0_WAV, 611 PINCTRL_GRP_TTC0_1_WAV, 612 PINCTRL_GRP_TTC0_2_WAV, 613 PINCTRL_GRP_TTC0_3_WAV, 614 PINCTRL_GRP_TTC0_4_WAV, 615 PINCTRL_GRP_TTC0_5_WAV, 616 PINCTRL_GRP_TTC0_6_WAV, 617 PINCTRL_GRP_TTC0_7_WAV, 618 PINCTRL_GRP_TTC0_8_WAV, 619 END_OF_GROUPS, 620 }), 621 }, 622 [PINCTRL_FUNC_TTC1_CLK] = { 623 .name = "ttc1_clk", 624 .regval = 0xa0, 625 .groups = &((uint16_t []) { 626 PINCTRL_GRP_TTC1_0_CLK, 627 PINCTRL_GRP_TTC1_1_CLK, 628 PINCTRL_GRP_TTC1_2_CLK, 629 PINCTRL_GRP_TTC1_3_CLK, 630 PINCTRL_GRP_TTC1_4_CLK, 631 PINCTRL_GRP_TTC1_5_CLK, 632 PINCTRL_GRP_TTC1_6_CLK, 633 PINCTRL_GRP_TTC1_7_CLK, 634 PINCTRL_GRP_TTC1_8_CLK, 635 END_OF_GROUPS, 636 }), 637 }, 638 [PINCTRL_FUNC_TTC1_WAV] = { 639 .name = "ttc1_wav", 640 .regval = 0xa0, 641 .groups = &((uint16_t []) { 642 PINCTRL_GRP_TTC1_0_WAV, 643 PINCTRL_GRP_TTC1_1_WAV, 644 PINCTRL_GRP_TTC1_2_WAV, 645 PINCTRL_GRP_TTC1_3_WAV, 646 PINCTRL_GRP_TTC1_4_WAV, 647 PINCTRL_GRP_TTC1_5_WAV, 648 PINCTRL_GRP_TTC1_6_WAV, 649 PINCTRL_GRP_TTC1_7_WAV, 650 PINCTRL_GRP_TTC1_8_WAV, 651 END_OF_GROUPS, 652 }), 653 }, 654 [PINCTRL_FUNC_TTC2_CLK] = { 655 .name = "ttc2_clk", 656 .regval = 0xa0, 657 .groups = &((uint16_t []) { 658 PINCTRL_GRP_TTC2_0_CLK, 659 PINCTRL_GRP_TTC2_1_CLK, 660 PINCTRL_GRP_TTC2_2_CLK, 661 PINCTRL_GRP_TTC2_3_CLK, 662 PINCTRL_GRP_TTC2_4_CLK, 663 PINCTRL_GRP_TTC2_5_CLK, 664 PINCTRL_GRP_TTC2_6_CLK, 665 PINCTRL_GRP_TTC2_7_CLK, 666 PINCTRL_GRP_TTC2_8_CLK, 667 END_OF_GROUPS, 668 }), 669 }, 670 [PINCTRL_FUNC_TTC2_WAV] = { 671 .name = "ttc2_wav", 672 .regval = 0xa0, 673 .groups = &((uint16_t []) { 674 PINCTRL_GRP_TTC2_0_WAV, 675 PINCTRL_GRP_TTC2_1_WAV, 676 PINCTRL_GRP_TTC2_2_WAV, 677 PINCTRL_GRP_TTC2_3_WAV, 678 PINCTRL_GRP_TTC2_4_WAV, 679 PINCTRL_GRP_TTC2_5_WAV, 680 PINCTRL_GRP_TTC2_6_WAV, 681 PINCTRL_GRP_TTC2_7_WAV, 682 PINCTRL_GRP_TTC2_8_WAV, 683 END_OF_GROUPS, 684 }), 685 }, 686 [PINCTRL_FUNC_TTC3_CLK] = { 687 .name = "ttc3_clk", 688 .regval = 0xa0, 689 .groups = &((uint16_t []) { 690 PINCTRL_GRP_TTC3_0_CLK, 691 PINCTRL_GRP_TTC3_1_CLK, 692 PINCTRL_GRP_TTC3_2_CLK, 693 PINCTRL_GRP_TTC3_3_CLK, 694 PINCTRL_GRP_TTC3_4_CLK, 695 PINCTRL_GRP_TTC3_5_CLK, 696 PINCTRL_GRP_TTC3_6_CLK, 697 PINCTRL_GRP_TTC3_7_CLK, 698 PINCTRL_GRP_TTC3_8_CLK, 699 END_OF_GROUPS, 700 }), 701 }, 702 [PINCTRL_FUNC_TTC3_WAV] = { 703 .name = "ttc3_wav", 704 .regval = 0xa0, 705 .groups = &((uint16_t []) { 706 PINCTRL_GRP_TTC3_0_WAV, 707 PINCTRL_GRP_TTC3_1_WAV, 708 PINCTRL_GRP_TTC3_2_WAV, 709 PINCTRL_GRP_TTC3_3_WAV, 710 PINCTRL_GRP_TTC3_4_WAV, 711 PINCTRL_GRP_TTC3_5_WAV, 712 PINCTRL_GRP_TTC3_6_WAV, 713 PINCTRL_GRP_TTC3_7_WAV, 714 PINCTRL_GRP_TTC3_8_WAV, 715 END_OF_GROUPS, 716 }), 717 }, 718 [PINCTRL_FUNC_UART0] = { 719 .name = "uart0", 720 .regval = 0xc0, 721 .groups = &((uint16_t []) { 722 PINCTRL_GRP_UART0_0, 723 PINCTRL_GRP_UART0_1, 724 PINCTRL_GRP_UART0_2, 725 PINCTRL_GRP_UART0_3, 726 PINCTRL_GRP_UART0_4, 727 PINCTRL_GRP_UART0_5, 728 PINCTRL_GRP_UART0_6, 729 PINCTRL_GRP_UART0_7, 730 PINCTRL_GRP_UART0_8, 731 PINCTRL_GRP_UART0_9, 732 PINCTRL_GRP_UART0_10, 733 PINCTRL_GRP_UART0_11, 734 PINCTRL_GRP_UART0_12, 735 PINCTRL_GRP_UART0_13, 736 PINCTRL_GRP_UART0_14, 737 PINCTRL_GRP_UART0_15, 738 PINCTRL_GRP_UART0_16, 739 PINCTRL_GRP_UART0_17, 740 PINCTRL_GRP_UART0_18, 741 END_OF_GROUPS, 742 }), 743 }, 744 [PINCTRL_FUNC_UART1] = { 745 .name = "uart1", 746 .regval = 0xc0, 747 .groups = &((uint16_t []) { 748 PINCTRL_GRP_UART1_0, 749 PINCTRL_GRP_UART1_1, 750 PINCTRL_GRP_UART1_2, 751 PINCTRL_GRP_UART1_3, 752 PINCTRL_GRP_UART1_4, 753 PINCTRL_GRP_UART1_5, 754 PINCTRL_GRP_UART1_6, 755 PINCTRL_GRP_UART1_7, 756 PINCTRL_GRP_UART1_8, 757 PINCTRL_GRP_UART1_9, 758 PINCTRL_GRP_UART1_10, 759 PINCTRL_GRP_UART1_11, 760 PINCTRL_GRP_UART1_12, 761 PINCTRL_GRP_UART1_13, 762 PINCTRL_GRP_UART1_14, 763 PINCTRL_GRP_UART1_15, 764 PINCTRL_GRP_UART1_16, 765 PINCTRL_GRP_UART1_17, 766 PINCTRL_GRP_UART1_18, 767 END_OF_GROUPS, 768 }), 769 }, 770 [PINCTRL_FUNC_USB0] = { 771 .name = "usb0", 772 .regval = 0x04, 773 .groups = &((uint16_t []) { 774 PINCTRL_GRP_USB0_0, 775 END_OF_GROUPS, 776 }), 777 }, 778 [PINCTRL_FUNC_USB1] = { 779 .name = "usb1", 780 .regval = 0x04, 781 .groups = &((uint16_t []) { 782 PINCTRL_GRP_USB1_0, 783 END_OF_GROUPS, 784 }), 785 }, 786 [PINCTRL_FUNC_SWDT0_CLK] = { 787 .name = "swdt0_clk", 788 .regval = 0x60, 789 .groups = &((uint16_t []) { 790 PINCTRL_GRP_SWDT0_0_CLK, 791 PINCTRL_GRP_SWDT0_1_CLK, 792 PINCTRL_GRP_SWDT0_2_CLK, 793 PINCTRL_GRP_SWDT0_3_CLK, 794 PINCTRL_GRP_SWDT0_4_CLK, 795 PINCTRL_GRP_SWDT0_5_CLK, 796 PINCTRL_GRP_SWDT0_6_CLK, 797 PINCTRL_GRP_SWDT0_7_CLK, 798 PINCTRL_GRP_SWDT0_8_CLK, 799 PINCTRL_GRP_SWDT0_9_CLK, 800 PINCTRL_GRP_SWDT0_10_CLK, 801 PINCTRL_GRP_SWDT0_11_CLK, 802 PINCTRL_GRP_SWDT0_12_CLK, 803 END_OF_GROUPS, 804 }), 805 }, 806 [PINCTRL_FUNC_SWDT0_RST] = { 807 .name = "swdt0_rst", 808 .regval = 0x60, 809 .groups = &((uint16_t []) { 810 PINCTRL_GRP_SWDT0_0_RST, 811 PINCTRL_GRP_SWDT0_1_RST, 812 PINCTRL_GRP_SWDT0_2_RST, 813 PINCTRL_GRP_SWDT0_3_RST, 814 PINCTRL_GRP_SWDT0_4_RST, 815 PINCTRL_GRP_SWDT0_5_RST, 816 PINCTRL_GRP_SWDT0_6_RST, 817 PINCTRL_GRP_SWDT0_7_RST, 818 PINCTRL_GRP_SWDT0_8_RST, 819 PINCTRL_GRP_SWDT0_9_RST, 820 PINCTRL_GRP_SWDT0_10_RST, 821 PINCTRL_GRP_SWDT0_11_RST, 822 PINCTRL_GRP_SWDT0_12_RST, 823 END_OF_GROUPS, 824 }), 825 }, 826 [PINCTRL_FUNC_SWDT1_CLK] = { 827 .name = "swdt1_clk", 828 .regval = 0x60, 829 .groups = &((uint16_t []) { 830 PINCTRL_GRP_SWDT1_0_CLK, 831 PINCTRL_GRP_SWDT1_1_CLK, 832 PINCTRL_GRP_SWDT1_2_CLK, 833 PINCTRL_GRP_SWDT1_3_CLK, 834 PINCTRL_GRP_SWDT1_4_CLK, 835 PINCTRL_GRP_SWDT1_5_CLK, 836 PINCTRL_GRP_SWDT1_6_CLK, 837 PINCTRL_GRP_SWDT1_7_CLK, 838 PINCTRL_GRP_SWDT1_8_CLK, 839 PINCTRL_GRP_SWDT1_9_CLK, 840 PINCTRL_GRP_SWDT1_10_CLK, 841 PINCTRL_GRP_SWDT1_11_CLK, 842 PINCTRL_GRP_SWDT1_12_CLK, 843 END_OF_GROUPS, 844 }), 845 }, 846 [PINCTRL_FUNC_SWDT1_RST] = { 847 .name = "swdt1_rst", 848 .regval = 0x60, 849 .groups = &((uint16_t []) { 850 PINCTRL_GRP_SWDT1_0_RST, 851 PINCTRL_GRP_SWDT1_1_RST, 852 PINCTRL_GRP_SWDT1_2_RST, 853 PINCTRL_GRP_SWDT1_3_RST, 854 PINCTRL_GRP_SWDT1_4_RST, 855 PINCTRL_GRP_SWDT1_5_RST, 856 PINCTRL_GRP_SWDT1_6_RST, 857 PINCTRL_GRP_SWDT1_7_RST, 858 PINCTRL_GRP_SWDT1_8_RST, 859 PINCTRL_GRP_SWDT1_9_RST, 860 PINCTRL_GRP_SWDT1_10_RST, 861 PINCTRL_GRP_SWDT1_11_RST, 862 PINCTRL_GRP_SWDT1_12_RST, 863 END_OF_GROUPS, 864 }), 865 }, 866 [PINCTRL_FUNC_PMU0] = { 867 .name = "pmu0", 868 .regval = 0x08, 869 .groups = &((uint16_t []) { 870 PINCTRL_GRP_PMU0_0, 871 PINCTRL_GRP_PMU0_1, 872 PINCTRL_GRP_PMU0_2, 873 PINCTRL_GRP_PMU0_3, 874 PINCTRL_GRP_PMU0_4, 875 PINCTRL_GRP_PMU0_5, 876 PINCTRL_GRP_PMU0_6, 877 PINCTRL_GRP_PMU0_7, 878 PINCTRL_GRP_PMU0_8, 879 PINCTRL_GRP_PMU0_9, 880 PINCTRL_GRP_PMU0_10, 881 PINCTRL_GRP_PMU0_11, 882 END_OF_GROUPS, 883 }), 884 }, 885 [PINCTRL_FUNC_PCIE0] = { 886 .name = "pcie0", 887 .regval = 0x04, 888 .groups = &((uint16_t []) { 889 PINCTRL_GRP_PCIE0_0, 890 PINCTRL_GRP_PCIE0_1, 891 PINCTRL_GRP_PCIE0_2, 892 PINCTRL_GRP_PCIE0_3, 893 PINCTRL_GRP_PCIE0_4, 894 PINCTRL_GRP_PCIE0_5, 895 PINCTRL_GRP_PCIE0_6, 896 PINCTRL_GRP_PCIE0_7, 897 END_OF_GROUPS, 898 }), 899 }, 900 [PINCTRL_FUNC_CSU0] = { 901 .name = "csu0", 902 .regval = 0x18, 903 .groups = &((uint16_t []) { 904 PINCTRL_GRP_CSU0_0, 905 PINCTRL_GRP_CSU0_1, 906 PINCTRL_GRP_CSU0_2, 907 PINCTRL_GRP_CSU0_3, 908 PINCTRL_GRP_CSU0_4, 909 PINCTRL_GRP_CSU0_5, 910 PINCTRL_GRP_CSU0_6, 911 PINCTRL_GRP_CSU0_7, 912 PINCTRL_GRP_CSU0_8, 913 PINCTRL_GRP_CSU0_9, 914 PINCTRL_GRP_CSU0_10, 915 PINCTRL_GRP_CSU0_11, 916 END_OF_GROUPS, 917 }), 918 }, 919 [PINCTRL_FUNC_DPAUX0] = { 920 .name = "dpaux0", 921 .regval = 0x18, 922 .groups = &((uint16_t []) { 923 PINCTRL_GRP_DPAUX0_0, 924 PINCTRL_GRP_DPAUX0_1, 925 PINCTRL_GRP_DPAUX0_2, 926 PINCTRL_GRP_DPAUX0_3, 927 END_OF_GROUPS, 928 }), 929 }, 930 [PINCTRL_FUNC_PJTAG0] = { 931 .name = "pjtag0", 932 .regval = 0x60, 933 .groups = &((uint16_t []) { 934 PINCTRL_GRP_PJTAG0_0, 935 PINCTRL_GRP_PJTAG0_1, 936 PINCTRL_GRP_PJTAG0_2, 937 PINCTRL_GRP_PJTAG0_3, 938 PINCTRL_GRP_PJTAG0_4, 939 PINCTRL_GRP_PJTAG0_5, 940 END_OF_GROUPS, 941 }), 942 }, 943 [PINCTRL_FUNC_TRACE0] = { 944 .name = "trace0", 945 .regval = 0xe0, 946 .groups = &((uint16_t []) { 947 PINCTRL_GRP_TRACE0_0, 948 PINCTRL_GRP_TRACE0_1, 949 PINCTRL_GRP_TRACE0_2, 950 END_OF_GROUPS, 951 }), 952 }, 953 [PINCTRL_FUNC_TRACE0_CLK] = { 954 .name = "trace0_clk", 955 .regval = 0xe0, 956 .groups = &((uint16_t []) { 957 PINCTRL_GRP_TRACE0_0_CLK, 958 PINCTRL_GRP_TRACE0_1_CLK, 959 PINCTRL_GRP_TRACE0_2_CLK, 960 END_OF_GROUPS, 961 }), 962 }, 963 [PINCTRL_FUNC_TESTSCAN0] = { 964 .name = "testscan0", 965 .regval = 0x10, 966 .groups = &((uint16_t []) { 967 PINCTRL_GRP_TESTSCAN0_0, 968 END_OF_GROUPS, 969 }), 970 }, 971 }; 972 973 static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { 974 [PINCTRL_PIN_0] = { 975 .groups = &((uint16_t []) { 976 PINCTRL_GRP_QSPI0_0, 977 PINCTRL_GRP_RESERVED, 978 PINCTRL_GRP_RESERVED, 979 PINCTRL_GRP_TESTSCAN0_0, 980 PINCTRL_GRP_RESERVED, 981 PINCTRL_GRP_GPIO0_0, 982 PINCTRL_GRP_CAN1_0, 983 PINCTRL_GRP_I2C1_0, 984 PINCTRL_GRP_PJTAG0_0, 985 PINCTRL_GRP_SPI0_0, 986 PINCTRL_GRP_TTC3_0_CLK, 987 PINCTRL_GRP_UART1_0, 988 PINCTRL_GRP_TRACE0_0_CLK, 989 END_OF_GROUPS, 990 }), 991 }, 992 [PINCTRL_PIN_1] = { 993 .groups = &((uint16_t []) { 994 PINCTRL_GRP_QSPI0_0, 995 PINCTRL_GRP_RESERVED, 996 PINCTRL_GRP_RESERVED, 997 PINCTRL_GRP_TESTSCAN0_0, 998 PINCTRL_GRP_RESERVED, 999 PINCTRL_GRP_GPIO0_1, 1000 PINCTRL_GRP_CAN1_0, 1001 PINCTRL_GRP_I2C1_0, 1002 PINCTRL_GRP_PJTAG0_0, 1003 PINCTRL_GRP_SPI0_0_SS2, 1004 PINCTRL_GRP_TTC3_0_WAV, 1005 PINCTRL_GRP_UART1_0, 1006 PINCTRL_GRP_TRACE0_0_CLK, 1007 END_OF_GROUPS, 1008 }), 1009 }, 1010 [PINCTRL_PIN_2] = { 1011 .groups = &((uint16_t []) { 1012 PINCTRL_GRP_QSPI0_0, 1013 PINCTRL_GRP_RESERVED, 1014 PINCTRL_GRP_RESERVED, 1015 PINCTRL_GRP_TESTSCAN0_0, 1016 PINCTRL_GRP_RESERVED, 1017 PINCTRL_GRP_GPIO0_2, 1018 PINCTRL_GRP_CAN0_0, 1019 PINCTRL_GRP_I2C0_0, 1020 PINCTRL_GRP_PJTAG0_0, 1021 PINCTRL_GRP_SPI0_0_SS1, 1022 PINCTRL_GRP_TTC2_0_CLK, 1023 PINCTRL_GRP_UART0_0, 1024 PINCTRL_GRP_TRACE0_0, 1025 END_OF_GROUPS, 1026 }), 1027 }, 1028 [PINCTRL_PIN_3] = { 1029 .groups = &((uint16_t []) { 1030 PINCTRL_GRP_QSPI0_0, 1031 PINCTRL_GRP_RESERVED, 1032 PINCTRL_GRP_RESERVED, 1033 PINCTRL_GRP_TESTSCAN0_0, 1034 PINCTRL_GRP_RESERVED, 1035 PINCTRL_GRP_GPIO0_3, 1036 PINCTRL_GRP_CAN0_0, 1037 PINCTRL_GRP_I2C0_0, 1038 PINCTRL_GRP_PJTAG0_0, 1039 PINCTRL_GRP_SPI0_0_SS0, 1040 PINCTRL_GRP_TTC2_0_WAV, 1041 PINCTRL_GRP_UART0_0, 1042 PINCTRL_GRP_TRACE0_0, 1043 END_OF_GROUPS, 1044 }), 1045 }, 1046 [PINCTRL_PIN_4] = { 1047 .groups = &((uint16_t []) { 1048 PINCTRL_GRP_QSPI0_0, 1049 PINCTRL_GRP_RESERVED, 1050 PINCTRL_GRP_RESERVED, 1051 PINCTRL_GRP_TESTSCAN0_0, 1052 PINCTRL_GRP_RESERVED, 1053 PINCTRL_GRP_GPIO0_4, 1054 PINCTRL_GRP_CAN1_1, 1055 PINCTRL_GRP_I2C1_1, 1056 PINCTRL_GRP_SWDT1_0_CLK, 1057 PINCTRL_GRP_SPI0_0, 1058 PINCTRL_GRP_TTC1_0_CLK, 1059 PINCTRL_GRP_UART1_1, 1060 PINCTRL_GRP_TRACE0_0, 1061 END_OF_GROUPS, 1062 }), 1063 }, 1064 [PINCTRL_PIN_5] = { 1065 .groups = &((uint16_t []) { 1066 PINCTRL_GRP_QSPI_SS, 1067 PINCTRL_GRP_RESERVED, 1068 PINCTRL_GRP_RESERVED, 1069 PINCTRL_GRP_TESTSCAN0_0, 1070 PINCTRL_GRP_RESERVED, 1071 PINCTRL_GRP_GPIO0_5, 1072 PINCTRL_GRP_CAN1_1, 1073 PINCTRL_GRP_I2C1_1, 1074 PINCTRL_GRP_SWDT1_0_RST, 1075 PINCTRL_GRP_SPI0_0, 1076 PINCTRL_GRP_TTC1_0_WAV, 1077 PINCTRL_GRP_UART1_1, 1078 PINCTRL_GRP_TRACE0_0, 1079 END_OF_GROUPS, 1080 }), 1081 }, 1082 [PINCTRL_PIN_6] = { 1083 .groups = &((uint16_t []) { 1084 PINCTRL_GRP_QSPI_FBCLK, 1085 PINCTRL_GRP_RESERVED, 1086 PINCTRL_GRP_RESERVED, 1087 PINCTRL_GRP_TESTSCAN0_0, 1088 PINCTRL_GRP_RESERVED, 1089 PINCTRL_GRP_GPIO0_6, 1090 PINCTRL_GRP_CAN0_1, 1091 PINCTRL_GRP_I2C0_1, 1092 PINCTRL_GRP_SWDT0_0_CLK, 1093 PINCTRL_GRP_SPI1_0, 1094 PINCTRL_GRP_TTC0_0_CLK, 1095 PINCTRL_GRP_UART0_1, 1096 PINCTRL_GRP_TRACE0_0, 1097 END_OF_GROUPS, 1098 }), 1099 }, 1100 [PINCTRL_PIN_7] = { 1101 .groups = &((uint16_t []) { 1102 PINCTRL_GRP_QSPI_SS, 1103 PINCTRL_GRP_RESERVED, 1104 PINCTRL_GRP_RESERVED, 1105 PINCTRL_GRP_TESTSCAN0_0, 1106 PINCTRL_GRP_RESERVED, 1107 PINCTRL_GRP_GPIO0_7, 1108 PINCTRL_GRP_CAN0_1, 1109 PINCTRL_GRP_I2C0_1, 1110 PINCTRL_GRP_SWDT0_0_RST, 1111 PINCTRL_GRP_SPI1_0_SS2, 1112 PINCTRL_GRP_TTC0_0_WAV, 1113 PINCTRL_GRP_UART0_1, 1114 PINCTRL_GRP_TRACE0_0, 1115 END_OF_GROUPS, 1116 }), 1117 }, 1118 [PINCTRL_PIN_8] = { 1119 .groups = &((uint16_t []) { 1120 PINCTRL_GRP_QSPI0_0, 1121 PINCTRL_GRP_RESERVED, 1122 PINCTRL_GRP_RESERVED, 1123 PINCTRL_GRP_TESTSCAN0_0, 1124 PINCTRL_GRP_RESERVED, 1125 PINCTRL_GRP_GPIO0_8, 1126 PINCTRL_GRP_CAN1_2, 1127 PINCTRL_GRP_I2C1_2, 1128 PINCTRL_GRP_SWDT1_1_CLK, 1129 PINCTRL_GRP_SPI1_0_SS1, 1130 PINCTRL_GRP_TTC3_1_CLK, 1131 PINCTRL_GRP_UART1_2, 1132 PINCTRL_GRP_TRACE0_0, 1133 END_OF_GROUPS, 1134 }), 1135 }, 1136 [PINCTRL_PIN_9] = { 1137 .groups = &((uint16_t []) { 1138 PINCTRL_GRP_QSPI0_0, 1139 PINCTRL_GRP_NAND0_0_CE, 1140 PINCTRL_GRP_RESERVED, 1141 PINCTRL_GRP_TESTSCAN0_0, 1142 PINCTRL_GRP_RESERVED, 1143 PINCTRL_GRP_GPIO0_9, 1144 PINCTRL_GRP_CAN1_2, 1145 PINCTRL_GRP_I2C1_2, 1146 PINCTRL_GRP_SWDT1_1_RST, 1147 PINCTRL_GRP_SPI1_0_SS0, 1148 PINCTRL_GRP_TTC3_1_WAV, 1149 PINCTRL_GRP_UART1_2, 1150 PINCTRL_GRP_TRACE0_0, 1151 END_OF_GROUPS, 1152 }), 1153 }, 1154 [PINCTRL_PIN_10] = { 1155 .groups = &((uint16_t []) { 1156 PINCTRL_GRP_QSPI0_0, 1157 PINCTRL_GRP_NAND0_0_RB, 1158 PINCTRL_GRP_RESERVED, 1159 PINCTRL_GRP_TESTSCAN0_0, 1160 PINCTRL_GRP_RESERVED, 1161 PINCTRL_GRP_GPIO0_10, 1162 PINCTRL_GRP_CAN0_2, 1163 PINCTRL_GRP_I2C0_2, 1164 PINCTRL_GRP_SWDT0_1_CLK, 1165 PINCTRL_GRP_SPI1_0, 1166 PINCTRL_GRP_TTC2_1_CLK, 1167 PINCTRL_GRP_UART0_2, 1168 PINCTRL_GRP_TRACE0_0, 1169 END_OF_GROUPS, 1170 }), 1171 }, 1172 [PINCTRL_PIN_11] = { 1173 .groups = &((uint16_t []) { 1174 PINCTRL_GRP_QSPI0_0, 1175 PINCTRL_GRP_NAND0_0_RB, 1176 PINCTRL_GRP_RESERVED, 1177 PINCTRL_GRP_TESTSCAN0_0, 1178 PINCTRL_GRP_RESERVED, 1179 PINCTRL_GRP_GPIO0_11, 1180 PINCTRL_GRP_CAN0_2, 1181 PINCTRL_GRP_I2C0_2, 1182 PINCTRL_GRP_SWDT0_1_RST, 1183 PINCTRL_GRP_SPI1_0, 1184 PINCTRL_GRP_TTC2_1_WAV, 1185 PINCTRL_GRP_UART0_2, 1186 PINCTRL_GRP_TRACE0_0, 1187 END_OF_GROUPS, 1188 }), 1189 }, 1190 [PINCTRL_PIN_12] = { 1191 .groups = &((uint16_t []) { 1192 PINCTRL_GRP_QSPI0_0, 1193 PINCTRL_GRP_NAND0_0_DQS, 1194 PINCTRL_GRP_RESERVED, 1195 PINCTRL_GRP_TESTSCAN0_0, 1196 PINCTRL_GRP_RESERVED, 1197 PINCTRL_GRP_GPIO0_12, 1198 PINCTRL_GRP_CAN1_3, 1199 PINCTRL_GRP_I2C1_3, 1200 PINCTRL_GRP_PJTAG0_1, 1201 PINCTRL_GRP_SPI0_1, 1202 PINCTRL_GRP_TTC1_1_CLK, 1203 PINCTRL_GRP_UART1_3, 1204 PINCTRL_GRP_TRACE0_0, 1205 END_OF_GROUPS, 1206 }), 1207 }, 1208 [PINCTRL_PIN_13] = { 1209 .groups = &((uint16_t []) { 1210 PINCTRL_GRP_RESERVED, 1211 PINCTRL_GRP_NAND0_0, 1212 PINCTRL_GRP_SDIO0_0, 1213 PINCTRL_GRP_TESTSCAN0_0, 1214 PINCTRL_GRP_RESERVED, 1215 PINCTRL_GRP_GPIO0_13, 1216 PINCTRL_GRP_CAN1_3, 1217 PINCTRL_GRP_I2C1_3, 1218 PINCTRL_GRP_PJTAG0_1, 1219 PINCTRL_GRP_SPI0_1_SS2, 1220 PINCTRL_GRP_TTC1_1_WAV, 1221 PINCTRL_GRP_UART1_3, 1222 PINCTRL_GRP_TRACE0_0, 1223 PINCTRL_GRP_SDIO0_4BIT_0_0, 1224 PINCTRL_GRP_SDIO0_1BIT_0_0, 1225 END_OF_GROUPS, 1226 }), 1227 }, 1228 [PINCTRL_PIN_14] = { 1229 .groups = &((uint16_t []) { 1230 PINCTRL_GRP_RESERVED, 1231 PINCTRL_GRP_NAND0_0, 1232 PINCTRL_GRP_SDIO0_0, 1233 PINCTRL_GRP_TESTSCAN0_0, 1234 PINCTRL_GRP_RESERVED, 1235 PINCTRL_GRP_GPIO0_14, 1236 PINCTRL_GRP_CAN0_3, 1237 PINCTRL_GRP_I2C0_3, 1238 PINCTRL_GRP_PJTAG0_1, 1239 PINCTRL_GRP_SPI0_1_SS1, 1240 PINCTRL_GRP_TTC0_1_CLK, 1241 PINCTRL_GRP_UART0_3, 1242 PINCTRL_GRP_TRACE0_0, 1243 PINCTRL_GRP_SDIO0_4BIT_0_0, 1244 PINCTRL_GRP_SDIO0_1BIT_0_1, 1245 END_OF_GROUPS, 1246 }), 1247 }, 1248 [PINCTRL_PIN_15] = { 1249 .groups = &((uint16_t []) { 1250 PINCTRL_GRP_RESERVED, 1251 PINCTRL_GRP_NAND0_0, 1252 PINCTRL_GRP_SDIO0_0, 1253 PINCTRL_GRP_TESTSCAN0_0, 1254 PINCTRL_GRP_RESERVED, 1255 PINCTRL_GRP_GPIO0_15, 1256 PINCTRL_GRP_CAN0_3, 1257 PINCTRL_GRP_I2C0_3, 1258 PINCTRL_GRP_PJTAG0_1, 1259 PINCTRL_GRP_SPI0_1_SS0, 1260 PINCTRL_GRP_TTC0_1_WAV, 1261 PINCTRL_GRP_UART0_3, 1262 PINCTRL_GRP_TRACE0_0, 1263 PINCTRL_GRP_SDIO0_4BIT_0_0, 1264 PINCTRL_GRP_SDIO0_1BIT_0_2, 1265 END_OF_GROUPS, 1266 }), 1267 }, 1268 [PINCTRL_PIN_16] = { 1269 .groups = &((uint16_t []) { 1270 PINCTRL_GRP_RESERVED, 1271 PINCTRL_GRP_NAND0_0, 1272 PINCTRL_GRP_SDIO0_0, 1273 PINCTRL_GRP_TESTSCAN0_0, 1274 PINCTRL_GRP_RESERVED, 1275 PINCTRL_GRP_GPIO0_16, 1276 PINCTRL_GRP_CAN1_4, 1277 PINCTRL_GRP_I2C1_4, 1278 PINCTRL_GRP_SWDT1_2_CLK, 1279 PINCTRL_GRP_SPI0_1, 1280 PINCTRL_GRP_TTC3_2_CLK, 1281 PINCTRL_GRP_UART1_4, 1282 PINCTRL_GRP_TRACE0_0, 1283 PINCTRL_GRP_SDIO0_4BIT_0_0, 1284 PINCTRL_GRP_SDIO0_1BIT_0_3, 1285 END_OF_GROUPS, 1286 }), 1287 }, 1288 [PINCTRL_PIN_17] = { 1289 .groups = &((uint16_t []) { 1290 PINCTRL_GRP_RESERVED, 1291 PINCTRL_GRP_NAND0_0, 1292 PINCTRL_GRP_SDIO0_0, 1293 PINCTRL_GRP_TESTSCAN0_0, 1294 PINCTRL_GRP_RESERVED, 1295 PINCTRL_GRP_GPIO0_17, 1296 PINCTRL_GRP_CAN1_4, 1297 PINCTRL_GRP_I2C1_4, 1298 PINCTRL_GRP_SWDT1_2_RST, 1299 PINCTRL_GRP_SPI0_1, 1300 PINCTRL_GRP_TTC3_2_WAV, 1301 PINCTRL_GRP_UART1_4, 1302 PINCTRL_GRP_TRACE0_0, 1303 PINCTRL_GRP_SDIO0_4BIT_0_1, 1304 PINCTRL_GRP_SDIO0_1BIT_0_4, 1305 END_OF_GROUPS, 1306 }), 1307 }, 1308 [PINCTRL_PIN_18] = { 1309 .groups = &((uint16_t []) { 1310 PINCTRL_GRP_RESERVED, 1311 PINCTRL_GRP_NAND0_0, 1312 PINCTRL_GRP_SDIO0_0, 1313 PINCTRL_GRP_TESTSCAN0_0, 1314 PINCTRL_GRP_CSU0_0, 1315 PINCTRL_GRP_GPIO0_18, 1316 PINCTRL_GRP_CAN0_4, 1317 PINCTRL_GRP_I2C0_4, 1318 PINCTRL_GRP_SWDT0_2_CLK, 1319 PINCTRL_GRP_SPI1_1, 1320 PINCTRL_GRP_TTC2_2_CLK, 1321 PINCTRL_GRP_UART0_4, 1322 PINCTRL_GRP_RESERVED, 1323 PINCTRL_GRP_SDIO0_4BIT_0_1, 1324 PINCTRL_GRP_SDIO0_1BIT_0_5, 1325 END_OF_GROUPS, 1326 }), 1327 }, 1328 [PINCTRL_PIN_19] = { 1329 .groups = &((uint16_t []) { 1330 PINCTRL_GRP_RESERVED, 1331 PINCTRL_GRP_NAND0_0, 1332 PINCTRL_GRP_SDIO0_0, 1333 PINCTRL_GRP_TESTSCAN0_0, 1334 PINCTRL_GRP_CSU0_1, 1335 PINCTRL_GRP_GPIO0_19, 1336 PINCTRL_GRP_CAN0_4, 1337 PINCTRL_GRP_I2C0_4, 1338 PINCTRL_GRP_SWDT0_2_RST, 1339 PINCTRL_GRP_SPI1_1_SS2, 1340 PINCTRL_GRP_TTC2_2_WAV, 1341 PINCTRL_GRP_UART0_4, 1342 PINCTRL_GRP_RESERVED, 1343 PINCTRL_GRP_SDIO0_4BIT_0_1, 1344 PINCTRL_GRP_SDIO0_1BIT_0_6, 1345 END_OF_GROUPS, 1346 }), 1347 }, 1348 [PINCTRL_PIN_20] = { 1349 .groups = &((uint16_t []) { 1350 PINCTRL_GRP_RESERVED, 1351 PINCTRL_GRP_NAND0_0, 1352 PINCTRL_GRP_SDIO0_0, 1353 PINCTRL_GRP_TESTSCAN0_0, 1354 PINCTRL_GRP_CSU0_2, 1355 PINCTRL_GRP_GPIO0_20, 1356 PINCTRL_GRP_CAN1_5, 1357 PINCTRL_GRP_I2C1_5, 1358 PINCTRL_GRP_SWDT1_3_CLK, 1359 PINCTRL_GRP_SPI1_1_SS1, 1360 PINCTRL_GRP_TTC1_2_CLK, 1361 PINCTRL_GRP_UART1_5, 1362 PINCTRL_GRP_RESERVED, 1363 PINCTRL_GRP_SDIO0_4BIT_0_1, 1364 PINCTRL_GRP_SDIO0_1BIT_0_7, 1365 END_OF_GROUPS, 1366 }), 1367 }, 1368 [PINCTRL_PIN_21] = { 1369 .groups = &((uint16_t []) { 1370 PINCTRL_GRP_RESERVED, 1371 PINCTRL_GRP_NAND0_0, 1372 PINCTRL_GRP_SDIO0_0, 1373 PINCTRL_GRP_TESTSCAN0_0, 1374 PINCTRL_GRP_CSU0_3, 1375 PINCTRL_GRP_GPIO0_21, 1376 PINCTRL_GRP_CAN1_5, 1377 PINCTRL_GRP_I2C1_5, 1378 PINCTRL_GRP_SWDT1_3_RST, 1379 PINCTRL_GRP_SPI1_1_SS0, 1380 PINCTRL_GRP_TTC1_2_WAV, 1381 PINCTRL_GRP_UART1_5, 1382 PINCTRL_GRP_RESERVED, 1383 PINCTRL_GRP_SDIO0_4BIT_0_0, 1384 PINCTRL_GRP_SDIO0_4BIT_0_1, 1385 PINCTRL_GRP_SDIO0_1BIT_0_0, 1386 PINCTRL_GRP_SDIO0_1BIT_0_1, 1387 PINCTRL_GRP_SDIO0_1BIT_0_2, 1388 PINCTRL_GRP_SDIO0_1BIT_0_3, 1389 PINCTRL_GRP_SDIO0_1BIT_0_4, 1390 PINCTRL_GRP_SDIO0_1BIT_0_5, 1391 PINCTRL_GRP_SDIO0_1BIT_0_6, 1392 PINCTRL_GRP_SDIO0_1BIT_0_7, 1393 END_OF_GROUPS, 1394 }), 1395 }, 1396 [PINCTRL_PIN_22] = { 1397 .groups = &((uint16_t []) { 1398 PINCTRL_GRP_RESERVED, 1399 PINCTRL_GRP_NAND0_0, 1400 PINCTRL_GRP_SDIO0_0, 1401 PINCTRL_GRP_TESTSCAN0_0, 1402 PINCTRL_GRP_CSU0_4, 1403 PINCTRL_GRP_GPIO0_22, 1404 PINCTRL_GRP_CAN0_5, 1405 PINCTRL_GRP_I2C0_5, 1406 PINCTRL_GRP_SWDT0_3_CLK, 1407 PINCTRL_GRP_SPI1_1, 1408 PINCTRL_GRP_TTC0_2_CLK, 1409 PINCTRL_GRP_UART0_5, 1410 PINCTRL_GRP_RESERVED, 1411 PINCTRL_GRP_SDIO0_4BIT_0_0, 1412 PINCTRL_GRP_SDIO0_4BIT_0_1, 1413 PINCTRL_GRP_SDIO0_1BIT_0_0, 1414 PINCTRL_GRP_SDIO0_1BIT_0_1, 1415 PINCTRL_GRP_SDIO0_1BIT_0_2, 1416 PINCTRL_GRP_SDIO0_1BIT_0_3, 1417 PINCTRL_GRP_SDIO0_1BIT_0_4, 1418 PINCTRL_GRP_SDIO0_1BIT_0_5, 1419 PINCTRL_GRP_SDIO0_1BIT_0_6, 1420 PINCTRL_GRP_SDIO0_1BIT_0_7, 1421 END_OF_GROUPS, 1422 }), 1423 }, 1424 [PINCTRL_PIN_23] = { 1425 .groups = &((uint16_t []) { 1426 PINCTRL_GRP_RESERVED, 1427 PINCTRL_GRP_NAND0_0, 1428 PINCTRL_GRP_SDIO0_0_PC, 1429 PINCTRL_GRP_TESTSCAN0_0, 1430 PINCTRL_GRP_CSU0_5, 1431 PINCTRL_GRP_GPIO0_23, 1432 PINCTRL_GRP_CAN0_5, 1433 PINCTRL_GRP_I2C0_5, 1434 PINCTRL_GRP_SWDT0_3_RST, 1435 PINCTRL_GRP_SPI1_1, 1436 PINCTRL_GRP_TTC0_2_WAV, 1437 PINCTRL_GRP_UART0_5, 1438 PINCTRL_GRP_RESERVED, 1439 END_OF_GROUPS, 1440 }), 1441 }, 1442 [PINCTRL_PIN_24] = { 1443 .groups = &((uint16_t []) { 1444 PINCTRL_GRP_RESERVED, 1445 PINCTRL_GRP_NAND0_0, 1446 PINCTRL_GRP_SDIO0_0_CD, 1447 PINCTRL_GRP_TESTSCAN0_0, 1448 PINCTRL_GRP_CSU0_6, 1449 PINCTRL_GRP_GPIO0_24, 1450 PINCTRL_GRP_CAN1_6, 1451 PINCTRL_GRP_I2C1_6, 1452 PINCTRL_GRP_SWDT1_4_CLK, 1453 PINCTRL_GRP_RESERVED, 1454 PINCTRL_GRP_TTC3_3_CLK, 1455 PINCTRL_GRP_UART1_6, 1456 PINCTRL_GRP_RESERVED, 1457 END_OF_GROUPS, 1458 }), 1459 }, 1460 [PINCTRL_PIN_25] = { 1461 .groups = &((uint16_t []) { 1462 PINCTRL_GRP_RESERVED, 1463 PINCTRL_GRP_NAND0_0, 1464 PINCTRL_GRP_SDIO0_0_WP, 1465 PINCTRL_GRP_TESTSCAN0_0, 1466 PINCTRL_GRP_CSU0_7, 1467 PINCTRL_GRP_GPIO0_25, 1468 PINCTRL_GRP_CAN1_6, 1469 PINCTRL_GRP_I2C1_6, 1470 PINCTRL_GRP_SWDT1_4_RST, 1471 PINCTRL_GRP_RESERVED, 1472 PINCTRL_GRP_TTC3_3_WAV, 1473 PINCTRL_GRP_UART1_6, 1474 PINCTRL_GRP_RESERVED, 1475 END_OF_GROUPS, 1476 }), 1477 }, 1478 [PINCTRL_PIN_26] = { 1479 .groups = &((uint16_t []) { 1480 PINCTRL_GRP_ETHERNET0_0, 1481 PINCTRL_GRP_GEMTSU0_0, 1482 PINCTRL_GRP_NAND0_1_CE, 1483 PINCTRL_GRP_PMU0_0, 1484 PINCTRL_GRP_TESTSCAN0_0, 1485 PINCTRL_GRP_CSU0_8, 1486 PINCTRL_GRP_GPIO0_26, 1487 PINCTRL_GRP_CAN0_6, 1488 PINCTRL_GRP_I2C0_6, 1489 PINCTRL_GRP_PJTAG0_2, 1490 PINCTRL_GRP_SPI0_2, 1491 PINCTRL_GRP_TTC2_3_CLK, 1492 PINCTRL_GRP_UART0_6, 1493 PINCTRL_GRP_TRACE0_1, 1494 END_OF_GROUPS, 1495 }), 1496 }, 1497 [PINCTRL_PIN_27] = { 1498 .groups = &((uint16_t []) { 1499 PINCTRL_GRP_ETHERNET0_0, 1500 PINCTRL_GRP_NAND0_1_RB, 1501 PINCTRL_GRP_PMU0_1, 1502 PINCTRL_GRP_TESTSCAN0_0, 1503 PINCTRL_GRP_DPAUX0_0, 1504 PINCTRL_GRP_GPIO0_27, 1505 PINCTRL_GRP_CAN0_6, 1506 PINCTRL_GRP_I2C0_6, 1507 PINCTRL_GRP_PJTAG0_2, 1508 PINCTRL_GRP_SPI0_2_SS2, 1509 PINCTRL_GRP_TTC2_3_WAV, 1510 PINCTRL_GRP_UART0_6, 1511 PINCTRL_GRP_TRACE0_1, 1512 END_OF_GROUPS, 1513 }), 1514 }, 1515 [PINCTRL_PIN_28] = { 1516 .groups = &((uint16_t []) { 1517 PINCTRL_GRP_ETHERNET0_0, 1518 PINCTRL_GRP_NAND0_1_RB, 1519 PINCTRL_GRP_PMU0_2, 1520 PINCTRL_GRP_TESTSCAN0_0, 1521 PINCTRL_GRP_DPAUX0_0, 1522 PINCTRL_GRP_GPIO0_28, 1523 PINCTRL_GRP_CAN1_7, 1524 PINCTRL_GRP_I2C1_7, 1525 PINCTRL_GRP_PJTAG0_2, 1526 PINCTRL_GRP_SPI0_2_SS1, 1527 PINCTRL_GRP_TTC1_3_CLK, 1528 PINCTRL_GRP_UART1_7, 1529 PINCTRL_GRP_TRACE0_1, 1530 END_OF_GROUPS, 1531 }), 1532 }, 1533 [PINCTRL_PIN_29] = { 1534 .groups = &((uint16_t []) { 1535 PINCTRL_GRP_ETHERNET0_0, 1536 PINCTRL_GRP_PCIE0_0, 1537 PINCTRL_GRP_PMU0_3, 1538 PINCTRL_GRP_TESTSCAN0_0, 1539 PINCTRL_GRP_DPAUX0_1, 1540 PINCTRL_GRP_GPIO0_29, 1541 PINCTRL_GRP_CAN1_7, 1542 PINCTRL_GRP_I2C1_7, 1543 PINCTRL_GRP_PJTAG0_2, 1544 PINCTRL_GRP_SPI0_2_SS0, 1545 PINCTRL_GRP_TTC1_3_WAV, 1546 PINCTRL_GRP_UART1_7, 1547 PINCTRL_GRP_TRACE0_1, 1548 END_OF_GROUPS, 1549 }), 1550 }, 1551 [PINCTRL_PIN_30] = { 1552 .groups = &((uint16_t []) { 1553 PINCTRL_GRP_ETHERNET0_0, 1554 PINCTRL_GRP_PCIE0_1, 1555 PINCTRL_GRP_PMU0_4, 1556 PINCTRL_GRP_TESTSCAN0_0, 1557 PINCTRL_GRP_DPAUX0_1, 1558 PINCTRL_GRP_GPIO0_30, 1559 PINCTRL_GRP_CAN0_7, 1560 PINCTRL_GRP_I2C0_7, 1561 PINCTRL_GRP_SWDT0_4_CLK, 1562 PINCTRL_GRP_SPI0_2, 1563 PINCTRL_GRP_TTC0_3_CLK, 1564 PINCTRL_GRP_UART0_7, 1565 PINCTRL_GRP_TRACE0_1, 1566 END_OF_GROUPS, 1567 }), 1568 }, 1569 [PINCTRL_PIN_31] = { 1570 .groups = &((uint16_t []) { 1571 PINCTRL_GRP_ETHERNET0_0, 1572 PINCTRL_GRP_PCIE0_2, 1573 PINCTRL_GRP_PMU0_5, 1574 PINCTRL_GRP_TESTSCAN0_0, 1575 PINCTRL_GRP_CSU0_9, 1576 PINCTRL_GRP_GPIO0_31, 1577 PINCTRL_GRP_CAN0_7, 1578 PINCTRL_GRP_I2C0_7, 1579 PINCTRL_GRP_SWDT0_4_RST, 1580 PINCTRL_GRP_SPI0_2, 1581 PINCTRL_GRP_TTC0_3_WAV, 1582 PINCTRL_GRP_UART0_7, 1583 PINCTRL_GRP_TRACE0_1, 1584 END_OF_GROUPS, 1585 }), 1586 }, 1587 [PINCTRL_PIN_32] = { 1588 .groups = &((uint16_t []) { 1589 PINCTRL_GRP_ETHERNET0_0, 1590 PINCTRL_GRP_NAND0_1_DQS, 1591 PINCTRL_GRP_PMU0_6, 1592 PINCTRL_GRP_TESTSCAN0_0, 1593 PINCTRL_GRP_CSU0_10, 1594 PINCTRL_GRP_GPIO0_32, 1595 PINCTRL_GRP_CAN1_8, 1596 PINCTRL_GRP_I2C1_8, 1597 PINCTRL_GRP_SWDT1_5_CLK, 1598 PINCTRL_GRP_SPI1_2, 1599 PINCTRL_GRP_TTC3_4_CLK, 1600 PINCTRL_GRP_UART1_8, 1601 PINCTRL_GRP_TRACE0_1, 1602 END_OF_GROUPS, 1603 }), 1604 }, 1605 [PINCTRL_PIN_33] = { 1606 .groups = &((uint16_t []) { 1607 PINCTRL_GRP_ETHERNET0_0, 1608 PINCTRL_GRP_PCIE0_3, 1609 PINCTRL_GRP_PMU0_7, 1610 PINCTRL_GRP_TESTSCAN0_0, 1611 PINCTRL_GRP_CSU0_11, 1612 PINCTRL_GRP_GPIO0_33, 1613 PINCTRL_GRP_CAN1_8, 1614 PINCTRL_GRP_I2C1_8, 1615 PINCTRL_GRP_SWDT1_5_RST, 1616 PINCTRL_GRP_SPI1_2_SS2, 1617 PINCTRL_GRP_TTC3_4_WAV, 1618 PINCTRL_GRP_UART1_8, 1619 PINCTRL_GRP_TRACE0_1, 1620 END_OF_GROUPS, 1621 }), 1622 }, 1623 [PINCTRL_PIN_34] = { 1624 .groups = &((uint16_t []) { 1625 PINCTRL_GRP_ETHERNET0_0, 1626 PINCTRL_GRP_PCIE0_4, 1627 PINCTRL_GRP_PMU0_8, 1628 PINCTRL_GRP_TESTSCAN0_0, 1629 PINCTRL_GRP_DPAUX0_2, 1630 PINCTRL_GRP_GPIO0_34, 1631 PINCTRL_GRP_CAN0_8, 1632 PINCTRL_GRP_I2C0_8, 1633 PINCTRL_GRP_SWDT0_5_CLK, 1634 PINCTRL_GRP_SPI1_2_SS1, 1635 PINCTRL_GRP_TTC2_4_CLK, 1636 PINCTRL_GRP_UART0_8, 1637 PINCTRL_GRP_TRACE0_1, 1638 END_OF_GROUPS, 1639 }), 1640 }, 1641 [PINCTRL_PIN_35] = { 1642 .groups = &((uint16_t []) { 1643 PINCTRL_GRP_ETHERNET0_0, 1644 PINCTRL_GRP_PCIE0_5, 1645 PINCTRL_GRP_PMU0_9, 1646 PINCTRL_GRP_TESTSCAN0_0, 1647 PINCTRL_GRP_DPAUX0_2, 1648 PINCTRL_GRP_GPIO0_35, 1649 PINCTRL_GRP_CAN0_8, 1650 PINCTRL_GRP_I2C0_8, 1651 PINCTRL_GRP_SWDT0_5_RST, 1652 PINCTRL_GRP_SPI1_2_SS0, 1653 PINCTRL_GRP_TTC2_4_WAV, 1654 PINCTRL_GRP_UART0_8, 1655 PINCTRL_GRP_TRACE0_1, 1656 END_OF_GROUPS, 1657 }), 1658 }, 1659 [PINCTRL_PIN_36] = { 1660 .groups = &((uint16_t []) { 1661 PINCTRL_GRP_ETHERNET0_0, 1662 PINCTRL_GRP_PCIE0_6, 1663 PINCTRL_GRP_PMU0_10, 1664 PINCTRL_GRP_TESTSCAN0_0, 1665 PINCTRL_GRP_DPAUX0_3, 1666 PINCTRL_GRP_GPIO0_36, 1667 PINCTRL_GRP_CAN1_9, 1668 PINCTRL_GRP_I2C1_9, 1669 PINCTRL_GRP_SWDT1_6_CLK, 1670 PINCTRL_GRP_SPI1_2, 1671 PINCTRL_GRP_TTC1_4_CLK, 1672 PINCTRL_GRP_UART1_9, 1673 PINCTRL_GRP_TRACE0_1, 1674 END_OF_GROUPS, 1675 }), 1676 }, 1677 [PINCTRL_PIN_37] = { 1678 .groups = &((uint16_t []) { 1679 PINCTRL_GRP_ETHERNET0_0, 1680 PINCTRL_GRP_PCIE0_7, 1681 PINCTRL_GRP_PMU0_11, 1682 PINCTRL_GRP_TESTSCAN0_0, 1683 PINCTRL_GRP_DPAUX0_3, 1684 PINCTRL_GRP_GPIO0_37, 1685 PINCTRL_GRP_CAN1_9, 1686 PINCTRL_GRP_I2C1_9, 1687 PINCTRL_GRP_SWDT1_6_RST, 1688 PINCTRL_GRP_SPI1_2, 1689 PINCTRL_GRP_TTC1_4_WAV, 1690 PINCTRL_GRP_UART1_9, 1691 PINCTRL_GRP_TRACE0_1, 1692 END_OF_GROUPS, 1693 }), 1694 }, 1695 [PINCTRL_PIN_38] = { 1696 .groups = &((uint16_t []) { 1697 PINCTRL_GRP_ETHERNET1_0, 1698 PINCTRL_GRP_RESERVED, 1699 PINCTRL_GRP_SDIO0_1, 1700 PINCTRL_GRP_RESERVED, 1701 PINCTRL_GRP_RESERVED, 1702 PINCTRL_GRP_GPIO0_38, 1703 PINCTRL_GRP_CAN0_9, 1704 PINCTRL_GRP_I2C0_9, 1705 PINCTRL_GRP_PJTAG0_3, 1706 PINCTRL_GRP_SPI0_3, 1707 PINCTRL_GRP_TTC0_4_CLK, 1708 PINCTRL_GRP_UART0_9, 1709 PINCTRL_GRP_TRACE0_1_CLK, 1710 PINCTRL_GRP_SDIO0_4BIT_1_0, 1711 PINCTRL_GRP_SDIO0_4BIT_1_1, 1712 PINCTRL_GRP_SDIO0_1BIT_1_0, 1713 PINCTRL_GRP_SDIO0_1BIT_1_1, 1714 PINCTRL_GRP_SDIO0_1BIT_1_2, 1715 PINCTRL_GRP_SDIO0_1BIT_1_3, 1716 PINCTRL_GRP_SDIO0_1BIT_1_4, 1717 PINCTRL_GRP_SDIO0_1BIT_1_5, 1718 PINCTRL_GRP_SDIO0_1BIT_1_6, 1719 PINCTRL_GRP_SDIO0_1BIT_1_7, 1720 END_OF_GROUPS, 1721 }), 1722 }, 1723 [PINCTRL_PIN_39] = { 1724 .groups = &((uint16_t []) { 1725 PINCTRL_GRP_ETHERNET1_0, 1726 PINCTRL_GRP_RESERVED, 1727 PINCTRL_GRP_SDIO0_1_CD, 1728 PINCTRL_GRP_SDIO1_0, 1729 PINCTRL_GRP_RESERVED, 1730 PINCTRL_GRP_GPIO0_39, 1731 PINCTRL_GRP_CAN0_9, 1732 PINCTRL_GRP_I2C0_9, 1733 PINCTRL_GRP_PJTAG0_3, 1734 PINCTRL_GRP_SPI0_3_SS2, 1735 PINCTRL_GRP_TTC0_4_WAV, 1736 PINCTRL_GRP_UART0_9, 1737 PINCTRL_GRP_TRACE0_1_CLK, 1738 PINCTRL_GRP_SDIO1_4BIT_0_0, 1739 PINCTRL_GRP_SDIO1_1BIT_0_0, 1740 END_OF_GROUPS, 1741 }), 1742 }, 1743 [PINCTRL_PIN_40] = { 1744 .groups = &((uint16_t []) { 1745 PINCTRL_GRP_ETHERNET1_0, 1746 PINCTRL_GRP_RESERVED, 1747 PINCTRL_GRP_SDIO0_1, 1748 PINCTRL_GRP_SDIO1_0, 1749 PINCTRL_GRP_RESERVED, 1750 PINCTRL_GRP_GPIO0_40, 1751 PINCTRL_GRP_CAN1_10, 1752 PINCTRL_GRP_I2C1_10, 1753 PINCTRL_GRP_PJTAG0_3, 1754 PINCTRL_GRP_SPI0_3_SS1, 1755 PINCTRL_GRP_TTC3_5_CLK, 1756 PINCTRL_GRP_UART1_10, 1757 PINCTRL_GRP_TRACE0_1, 1758 PINCTRL_GRP_SDIO0_4BIT_1_0, 1759 PINCTRL_GRP_SDIO0_4BIT_1_1, 1760 PINCTRL_GRP_SDIO0_1BIT_1_0, 1761 PINCTRL_GRP_SDIO0_1BIT_1_1, 1762 PINCTRL_GRP_SDIO0_1BIT_1_2, 1763 PINCTRL_GRP_SDIO0_1BIT_1_3, 1764 PINCTRL_GRP_SDIO0_1BIT_1_4, 1765 PINCTRL_GRP_SDIO0_1BIT_1_5, 1766 PINCTRL_GRP_SDIO0_1BIT_1_6, 1767 PINCTRL_GRP_SDIO0_1BIT_1_7, 1768 PINCTRL_GRP_SDIO1_4BIT_0_0, 1769 PINCTRL_GRP_SDIO1_1BIT_0_1, 1770 END_OF_GROUPS, 1771 }), 1772 }, 1773 [PINCTRL_PIN_41] = { 1774 .groups = &((uint16_t []) { 1775 PINCTRL_GRP_ETHERNET1_0, 1776 PINCTRL_GRP_RESERVED, 1777 PINCTRL_GRP_SDIO0_1, 1778 PINCTRL_GRP_SDIO1_0, 1779 PINCTRL_GRP_RESERVED, 1780 PINCTRL_GRP_GPIO0_41, 1781 PINCTRL_GRP_CAN1_10, 1782 PINCTRL_GRP_I2C1_10, 1783 PINCTRL_GRP_PJTAG0_3, 1784 PINCTRL_GRP_SPI0_3_SS0, 1785 PINCTRL_GRP_TTC3_5_WAV, 1786 PINCTRL_GRP_UART1_10, 1787 PINCTRL_GRP_TRACE0_1, 1788 PINCTRL_GRP_SDIO0_4BIT_1_0, 1789 PINCTRL_GRP_SDIO0_1BIT_1_0, 1790 PINCTRL_GRP_SDIO1_4BIT_0_0, 1791 PINCTRL_GRP_SDIO1_1BIT_0_2, 1792 END_OF_GROUPS, 1793 }), 1794 }, 1795 [PINCTRL_PIN_42] = { 1796 .groups = &((uint16_t []) { 1797 PINCTRL_GRP_ETHERNET1_0, 1798 PINCTRL_GRP_RESERVED, 1799 PINCTRL_GRP_SDIO0_1, 1800 PINCTRL_GRP_SDIO1_0, 1801 PINCTRL_GRP_RESERVED, 1802 PINCTRL_GRP_GPIO0_42, 1803 PINCTRL_GRP_CAN0_10, 1804 PINCTRL_GRP_I2C0_10, 1805 PINCTRL_GRP_SWDT0_6_CLK, 1806 PINCTRL_GRP_SPI0_3, 1807 PINCTRL_GRP_TTC2_5_CLK, 1808 PINCTRL_GRP_UART0_10, 1809 PINCTRL_GRP_TRACE0_1, 1810 PINCTRL_GRP_SDIO0_1, 1811 PINCTRL_GRP_SDIO0_4BIT_1_0, 1812 PINCTRL_GRP_SDIO0_1BIT_1_1, 1813 PINCTRL_GRP_SDIO1_4BIT_0_0, 1814 PINCTRL_GRP_SDIO1_1BIT_0_3, 1815 END_OF_GROUPS, 1816 }), 1817 }, 1818 [PINCTRL_PIN_43] = { 1819 .groups = &((uint16_t []) { 1820 PINCTRL_GRP_ETHERNET1_0, 1821 PINCTRL_GRP_RESERVED, 1822 PINCTRL_GRP_SDIO0_1, 1823 PINCTRL_GRP_SDIO1_0_PC, 1824 PINCTRL_GRP_RESERVED, 1825 PINCTRL_GRP_GPIO0_43, 1826 PINCTRL_GRP_CAN0_10, 1827 PINCTRL_GRP_I2C0_10, 1828 PINCTRL_GRP_SWDT0_6_RST, 1829 PINCTRL_GRP_SPI0_3, 1830 PINCTRL_GRP_TTC2_5_WAV, 1831 PINCTRL_GRP_UART0_10, 1832 PINCTRL_GRP_TRACE0_1, 1833 PINCTRL_GRP_SDIO0_4BIT_1_0, 1834 PINCTRL_GRP_SDIO0_1BIT_1_2, 1835 END_OF_GROUPS, 1836 }), 1837 }, 1838 [PINCTRL_PIN_44] = { 1839 .groups = &((uint16_t []) { 1840 PINCTRL_GRP_ETHERNET1_0, 1841 PINCTRL_GRP_RESERVED, 1842 PINCTRL_GRP_SDIO0_1, 1843 PINCTRL_GRP_SDIO1_0_WP, 1844 PINCTRL_GRP_RESERVED, 1845 PINCTRL_GRP_GPIO0_44, 1846 PINCTRL_GRP_CAN1_11, 1847 PINCTRL_GRP_I2C1_11, 1848 PINCTRL_GRP_SWDT1_7_CLK, 1849 PINCTRL_GRP_SPI1_3, 1850 PINCTRL_GRP_TTC1_5_CLK, 1851 PINCTRL_GRP_UART1_11, 1852 PINCTRL_GRP_RESERVED, 1853 PINCTRL_GRP_SDIO0_4BIT_1_0, 1854 PINCTRL_GRP_SDIO0_1BIT_1_3, 1855 END_OF_GROUPS, 1856 }), 1857 }, 1858 [PINCTRL_PIN_45] = { 1859 .groups = &((uint16_t []) { 1860 PINCTRL_GRP_ETHERNET1_0, 1861 PINCTRL_GRP_RESERVED, 1862 PINCTRL_GRP_SDIO0_1, 1863 PINCTRL_GRP_SDIO1_0_CD, 1864 PINCTRL_GRP_RESERVED, 1865 PINCTRL_GRP_GPIO0_45, 1866 PINCTRL_GRP_CAN1_11, 1867 PINCTRL_GRP_I2C1_11, 1868 PINCTRL_GRP_SWDT1_7_RST, 1869 PINCTRL_GRP_SPI1_3_SS2, 1870 PINCTRL_GRP_TTC1_5_WAV, 1871 PINCTRL_GRP_UART1_11, 1872 PINCTRL_GRP_RESERVED, 1873 PINCTRL_GRP_SDIO0_4BIT_1_1, 1874 PINCTRL_GRP_SDIO0_1BIT_1_4, 1875 END_OF_GROUPS, 1876 }), 1877 }, 1878 [PINCTRL_PIN_46] = { 1879 .groups = &((uint16_t []) { 1880 PINCTRL_GRP_ETHERNET1_0, 1881 PINCTRL_GRP_RESERVED, 1882 PINCTRL_GRP_SDIO0_1, 1883 PINCTRL_GRP_SDIO1_0, 1884 PINCTRL_GRP_RESERVED, 1885 PINCTRL_GRP_GPIO0_46, 1886 PINCTRL_GRP_CAN0_11, 1887 PINCTRL_GRP_I2C0_11, 1888 PINCTRL_GRP_SWDT0_7_CLK, 1889 PINCTRL_GRP_SPI1_3_SS1, 1890 PINCTRL_GRP_TTC0_5_CLK, 1891 PINCTRL_GRP_UART0_11, 1892 PINCTRL_GRP_RESERVED, 1893 PINCTRL_GRP_SDIO0_4BIT_1_1, 1894 PINCTRL_GRP_SDIO0_1BIT_1_5, 1895 PINCTRL_GRP_SDIO1_4BIT_0_1, 1896 PINCTRL_GRP_SDIO1_1BIT_0_4, 1897 END_OF_GROUPS, 1898 }), 1899 }, 1900 [PINCTRL_PIN_47] = { 1901 .groups = &((uint16_t []) { 1902 PINCTRL_GRP_ETHERNET1_0, 1903 PINCTRL_GRP_RESERVED, 1904 PINCTRL_GRP_SDIO0_1, 1905 PINCTRL_GRP_SDIO1_0, 1906 PINCTRL_GRP_RESERVED, 1907 PINCTRL_GRP_GPIO0_47, 1908 PINCTRL_GRP_CAN0_11, 1909 PINCTRL_GRP_I2C0_11, 1910 PINCTRL_GRP_SWDT0_7_RST, 1911 PINCTRL_GRP_SPI1_3_SS0, 1912 PINCTRL_GRP_TTC0_5_WAV, 1913 PINCTRL_GRP_UART0_11, 1914 PINCTRL_GRP_RESERVED, 1915 PINCTRL_GRP_SDIO0_4BIT_1_1, 1916 PINCTRL_GRP_SDIO0_1BIT_1_6, 1917 PINCTRL_GRP_SDIO1_4BIT_0_1, 1918 PINCTRL_GRP_SDIO1_1BIT_0_5, 1919 END_OF_GROUPS, 1920 }), 1921 }, 1922 [PINCTRL_PIN_48] = { 1923 .groups = &((uint16_t []) { 1924 PINCTRL_GRP_ETHERNET1_0, 1925 PINCTRL_GRP_RESERVED, 1926 PINCTRL_GRP_SDIO0_1, 1927 PINCTRL_GRP_SDIO1_0, 1928 PINCTRL_GRP_RESERVED, 1929 PINCTRL_GRP_GPIO0_48, 1930 PINCTRL_GRP_CAN1_12, 1931 PINCTRL_GRP_I2C1_12, 1932 PINCTRL_GRP_SWDT1_8_CLK, 1933 PINCTRL_GRP_SPI1_3, 1934 PINCTRL_GRP_TTC3_6_CLK, 1935 PINCTRL_GRP_UART1_12, 1936 PINCTRL_GRP_RESERVED, 1937 PINCTRL_GRP_SDIO0_4BIT_1_1, 1938 PINCTRL_GRP_SDIO0_1BIT_1_7, 1939 PINCTRL_GRP_SDIO1_4BIT_0_1, 1940 PINCTRL_GRP_SDIO1_1BIT_0_6, 1941 END_OF_GROUPS, 1942 }), 1943 }, 1944 [PINCTRL_PIN_49] = { 1945 .groups = &((uint16_t []) { 1946 PINCTRL_GRP_ETHERNET1_0, 1947 PINCTRL_GRP_RESERVED, 1948 PINCTRL_GRP_SDIO0_1_PC, 1949 PINCTRL_GRP_SDIO1_0, 1950 PINCTRL_GRP_RESERVED, 1951 PINCTRL_GRP_GPIO0_49, 1952 PINCTRL_GRP_CAN1_12, 1953 PINCTRL_GRP_I2C1_12, 1954 PINCTRL_GRP_SWDT1_8_RST, 1955 PINCTRL_GRP_SPI1_3, 1956 PINCTRL_GRP_TTC3_6_WAV, 1957 PINCTRL_GRP_UART1_12, 1958 PINCTRL_GRP_RESERVED, 1959 PINCTRL_GRP_SDIO1_4BIT_0_1, 1960 PINCTRL_GRP_SDIO1_1BIT_0_7, 1961 END_OF_GROUPS, 1962 }), 1963 }, 1964 [PINCTRL_PIN_50] = { 1965 .groups = &((uint16_t []) { 1966 PINCTRL_GRP_GEMTSU0_1, 1967 PINCTRL_GRP_RESERVED, 1968 PINCTRL_GRP_SDIO0_1_WP, 1969 PINCTRL_GRP_SDIO1_0, 1970 PINCTRL_GRP_RESERVED, 1971 PINCTRL_GRP_GPIO0_50, 1972 PINCTRL_GRP_CAN0_12, 1973 PINCTRL_GRP_I2C0_12, 1974 PINCTRL_GRP_SWDT0_8_CLK, 1975 PINCTRL_GRP_MDIO1_0, 1976 PINCTRL_GRP_TTC2_6_CLK, 1977 PINCTRL_GRP_UART0_12, 1978 PINCTRL_GRP_RESERVED, 1979 PINCTRL_GRP_SDIO1_4BIT_0_0, 1980 PINCTRL_GRP_SDIO1_4BIT_0_1, 1981 PINCTRL_GRP_SDIO1_1BIT_0_0, 1982 PINCTRL_GRP_SDIO1_1BIT_0_1, 1983 PINCTRL_GRP_SDIO1_1BIT_0_2, 1984 PINCTRL_GRP_SDIO1_1BIT_0_3, 1985 PINCTRL_GRP_SDIO1_1BIT_0_4, 1986 PINCTRL_GRP_SDIO1_1BIT_0_5, 1987 PINCTRL_GRP_SDIO1_1BIT_0_6, 1988 PINCTRL_GRP_SDIO1_1BIT_0_7, 1989 END_OF_GROUPS, 1990 }), 1991 }, 1992 [PINCTRL_PIN_51] = { 1993 .groups = &((uint16_t []) { 1994 PINCTRL_GRP_GEMTSU0_2, 1995 PINCTRL_GRP_RESERVED, 1996 PINCTRL_GRP_RESERVED, 1997 PINCTRL_GRP_SDIO1_0, 1998 PINCTRL_GRP_RESERVED, 1999 PINCTRL_GRP_GPIO0_51, 2000 PINCTRL_GRP_CAN0_12, 2001 PINCTRL_GRP_I2C0_12, 2002 PINCTRL_GRP_SWDT0_8_RST, 2003 PINCTRL_GRP_MDIO1_0, 2004 PINCTRL_GRP_TTC2_6_WAV, 2005 PINCTRL_GRP_UART0_12, 2006 PINCTRL_GRP_RESERVED, 2007 PINCTRL_GRP_SDIO1_4BIT_0_0, 2008 PINCTRL_GRP_SDIO1_4BIT_0_1, 2009 PINCTRL_GRP_SDIO1_1BIT_0_0, 2010 PINCTRL_GRP_SDIO1_1BIT_0_1, 2011 PINCTRL_GRP_SDIO1_1BIT_0_2, 2012 PINCTRL_GRP_SDIO1_1BIT_0_3, 2013 PINCTRL_GRP_SDIO1_1BIT_0_4, 2014 PINCTRL_GRP_SDIO1_1BIT_0_5, 2015 PINCTRL_GRP_SDIO1_1BIT_0_6, 2016 PINCTRL_GRP_SDIO1_1BIT_0_7, 2017 END_OF_GROUPS, 2018 }), 2019 }, 2020 [PINCTRL_PIN_52] = { 2021 .groups = &((uint16_t []) { 2022 PINCTRL_GRP_ETHERNET2_0, 2023 PINCTRL_GRP_USB0_0, 2024 PINCTRL_GRP_RESERVED, 2025 PINCTRL_GRP_RESERVED, 2026 PINCTRL_GRP_RESERVED, 2027 PINCTRL_GRP_GPIO0_52, 2028 PINCTRL_GRP_CAN1_13, 2029 PINCTRL_GRP_I2C1_13, 2030 PINCTRL_GRP_PJTAG0_4, 2031 PINCTRL_GRP_SPI0_4, 2032 PINCTRL_GRP_TTC1_6_CLK, 2033 PINCTRL_GRP_UART1_13, 2034 PINCTRL_GRP_TRACE0_2_CLK, 2035 END_OF_GROUPS, 2036 }), 2037 }, 2038 [PINCTRL_PIN_53] = { 2039 .groups = &((uint16_t []) { 2040 PINCTRL_GRP_ETHERNET2_0, 2041 PINCTRL_GRP_USB0_0, 2042 PINCTRL_GRP_RESERVED, 2043 PINCTRL_GRP_RESERVED, 2044 PINCTRL_GRP_RESERVED, 2045 PINCTRL_GRP_GPIO0_53, 2046 PINCTRL_GRP_CAN1_13, 2047 PINCTRL_GRP_I2C1_13, 2048 PINCTRL_GRP_PJTAG0_4, 2049 PINCTRL_GRP_SPI0_4_SS2, 2050 PINCTRL_GRP_TTC1_6_WAV, 2051 PINCTRL_GRP_UART1_13, 2052 PINCTRL_GRP_TRACE0_2_CLK, 2053 END_OF_GROUPS, 2054 }), 2055 }, 2056 [PINCTRL_PIN_54] = { 2057 .groups = &((uint16_t []) { 2058 PINCTRL_GRP_ETHERNET2_0, 2059 PINCTRL_GRP_USB0_0, 2060 PINCTRL_GRP_RESERVED, 2061 PINCTRL_GRP_RESERVED, 2062 PINCTRL_GRP_RESERVED, 2063 PINCTRL_GRP_GPIO0_54, 2064 PINCTRL_GRP_CAN0_13, 2065 PINCTRL_GRP_I2C0_13, 2066 PINCTRL_GRP_PJTAG0_4, 2067 PINCTRL_GRP_SPI0_4_SS1, 2068 PINCTRL_GRP_TTC0_6_CLK, 2069 PINCTRL_GRP_UART0_13, 2070 PINCTRL_GRP_TRACE0_2, 2071 END_OF_GROUPS, 2072 }), 2073 }, 2074 [PINCTRL_PIN_55] = { 2075 .groups = &((uint16_t []) { 2076 PINCTRL_GRP_ETHERNET2_0, 2077 PINCTRL_GRP_USB0_0, 2078 PINCTRL_GRP_RESERVED, 2079 PINCTRL_GRP_RESERVED, 2080 PINCTRL_GRP_RESERVED, 2081 PINCTRL_GRP_GPIO0_55, 2082 PINCTRL_GRP_CAN0_13, 2083 PINCTRL_GRP_I2C0_13, 2084 PINCTRL_GRP_PJTAG0_4, 2085 PINCTRL_GRP_SPI0_4_SS0, 2086 PINCTRL_GRP_TTC0_6_WAV, 2087 PINCTRL_GRP_UART0_13, 2088 PINCTRL_GRP_TRACE0_2, 2089 END_OF_GROUPS, 2090 }), 2091 }, 2092 [PINCTRL_PIN_56] = { 2093 .groups = &((uint16_t []) { 2094 PINCTRL_GRP_ETHERNET2_0, 2095 PINCTRL_GRP_USB0_0, 2096 PINCTRL_GRP_RESERVED, 2097 PINCTRL_GRP_RESERVED, 2098 PINCTRL_GRP_RESERVED, 2099 PINCTRL_GRP_GPIO0_56, 2100 PINCTRL_GRP_CAN1_14, 2101 PINCTRL_GRP_I2C1_14, 2102 PINCTRL_GRP_SWDT1_9_CLK, 2103 PINCTRL_GRP_SPI0_4, 2104 PINCTRL_GRP_TTC3_7_CLK, 2105 PINCTRL_GRP_UART1_14, 2106 PINCTRL_GRP_TRACE0_2, 2107 END_OF_GROUPS, 2108 }), 2109 }, 2110 [PINCTRL_PIN_57] = { 2111 .groups = &((uint16_t []) { 2112 PINCTRL_GRP_ETHERNET2_0, 2113 PINCTRL_GRP_USB0_0, 2114 PINCTRL_GRP_RESERVED, 2115 PINCTRL_GRP_RESERVED, 2116 PINCTRL_GRP_RESERVED, 2117 PINCTRL_GRP_GPIO0_57, 2118 PINCTRL_GRP_CAN1_14, 2119 PINCTRL_GRP_I2C1_14, 2120 PINCTRL_GRP_SWDT1_9_RST, 2121 PINCTRL_GRP_SPI0_4, 2122 PINCTRL_GRP_TTC3_7_WAV, 2123 PINCTRL_GRP_UART1_14, 2124 PINCTRL_GRP_TRACE0_2, 2125 END_OF_GROUPS, 2126 }), 2127 }, 2128 [PINCTRL_PIN_58] = { 2129 .groups = &((uint16_t []) { 2130 PINCTRL_GRP_ETHERNET2_0, 2131 PINCTRL_GRP_USB0_0, 2132 PINCTRL_GRP_RESERVED, 2133 PINCTRL_GRP_RESERVED, 2134 PINCTRL_GRP_RESERVED, 2135 PINCTRL_GRP_GPIO0_58, 2136 PINCTRL_GRP_CAN0_14, 2137 PINCTRL_GRP_I2C0_14, 2138 PINCTRL_GRP_PJTAG0_5, 2139 PINCTRL_GRP_SPI1_4, 2140 PINCTRL_GRP_TTC2_7_CLK, 2141 PINCTRL_GRP_UART0_14, 2142 PINCTRL_GRP_TRACE0_2, 2143 END_OF_GROUPS, 2144 }), 2145 }, 2146 [PINCTRL_PIN_59] = { 2147 .groups = &((uint16_t []) { 2148 PINCTRL_GRP_ETHERNET2_0, 2149 PINCTRL_GRP_USB0_0, 2150 PINCTRL_GRP_RESERVED, 2151 PINCTRL_GRP_RESERVED, 2152 PINCTRL_GRP_RESERVED, 2153 PINCTRL_GRP_GPIO0_59, 2154 PINCTRL_GRP_CAN0_14, 2155 PINCTRL_GRP_I2C0_14, 2156 PINCTRL_GRP_PJTAG0_5, 2157 PINCTRL_GRP_SPI1_4_SS2, 2158 PINCTRL_GRP_TTC2_7_WAV, 2159 PINCTRL_GRP_UART0_14, 2160 PINCTRL_GRP_TRACE0_2, 2161 END_OF_GROUPS, 2162 }), 2163 }, 2164 [PINCTRL_PIN_60] = { 2165 .groups = &((uint16_t []) { 2166 PINCTRL_GRP_ETHERNET2_0, 2167 PINCTRL_GRP_USB0_0, 2168 PINCTRL_GRP_RESERVED, 2169 PINCTRL_GRP_RESERVED, 2170 PINCTRL_GRP_RESERVED, 2171 PINCTRL_GRP_GPIO0_60, 2172 PINCTRL_GRP_CAN1_15, 2173 PINCTRL_GRP_I2C1_15, 2174 PINCTRL_GRP_PJTAG0_5, 2175 PINCTRL_GRP_SPI1_4_SS1, 2176 PINCTRL_GRP_TTC1_7_CLK, 2177 PINCTRL_GRP_UART1_15, 2178 PINCTRL_GRP_TRACE0_2, 2179 END_OF_GROUPS, 2180 }), 2181 }, 2182 [PINCTRL_PIN_61] = { 2183 .groups = &((uint16_t []) { 2184 PINCTRL_GRP_ETHERNET2_0, 2185 PINCTRL_GRP_USB0_0, 2186 PINCTRL_GRP_RESERVED, 2187 PINCTRL_GRP_RESERVED, 2188 PINCTRL_GRP_RESERVED, 2189 PINCTRL_GRP_GPIO0_61, 2190 PINCTRL_GRP_CAN1_15, 2191 PINCTRL_GRP_I2C1_15, 2192 PINCTRL_GRP_PJTAG0_5, 2193 PINCTRL_GRP_SPI1_4_SS0, 2194 PINCTRL_GRP_TTC1_7_WAV, 2195 PINCTRL_GRP_UART1_15, 2196 PINCTRL_GRP_TRACE0_2, 2197 END_OF_GROUPS, 2198 }), 2199 }, 2200 [PINCTRL_PIN_62] = { 2201 .groups = &((uint16_t []) { 2202 PINCTRL_GRP_ETHERNET2_0, 2203 PINCTRL_GRP_USB0_0, 2204 PINCTRL_GRP_RESERVED, 2205 PINCTRL_GRP_RESERVED, 2206 PINCTRL_GRP_RESERVED, 2207 PINCTRL_GRP_GPIO0_62, 2208 PINCTRL_GRP_CAN0_15, 2209 PINCTRL_GRP_I2C0_15, 2210 PINCTRL_GRP_SWDT0_9_CLK, 2211 PINCTRL_GRP_SPI1_4, 2212 PINCTRL_GRP_TTC0_7_CLK, 2213 PINCTRL_GRP_UART0_15, 2214 PINCTRL_GRP_TRACE0_2, 2215 END_OF_GROUPS, 2216 }), 2217 }, 2218 [PINCTRL_PIN_63] = { 2219 .groups = &((uint16_t []) { 2220 PINCTRL_GRP_ETHERNET2_0, 2221 PINCTRL_GRP_USB0_0, 2222 PINCTRL_GRP_RESERVED, 2223 PINCTRL_GRP_RESERVED, 2224 PINCTRL_GRP_RESERVED, 2225 PINCTRL_GRP_GPIO0_63, 2226 PINCTRL_GRP_CAN0_15, 2227 PINCTRL_GRP_I2C0_15, 2228 PINCTRL_GRP_SWDT0_9_RST, 2229 PINCTRL_GRP_SPI1_4, 2230 PINCTRL_GRP_TTC0_7_WAV, 2231 PINCTRL_GRP_UART0_15, 2232 PINCTRL_GRP_TRACE0_2, 2233 END_OF_GROUPS, 2234 }), 2235 }, 2236 [PINCTRL_PIN_64] = { 2237 .groups = &((uint16_t []) { 2238 PINCTRL_GRP_ETHERNET3_0, 2239 PINCTRL_GRP_USB1_0, 2240 PINCTRL_GRP_SDIO0_2, 2241 PINCTRL_GRP_RESERVED, 2242 PINCTRL_GRP_RESERVED, 2243 PINCTRL_GRP_GPIO0_64, 2244 PINCTRL_GRP_CAN1_16, 2245 PINCTRL_GRP_I2C1_16, 2246 PINCTRL_GRP_SWDT1_10_CLK, 2247 PINCTRL_GRP_SPI0_5, 2248 PINCTRL_GRP_TTC3_8_CLK, 2249 PINCTRL_GRP_UART1_16, 2250 PINCTRL_GRP_TRACE0_2, 2251 PINCTRL_GRP_SDIO0_4BIT_2_0, 2252 PINCTRL_GRP_SDIO0_4BIT_2_1, 2253 PINCTRL_GRP_SDIO0_1BIT_2_0, 2254 PINCTRL_GRP_SDIO0_1BIT_2_1, 2255 PINCTRL_GRP_SDIO0_1BIT_2_2, 2256 PINCTRL_GRP_SDIO0_1BIT_2_3, 2257 PINCTRL_GRP_SDIO0_1BIT_2_4, 2258 PINCTRL_GRP_SDIO0_1BIT_2_5, 2259 PINCTRL_GRP_SDIO0_1BIT_2_6, 2260 PINCTRL_GRP_SDIO0_1BIT_2_7, 2261 END_OF_GROUPS, 2262 }), 2263 }, 2264 [PINCTRL_PIN_65] = { 2265 .groups = &((uint16_t []) { 2266 PINCTRL_GRP_ETHERNET3_0, 2267 PINCTRL_GRP_USB1_0, 2268 PINCTRL_GRP_SDIO0_2_CD, 2269 PINCTRL_GRP_RESERVED, 2270 PINCTRL_GRP_RESERVED, 2271 PINCTRL_GRP_GPIO0_65, 2272 PINCTRL_GRP_CAN1_16, 2273 PINCTRL_GRP_I2C1_16, 2274 PINCTRL_GRP_SWDT1_10_RST, 2275 PINCTRL_GRP_SPI0_5_SS2, 2276 PINCTRL_GRP_TTC3_8_WAV, 2277 PINCTRL_GRP_UART1_16, 2278 PINCTRL_GRP_TRACE0_2, 2279 END_OF_GROUPS, 2280 }), 2281 }, 2282 [PINCTRL_PIN_66] = { 2283 .groups = &((uint16_t []) { 2284 PINCTRL_GRP_ETHERNET3_0, 2285 PINCTRL_GRP_USB1_0, 2286 PINCTRL_GRP_SDIO0_2, 2287 PINCTRL_GRP_RESERVED, 2288 PINCTRL_GRP_RESERVED, 2289 PINCTRL_GRP_GPIO0_66, 2290 PINCTRL_GRP_CAN0_16, 2291 PINCTRL_GRP_I2C0_16, 2292 PINCTRL_GRP_SWDT0_10_CLK, 2293 PINCTRL_GRP_SPI0_5_SS1, 2294 PINCTRL_GRP_TTC2_8_CLK, 2295 PINCTRL_GRP_UART0_16, 2296 PINCTRL_GRP_TRACE0_2, 2297 PINCTRL_GRP_SDIO0_4BIT_2_0, 2298 PINCTRL_GRP_SDIO0_4BIT_2_1, 2299 PINCTRL_GRP_SDIO0_1BIT_2_0, 2300 PINCTRL_GRP_SDIO0_1BIT_2_1, 2301 PINCTRL_GRP_SDIO0_1BIT_2_2, 2302 PINCTRL_GRP_SDIO0_1BIT_2_3, 2303 PINCTRL_GRP_SDIO0_1BIT_2_4, 2304 PINCTRL_GRP_SDIO0_1BIT_2_5, 2305 PINCTRL_GRP_SDIO0_1BIT_2_6, 2306 PINCTRL_GRP_SDIO0_1BIT_2_7, 2307 END_OF_GROUPS, 2308 }), 2309 }, 2310 [PINCTRL_PIN_67] = { 2311 .groups = &((uint16_t []) { 2312 PINCTRL_GRP_ETHERNET3_0, 2313 PINCTRL_GRP_USB1_0, 2314 PINCTRL_GRP_SDIO0_2, 2315 PINCTRL_GRP_RESERVED, 2316 PINCTRL_GRP_RESERVED, 2317 PINCTRL_GRP_GPIO0_67, 2318 PINCTRL_GRP_CAN0_16, 2319 PINCTRL_GRP_I2C0_16, 2320 PINCTRL_GRP_SWDT0_10_RST, 2321 PINCTRL_GRP_SPI0_5_SS0, 2322 PINCTRL_GRP_TTC2_8_WAV, 2323 PINCTRL_GRP_UART0_16, 2324 PINCTRL_GRP_TRACE0_2, 2325 PINCTRL_GRP_SDIO0_4BIT_2_0, 2326 PINCTRL_GRP_SDIO0_1BIT_2_0, 2327 END_OF_GROUPS, 2328 }), 2329 }, 2330 [PINCTRL_PIN_68] = { 2331 .groups = &((uint16_t []) { 2332 PINCTRL_GRP_ETHERNET3_0, 2333 PINCTRL_GRP_USB1_0, 2334 PINCTRL_GRP_SDIO0_2, 2335 PINCTRL_GRP_RESERVED, 2336 PINCTRL_GRP_RESERVED, 2337 PINCTRL_GRP_GPIO0_68, 2338 PINCTRL_GRP_CAN1_17, 2339 PINCTRL_GRP_I2C1_17, 2340 PINCTRL_GRP_SWDT1_11_CLK, 2341 PINCTRL_GRP_SPI0_5, 2342 PINCTRL_GRP_TTC1_8_CLK, 2343 PINCTRL_GRP_UART1_17, 2344 PINCTRL_GRP_TRACE0_2, 2345 PINCTRL_GRP_SDIO0_4BIT_2_0, 2346 PINCTRL_GRP_SDIO0_1BIT_2_1, 2347 END_OF_GROUPS, 2348 }), 2349 }, 2350 [PINCTRL_PIN_69] = { 2351 .groups = &((uint16_t []) { 2352 PINCTRL_GRP_ETHERNET3_0, 2353 PINCTRL_GRP_USB1_0, 2354 PINCTRL_GRP_SDIO0_2, 2355 PINCTRL_GRP_SDIO1_1_WP, 2356 PINCTRL_GRP_RESERVED, 2357 PINCTRL_GRP_GPIO0_69, 2358 PINCTRL_GRP_CAN1_17, 2359 PINCTRL_GRP_I2C1_17, 2360 PINCTRL_GRP_SWDT1_11_RST, 2361 PINCTRL_GRP_SPI0_5, 2362 PINCTRL_GRP_TTC1_8_WAV, 2363 PINCTRL_GRP_UART1_17, 2364 PINCTRL_GRP_TRACE0_2, 2365 PINCTRL_GRP_SDIO0_4BIT_2_0, 2366 PINCTRL_GRP_SDIO0_1BIT_2_2, 2367 END_OF_GROUPS, 2368 }), 2369 }, 2370 [PINCTRL_PIN_70] = { 2371 .groups = &((uint16_t []) { 2372 PINCTRL_GRP_ETHERNET3_0, 2373 PINCTRL_GRP_USB1_0, 2374 PINCTRL_GRP_SDIO0_2, 2375 PINCTRL_GRP_SDIO1_1_PC, 2376 PINCTRL_GRP_RESERVED, 2377 PINCTRL_GRP_GPIO0_70, 2378 PINCTRL_GRP_CAN0_17, 2379 PINCTRL_GRP_I2C0_17, 2380 PINCTRL_GRP_SWDT0_11_CLK, 2381 PINCTRL_GRP_SPI1_5, 2382 PINCTRL_GRP_TTC0_8_CLK, 2383 PINCTRL_GRP_UART0_17, 2384 PINCTRL_GRP_RESERVED, 2385 PINCTRL_GRP_SDIO0_4BIT_2_0, 2386 PINCTRL_GRP_SDIO0_1BIT_2_3, 2387 END_OF_GROUPS, 2388 }), 2389 }, 2390 [PINCTRL_PIN_71] = { 2391 .groups = &((uint16_t []) { 2392 PINCTRL_GRP_ETHERNET3_0, 2393 PINCTRL_GRP_USB1_0, 2394 PINCTRL_GRP_SDIO0_2, 2395 PINCTRL_GRP_SDIO1_4BIT_1_0, 2396 PINCTRL_GRP_RESERVED, 2397 PINCTRL_GRP_GPIO0_71, 2398 PINCTRL_GRP_CAN0_17, 2399 PINCTRL_GRP_I2C0_17, 2400 PINCTRL_GRP_SWDT0_11_RST, 2401 PINCTRL_GRP_SPI1_5_SS2, 2402 PINCTRL_GRP_TTC0_8_WAV, 2403 PINCTRL_GRP_UART0_17, 2404 PINCTRL_GRP_RESERVED, 2405 PINCTRL_GRP_SDIO0_2, 2406 PINCTRL_GRP_SDIO0_4BIT_2_1, 2407 PINCTRL_GRP_SDIO0_1BIT_2_4, 2408 PINCTRL_GRP_SDIO1_1BIT_1_0, 2409 END_OF_GROUPS, 2410 }), 2411 }, 2412 [PINCTRL_PIN_72] = { 2413 .groups = &((uint16_t []) { 2414 PINCTRL_GRP_ETHERNET3_0, 2415 PINCTRL_GRP_USB1_0, 2416 PINCTRL_GRP_SDIO0_2, 2417 PINCTRL_GRP_SDIO1_4BIT_1_0, 2418 PINCTRL_GRP_RESERVED, 2419 PINCTRL_GRP_GPIO0_72, 2420 PINCTRL_GRP_CAN1_18, 2421 PINCTRL_GRP_I2C1_18, 2422 PINCTRL_GRP_SWDT1_12_CLK, 2423 PINCTRL_GRP_SPI1_5_SS1, 2424 PINCTRL_GRP_RESERVED, 2425 PINCTRL_GRP_UART1_18, 2426 PINCTRL_GRP_RESERVED, 2427 PINCTRL_GRP_SDIO0_4BIT_2_1, 2428 PINCTRL_GRP_SDIO0_1BIT_2_5, 2429 PINCTRL_GRP_SDIO1_1BIT_1_1, 2430 END_OF_GROUPS, 2431 }), 2432 }, 2433 [PINCTRL_PIN_73] = { 2434 .groups = &((uint16_t []) { 2435 PINCTRL_GRP_ETHERNET3_0, 2436 PINCTRL_GRP_USB1_0, 2437 PINCTRL_GRP_SDIO0_2, 2438 PINCTRL_GRP_SDIO1_4BIT_1_0, 2439 PINCTRL_GRP_RESERVED, 2440 PINCTRL_GRP_GPIO0_73, 2441 PINCTRL_GRP_CAN1_18, 2442 PINCTRL_GRP_I2C1_18, 2443 PINCTRL_GRP_SWDT1_12_RST, 2444 PINCTRL_GRP_SPI1_5_SS0, 2445 PINCTRL_GRP_RESERVED, 2446 PINCTRL_GRP_UART1_18, 2447 PINCTRL_GRP_RESERVED, 2448 PINCTRL_GRP_SDIO0_4BIT_2_1, 2449 PINCTRL_GRP_SDIO0_1BIT_2_6, 2450 PINCTRL_GRP_SDIO1_1BIT_1_2, 2451 END_OF_GROUPS, 2452 }), 2453 }, 2454 [PINCTRL_PIN_74] = { 2455 .groups = &((uint16_t []) { 2456 PINCTRL_GRP_ETHERNET3_0, 2457 PINCTRL_GRP_USB1_0, 2458 PINCTRL_GRP_SDIO0_2, 2459 PINCTRL_GRP_SDIO1_4BIT_1_0, 2460 PINCTRL_GRP_RESERVED, 2461 PINCTRL_GRP_GPIO0_74, 2462 PINCTRL_GRP_CAN0_18, 2463 PINCTRL_GRP_I2C0_18, 2464 PINCTRL_GRP_SWDT0_12_CLK, 2465 PINCTRL_GRP_SPI1_5, 2466 PINCTRL_GRP_RESERVED, 2467 PINCTRL_GRP_UART0_18, 2468 PINCTRL_GRP_RESERVED, 2469 PINCTRL_GRP_SDIO0_4BIT_2_1, 2470 PINCTRL_GRP_SDIO0_1BIT_2_7, 2471 PINCTRL_GRP_SDIO1_1BIT_1_3, 2472 END_OF_GROUPS, 2473 }), 2474 }, 2475 [PINCTRL_PIN_75] = { 2476 .groups = &((uint16_t []) { 2477 PINCTRL_GRP_ETHERNET3_0, 2478 PINCTRL_GRP_USB1_0, 2479 PINCTRL_GRP_SDIO0_2_PC, 2480 PINCTRL_GRP_SDIO1_4BIT_1_0, 2481 PINCTRL_GRP_RESERVED, 2482 PINCTRL_GRP_GPIO0_75, 2483 PINCTRL_GRP_CAN0_18, 2484 PINCTRL_GRP_I2C0_18, 2485 PINCTRL_GRP_SWDT0_12_RST, 2486 PINCTRL_GRP_SPI1_5, 2487 PINCTRL_GRP_RESERVED, 2488 PINCTRL_GRP_UART0_18, 2489 PINCTRL_GRP_RESERVED, 2490 PINCTRL_GRP_SDIO1_1BIT_1_0, 2491 PINCTRL_GRP_SDIO1_1BIT_1_1, 2492 PINCTRL_GRP_SDIO1_1BIT_1_2, 2493 PINCTRL_GRP_SDIO1_1BIT_1_3, 2494 END_OF_GROUPS, 2495 }), 2496 }, 2497 [PINCTRL_PIN_76] = { 2498 .groups = &((uint16_t []) { 2499 PINCTRL_GRP_RESERVED, 2500 PINCTRL_GRP_RESERVED, 2501 PINCTRL_GRP_SDIO0_2_WP, 2502 PINCTRL_GRP_SDIO1_4BIT_1_0, 2503 PINCTRL_GRP_RESERVED, 2504 PINCTRL_GRP_GPIO0_76, 2505 PINCTRL_GRP_CAN1_19, 2506 PINCTRL_GRP_I2C1_19, 2507 PINCTRL_GRP_MDIO0_0, 2508 PINCTRL_GRP_MDIO1_1, 2509 PINCTRL_GRP_MDIO2_0, 2510 PINCTRL_GRP_MDIO3_0, 2511 PINCTRL_GRP_RESERVED, 2512 PINCTRL_GRP_SDIO1_1BIT_1_0, 2513 PINCTRL_GRP_SDIO1_1BIT_1_1, 2514 PINCTRL_GRP_SDIO1_1BIT_1_2, 2515 PINCTRL_GRP_SDIO1_1BIT_1_3, 2516 END_OF_GROUPS, 2517 }), 2518 }, 2519 [PINCTRL_PIN_77] = { 2520 .groups = &((uint16_t []) { 2521 PINCTRL_GRP_RESERVED, 2522 PINCTRL_GRP_RESERVED, 2523 PINCTRL_GRP_RESERVED, 2524 PINCTRL_GRP_SDIO1_1_CD, 2525 PINCTRL_GRP_RESERVED, 2526 PINCTRL_GRP_GPIO0_77, 2527 PINCTRL_GRP_CAN1_19, 2528 PINCTRL_GRP_I2C1_19, 2529 PINCTRL_GRP_MDIO0_0, 2530 PINCTRL_GRP_MDIO1_1, 2531 PINCTRL_GRP_MDIO2_0, 2532 PINCTRL_GRP_MDIO3_0, 2533 PINCTRL_GRP_RESERVED, 2534 END_OF_GROUPS, 2535 }), 2536 }, 2537 }; 2538 2539 /** 2540 * pm_api_pinctrl_get_num_pins() - PM call to request number of pins 2541 * @npins Number of pins 2542 * 2543 * This function is used by master to get number of pins 2544 * 2545 * @return Returns success. 2546 */ 2547 enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) 2548 { 2549 *npins = MAX_PIN; 2550 2551 return PM_RET_SUCCESS; 2552 } 2553 2554 /** 2555 * pm_api_pinctrl_get_num_functions() - PM call to request number of functions 2556 * @nfuncs Number of functions 2557 * 2558 * This function is used by master to get number of functions 2559 * 2560 * @return Returns success. 2561 */ 2562 enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) 2563 { 2564 *nfuncs = MAX_FUNCTION; 2565 2566 return PM_RET_SUCCESS; 2567 } 2568 2569 /** 2570 * pm_api_pinctrl_get_num_func_groups() - PM call to request number of 2571 * function groups 2572 * @fid Function Id 2573 * @ngroups Number of function groups 2574 * 2575 * This function is used by master to get number of function groups 2576 * 2577 * @return Returns success. 2578 */ 2579 enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, 2580 unsigned int *ngroups) 2581 { 2582 int i = 0; 2583 uint16_t *grps; 2584 2585 if (fid >= MAX_FUNCTION) 2586 return PM_RET_ERROR_ARGS; 2587 2588 *ngroups = 0; 2589 2590 grps = *pinctrl_functions[fid].groups; 2591 if (grps == NULL) 2592 return PM_RET_SUCCESS; 2593 2594 while (grps[i++] != (uint16_t)END_OF_GROUPS) 2595 (*ngroups)++; 2596 2597 return PM_RET_SUCCESS; 2598 } 2599 2600 /** 2601 * pm_api_pinctrl_get_function_name() - PM call to request a function name 2602 * @fid Function ID 2603 * @name Name of function (max 16 bytes) 2604 * 2605 * This function is used by master to get name of function specified 2606 * by given function ID. 2607 * 2608 * @return Returns success. In case of error, name data is 0. 2609 */ 2610 enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid, 2611 char *name) 2612 { 2613 if (fid >= MAX_FUNCTION) 2614 memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); 2615 else 2616 memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); 2617 2618 return PM_RET_SUCCESS; 2619 } 2620 2621 /** 2622 * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function 2623 * groups of function Id 2624 * @fid Function ID 2625 * @index Index of next function groups 2626 * @groups Function groups 2627 * 2628 * This function is used by master to get function groups specified 2629 * by given function Id. This API will return 6 function groups with 2630 * a single response. To get other function groups, master should call 2631 * same API in loop with new function groups index till error is returned. 2632 * 2633 * E.g First call should have index 0 which will return function groups 2634 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2635 * function groups 6, 7, 8, 9, 10 and 11 and so on. 2636 * 2637 * Return: Returns status, either success or error+reason. 2638 */ 2639 enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, 2640 unsigned int index, 2641 uint16_t *groups) 2642 { 2643 unsigned int i; 2644 uint16_t *grps; 2645 2646 if (fid >= MAX_FUNCTION) 2647 return PM_RET_ERROR_ARGS; 2648 2649 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2650 2651 grps = *pinctrl_functions[fid].groups; 2652 if (grps == NULL) 2653 return PM_RET_SUCCESS; 2654 2655 /* Skip groups till index */ 2656 for (i = 0; i < index; i++) 2657 if (grps[i] == (uint16_t)END_OF_GROUPS) 2658 return PM_RET_SUCCESS; 2659 2660 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { 2661 groups[i] = grps[index + i]; 2662 if (groups[i] == (uint16_t)END_OF_GROUPS) 2663 break; 2664 } 2665 2666 return PM_RET_SUCCESS; 2667 } 2668 2669 /** 2670 * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin 2671 * groups of pin 2672 * @pin Pin 2673 * @index Index of next pin groups 2674 * @groups pin groups 2675 * 2676 * This function is used by master to get pin groups specified 2677 * by given pin Id. This API will return 6 pin groups with 2678 * a single response. To get other pin groups, master should call 2679 * same API in loop with new pin groups index till error is returned. 2680 * 2681 * E.g First call should have index 0 which will return pin groups 2682 * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return 2683 * pin groups 6, 7, 8, 9, 10 and 11 and so on. 2684 * 2685 * Return: Returns status, either success or error+reason. 2686 */ 2687 enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, 2688 unsigned int index, 2689 uint16_t *groups) 2690 { 2691 unsigned int i; 2692 uint16_t *grps; 2693 2694 if (pin >= MAX_PIN) 2695 return PM_RET_ERROR_ARGS; 2696 2697 memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); 2698 2699 grps = *zynqmp_pin_groups[pin].groups; 2700 if (!grps) 2701 return PM_RET_SUCCESS; 2702 2703 /* Skip groups till index */ 2704 for (i = 0; i < index; i++) 2705 if (grps[i] == (uint16_t)END_OF_GROUPS) 2706 return PM_RET_SUCCESS; 2707 2708 for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { 2709 groups[i] = grps[index + i]; 2710 if (groups[i] == (uint16_t)END_OF_GROUPS) 2711 break; 2712 } 2713 2714 return PM_RET_SUCCESS; 2715 } 2716 2717 /** 2718 * pm_api_pinctrl_get_function() - Read function id set for the given pin 2719 * @pin Pin number 2720 * @nid Node ID of function currently set for given pin 2721 * 2722 * This function provides the function currently set for the given pin. 2723 * 2724 * @return Returns status, either success or error+reason 2725 */ 2726 enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin, 2727 unsigned int *id) 2728 { 2729 unsigned int i = 0, j = 0; 2730 enum pm_ret_status ret = PM_RET_SUCCESS; 2731 unsigned int ctrlreg, val, gid; 2732 uint16_t *grps; 2733 2734 ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; 2735 ret = pm_mmio_read(ctrlreg, &val); 2736 if (ret != PM_RET_SUCCESS) 2737 return ret; 2738 2739 val &= PINCTRL_FUNCTION_MASK; 2740 2741 for (i = 0; i < NFUNCS_PER_PIN; i++) 2742 if (val == pm_pinctrl_mux[i]) 2743 break; 2744 2745 if (i == NFUNCS_PER_PIN) 2746 return PM_RET_ERROR_NOTSUPPORTED; 2747 2748 gid = *(*zynqmp_pin_groups[pin].groups + i); 2749 2750 for (i = 0; i < MAX_FUNCTION; i++) { 2751 grps = *pinctrl_functions[i].groups; 2752 if (grps == NULL) 2753 continue; 2754 if (val != pinctrl_functions[i].regval) 2755 continue; 2756 2757 for (j = 0; grps[j] != (uint16_t)END_OF_GROUPS; j++) { 2758 if (gid == grps[j]) { 2759 *id = i; 2760 goto done; 2761 } 2762 } 2763 } 2764 if (i == MAX_FUNCTION) 2765 ret = PM_RET_ERROR_ARGS; 2766 done: 2767 return ret; 2768 } 2769 2770 /** 2771 * pm_api_pinctrl_set_function() - Set function id set for the given pin 2772 * @pin Pin number 2773 * @nid Node ID of function to set for given pin 2774 * 2775 * This function provides the function currently set for the given pin. 2776 * 2777 * @return Returns status, either success or error+reason 2778 */ 2779 enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin, 2780 unsigned int fid) 2781 { 2782 int i, j; 2783 unsigned int ctrlreg, val; 2784 uint16_t *pgrps, *fgrps; 2785 2786 ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; 2787 val = pinctrl_functions[fid].regval; 2788 2789 for (i = 0; i < NFUNCS_PER_PIN; i++) 2790 if (val == pm_pinctrl_mux[i]) 2791 break; 2792 2793 if (i == NFUNCS_PER_PIN) 2794 return PM_RET_ERROR_NOTSUPPORTED; 2795 2796 pgrps = *zynqmp_pin_groups[pin].groups; 2797 if (!pgrps) 2798 return PM_RET_ERROR_NOTSUPPORTED; 2799 2800 fgrps = *pinctrl_functions[fid].groups; 2801 if (!fgrps) 2802 return PM_RET_ERROR_NOTSUPPORTED; 2803 2804 for (i = 0; fgrps[i] != (uint16_t)END_OF_GROUPS; i++) 2805 for (j = 0; pgrps[j] != (uint16_t)END_OF_GROUPS; j++) 2806 if (fgrps[i] == pgrps[j]) 2807 goto match; 2808 2809 return PM_RET_ERROR_NOTSUPPORTED; 2810 2811 match: 2812 return pm_mmio_write(ctrlreg, PINCTRL_FUNCTION_MASK, val); 2813 } 2814 2815 /** 2816 * pm_api_pinctrl_set_config() - Set configuration parameter for given pin 2817 * @pin: Pin for which configuration is to be set 2818 * @param: Configuration parameter to be set 2819 * @value: Value to be set for configuration parameter 2820 * 2821 * This function sets value of requested configuration parameter for given pin. 2822 * 2823 * @return Returns status, either success or error+reason 2824 */ 2825 enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin, 2826 unsigned int param, 2827 unsigned int value) 2828 { 2829 enum pm_ret_status ret; 2830 unsigned int ctrlreg, mask, val, offset; 2831 2832 if (param >= PINCTRL_CONFIG_MAX) 2833 return PM_RET_ERROR_NOTSUPPORTED; 2834 2835 if (pin >= PINCTRL_NUM_MIOS) 2836 return PM_RET_ERROR_ARGS; 2837 2838 mask = 1 << PINCTRL_PIN_OFFSET(pin); 2839 2840 switch (param) { 2841 case PINCTRL_CONFIG_SLEW_RATE: 2842 if (value != PINCTRL_SLEW_RATE_FAST && 2843 value != PINCTRL_SLEW_RATE_SLOW) 2844 return PM_RET_ERROR_ARGS; 2845 2846 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2847 PINCTRL_SLEWCTRL_REG_OFFSET, 2848 pin); 2849 val = value << PINCTRL_PIN_OFFSET(pin); 2850 ret = pm_mmio_write(ctrlreg, mask, val); 2851 break; 2852 case PINCTRL_CONFIG_BIAS_STATUS: 2853 if (value != PINCTRL_BIAS_ENABLE && 2854 value != PINCTRL_BIAS_DISABLE) 2855 return PM_RET_ERROR_ARGS; 2856 2857 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2858 PINCTRL_PULLSTAT_REG_OFFSET, 2859 pin); 2860 2861 offset = PINCTRL_PIN_OFFSET(pin); 2862 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2863 offset = (offset < 12U) ? 2864 (offset + 14U) : (offset - 12U); 2865 2866 val = value << offset; 2867 mask = 1 << offset; 2868 ret = pm_mmio_write(ctrlreg, mask, val); 2869 break; 2870 case PINCTRL_CONFIG_PULL_CTRL: 2871 2872 if (value != PINCTRL_BIAS_PULL_DOWN && 2873 value != PINCTRL_BIAS_PULL_UP) 2874 return PM_RET_ERROR_ARGS; 2875 2876 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2877 PINCTRL_PULLSTAT_REG_OFFSET, 2878 pin); 2879 2880 offset = PINCTRL_PIN_OFFSET(pin); 2881 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2882 offset = (offset < 12U) ? 2883 (offset + 14U) : (offset - 12U); 2884 2885 val = PINCTRL_BIAS_ENABLE << offset; 2886 ret = pm_mmio_write(ctrlreg, 1 << offset, val); 2887 if (ret != PM_RET_SUCCESS) 2888 return ret; 2889 2890 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2891 PINCTRL_PULLCTRL_REG_OFFSET, 2892 pin); 2893 val = value << PINCTRL_PIN_OFFSET(pin); 2894 ret = pm_mmio_write(ctrlreg, mask, val); 2895 break; 2896 case PINCTRL_CONFIG_SCHMITT_CMOS: 2897 if (value != PINCTRL_INPUT_TYPE_CMOS && 2898 value != PINCTRL_INPUT_TYPE_SCHMITT) 2899 return PM_RET_ERROR_ARGS; 2900 2901 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2902 PINCTRL_SCHCMOS_REG_OFFSET, 2903 pin); 2904 2905 val = value << PINCTRL_PIN_OFFSET(pin); 2906 ret = pm_mmio_write(ctrlreg, mask, val); 2907 break; 2908 case PINCTRL_CONFIG_DRIVE_STRENGTH: 2909 if (value > PINCTRL_DRIVE_STRENGTH_12MA) 2910 return PM_RET_ERROR_ARGS; 2911 2912 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2913 PINCTRL_DRVSTRN0_REG_OFFSET, 2914 pin); 2915 val = (value >> 1) << PINCTRL_PIN_OFFSET(pin); 2916 ret = pm_mmio_write(ctrlreg, mask, val); 2917 if (ret) 2918 return ret; 2919 2920 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2921 PINCTRL_DRVSTRN1_REG_OFFSET, 2922 pin); 2923 val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin); 2924 ret = pm_mmio_write(ctrlreg, mask, val); 2925 break; 2926 default: 2927 ERROR("Invalid parameter %u\n", param); 2928 ret = PM_RET_ERROR_NOTSUPPORTED; 2929 break; 2930 } 2931 2932 return ret; 2933 } 2934 2935 /** 2936 * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin 2937 * @pin: Pin for which configuration is to be read 2938 * @param: Configuration parameter to be read 2939 * @value: buffer to store value of configuration parameter 2940 * 2941 * This function reads value of requested configuration parameter for given pin. 2942 * 2943 * @return Returns status, either success or error+reason 2944 */ 2945 enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin, 2946 unsigned int param, 2947 unsigned int *value) 2948 { 2949 enum pm_ret_status ret; 2950 unsigned int ctrlreg, val; 2951 2952 if (param >= PINCTRL_CONFIG_MAX) 2953 return PM_RET_ERROR_NOTSUPPORTED; 2954 2955 if (pin >= PINCTRL_NUM_MIOS) 2956 return PM_RET_ERROR_ARGS; 2957 2958 switch (param) { 2959 case PINCTRL_CONFIG_SLEW_RATE: 2960 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2961 PINCTRL_SLEWCTRL_REG_OFFSET, 2962 pin); 2963 2964 ret = pm_mmio_read(ctrlreg, &val); 2965 if (ret != PM_RET_SUCCESS) 2966 return ret; 2967 2968 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2969 break; 2970 case PINCTRL_CONFIG_BIAS_STATUS: 2971 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2972 PINCTRL_PULLSTAT_REG_OFFSET, 2973 pin); 2974 2975 ret = pm_mmio_read(ctrlreg, &val); 2976 if (ret) 2977 return ret; 2978 2979 if (ctrlreg == IOU_SLCR_BANK1_CTRL5) 2980 val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF); 2981 2982 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2983 break; 2984 case PINCTRL_CONFIG_PULL_CTRL: 2985 2986 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2987 PINCTRL_PULLCTRL_REG_OFFSET, 2988 pin); 2989 2990 ret = pm_mmio_read(ctrlreg, &val); 2991 if (ret) 2992 return ret; 2993 2994 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 2995 break; 2996 case PINCTRL_CONFIG_SCHMITT_CMOS: 2997 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 2998 PINCTRL_SCHCMOS_REG_OFFSET, 2999 pin); 3000 3001 ret = pm_mmio_read(ctrlreg, &val); 3002 if (ret) 3003 return ret; 3004 3005 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 3006 break; 3007 case PINCTRL_CONFIG_DRIVE_STRENGTH: 3008 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 3009 PINCTRL_DRVSTRN0_REG_OFFSET, 3010 pin); 3011 ret = pm_mmio_read(ctrlreg, &val); 3012 if (ret) 3013 return ret; 3014 3015 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1; 3016 3017 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 3018 PINCTRL_DRVSTRN1_REG_OFFSET, 3019 pin); 3020 ret = pm_mmio_read(ctrlreg, &val); 3021 if (ret) 3022 return ret; 3023 3024 *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 3025 break; 3026 case PINCTRL_CONFIG_VOLTAGE_STATUS: 3027 ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 3028 PINCTRL_VOLTAGE_STAT_REG_OFFSET, 3029 pin); 3030 3031 ret = pm_mmio_read(ctrlreg, &val); 3032 if (ret) 3033 return ret; 3034 3035 *value = val & PINCTRL_VOLTAGE_STATUS_MASK; 3036 break; 3037 default: 3038 return PM_RET_ERROR_NOTSUPPORTED; 3039 } 3040 3041 return PM_RET_SUCCESS; 3042 } 3043