1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for clock control. 9 */ 10 11 #ifndef PM_API_CLOCK_H 12 #define PM_API_CLOCK_H 13 14 #include <lib/utils_def.h> 15 16 #include "pm_common.h" 17 18 #define CLK_NAME_LEN U(15) 19 #define MAX_PARENTS U(100) 20 #define CLK_NA_PARENT -1 21 #define CLK_DUMMY_PARENT -2 22 23 /* Flags for parent id */ 24 #define PARENT_CLK_SELF U(0) 25 #define PARENT_CLK_NODE1 U(1) 26 #define PARENT_CLK_NODE2 U(2) 27 #define PARENT_CLK_NODE3 U(3) 28 #define PARENT_CLK_NODE4 U(4) 29 #define PARENT_CLK_EXTERNAL U(5) 30 #define PARENT_CLK_MIO0_MIO77 U(6) 31 32 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 33 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 34 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 35 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 36 /* unused */ 37 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 38 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 39 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 40 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 41 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 42 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 43 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 44 /* parents need enable during gate/ungate, set rate and re-parent */ 45 #define CLK_OPS_PARENT_ENABLE BIT(12) 46 #define CLK_FRAC BIT(13) 47 48 #define CLK_DIVIDER_ONE_BASED BIT(0) 49 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 50 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 51 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 52 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 53 #define CLK_DIVIDER_READ_ONLY BIT(5) 54 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 55 56 #define END_OF_CLK "END_OF_CLK" 57 58 //CLock Ids 59 enum clock_id { 60 CLK_IOPLL, 61 CLK_RPLL, 62 CLK_APLL, 63 CLK_DPLL, 64 CLK_VPLL, 65 CLK_IOPLL_TO_FPD, 66 CLK_RPLL_TO_FPD, 67 CLK_APLL_TO_LPD, 68 CLK_DPLL_TO_LPD, 69 CLK_VPLL_TO_LPD, 70 CLK_ACPU, 71 CLK_ACPU_HALF, 72 CLK_DBG_FPD, 73 CLK_DBG_LPD, 74 CLK_DBG_TRACE, 75 CLK_DBG_TSTMP, 76 CLK_DP_VIDEO_REF, 77 CLK_DP_AUDIO_REF, 78 CLK_DP_STC_REF, 79 CLK_GDMA_REF, 80 CLK_DPDMA_REF, 81 CLK_DDR_REF, 82 CLK_SATA_REF, 83 CLK_PCIE_REF, 84 CLK_GPU_REF, 85 CLK_GPU_PP0_REF, 86 CLK_GPU_PP1_REF, 87 CLK_TOPSW_MAIN, 88 CLK_TOPSW_LSBUS, 89 CLK_GTGREF0_REF, 90 CLK_LPD_SWITCH, 91 CLK_LPD_LSBUS, 92 CLK_USB0_BUS_REF, 93 CLK_USB1_BUS_REF, 94 CLK_USB3_DUAL_REF, 95 CLK_USB0, 96 CLK_USB1, 97 CLK_CPU_R5, 98 CLK_CPU_R5_CORE, 99 CLK_CSU_SPB, 100 CLK_CSU_PLL, 101 CLK_PCAP, 102 CLK_IOU_SWITCH, 103 CLK_GEM_TSU_REF, 104 CLK_GEM_TSU, 105 CLK_GEM0_REF, 106 CLK_GEM1_REF, 107 CLK_GEM2_REF, 108 CLK_GEM3_REF, 109 CLK_GEM0_TX, 110 CLK_GEM1_TX, 111 CLK_GEM2_TX, 112 CLK_GEM3_TX, 113 CLK_QSPI_REF, 114 CLK_SDIO0_REF, 115 CLK_SDIO1_REF, 116 CLK_UART0_REF, 117 CLK_UART1_REF, 118 CLK_SPI0_REF, 119 CLK_SPI1_REF, 120 CLK_NAND_REF, 121 CLK_I2C0_REF, 122 CLK_I2C1_REF, 123 CLK_CAN0_REF, 124 CLK_CAN1_REF, 125 CLK_CAN0, 126 CLK_CAN1, 127 CLK_DLL_REF, 128 CLK_ADMA_REF, 129 CLK_TIMESTAMP_REF, 130 CLK_AMS_REF, 131 CLK_PL0_REF, 132 CLK_PL1_REF, 133 CLK_PL2_REF, 134 CLK_PL3_REF, 135 CLK_WDT, 136 CLK_IOPLL_INT, 137 CLK_IOPLL_PRE_SRC, 138 CLK_IOPLL_HALF, 139 CLK_IOPLL_INT_MUX, 140 CLK_IOPLL_POST_SRC, 141 CLK_RPLL_INT, 142 CLK_RPLL_PRE_SRC, 143 CLK_RPLL_HALF, 144 CLK_RPLL_INT_MUX, 145 CLK_RPLL_POST_SRC, 146 CLK_APLL_INT, 147 CLK_APLL_PRE_SRC, 148 CLK_APLL_HALF, 149 CLK_APLL_INT_MUX, 150 CLK_APLL_POST_SRC, 151 CLK_DPLL_INT, 152 CLK_DPLL_PRE_SRC, 153 CLK_DPLL_HALF, 154 CLK_DPLL_INT_MUX, 155 CLK_DPLL_POST_SRC, 156 CLK_VPLL_INT, 157 CLK_VPLL_PRE_SRC, 158 CLK_VPLL_HALF, 159 CLK_VPLL_INT_MUX, 160 CLK_VPLL_POST_SRC, 161 CLK_CAN0_MIO, 162 CLK_CAN1_MIO, 163 CLK_ACPU_FULL, 164 END_OF_OUTPUT_CLKS, 165 }; 166 167 #define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS) 168 169 //External clock ids 170 enum { 171 EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS, 172 EXT_CLK_VIDEO, 173 EXT_CLK_PSS_ALT_REF, 174 EXT_CLK_AUX_REF, 175 EXT_CLK_GT_CRX_REF, 176 EXT_CLK_SWDT0, 177 EXT_CLK_SWDT1, 178 EXT_CLK_GEM0_EMIO, 179 EXT_CLK_GEM1_EMIO, 180 EXT_CLK_GEM2_EMIO, 181 EXT_CLK_GEM3_EMIO, 182 EXT_CLK_MIO50_OR_MIO51, 183 EXT_CLK_MIO0, 184 EXT_CLK_MIO1, 185 EXT_CLK_MIO2, 186 EXT_CLK_MIO3, 187 EXT_CLK_MIO4, 188 EXT_CLK_MIO5, 189 EXT_CLK_MIO6, 190 EXT_CLK_MIO7, 191 EXT_CLK_MIO8, 192 EXT_CLK_MIO9, 193 EXT_CLK_MIO10, 194 EXT_CLK_MIO11, 195 EXT_CLK_MIO12, 196 EXT_CLK_MIO13, 197 EXT_CLK_MIO14, 198 EXT_CLK_MIO15, 199 EXT_CLK_MIO16, 200 EXT_CLK_MIO17, 201 EXT_CLK_MIO18, 202 EXT_CLK_MIO19, 203 EXT_CLK_MIO20, 204 EXT_CLK_MIO21, 205 EXT_CLK_MIO22, 206 EXT_CLK_MIO23, 207 EXT_CLK_MIO24, 208 EXT_CLK_MIO25, 209 EXT_CLK_MIO26, 210 EXT_CLK_MIO27, 211 EXT_CLK_MIO28, 212 EXT_CLK_MIO29, 213 EXT_CLK_MIO30, 214 EXT_CLK_MIO31, 215 EXT_CLK_MIO32, 216 EXT_CLK_MIO33, 217 EXT_CLK_MIO34, 218 EXT_CLK_MIO35, 219 EXT_CLK_MIO36, 220 EXT_CLK_MIO37, 221 EXT_CLK_MIO38, 222 EXT_CLK_MIO39, 223 EXT_CLK_MIO40, 224 EXT_CLK_MIO41, 225 EXT_CLK_MIO42, 226 EXT_CLK_MIO43, 227 EXT_CLK_MIO44, 228 EXT_CLK_MIO45, 229 EXT_CLK_MIO46, 230 EXT_CLK_MIO47, 231 EXT_CLK_MIO48, 232 EXT_CLK_MIO49, 233 EXT_CLK_MIO50, 234 EXT_CLK_MIO51, 235 EXT_CLK_MIO52, 236 EXT_CLK_MIO53, 237 EXT_CLK_MIO54, 238 EXT_CLK_MIO55, 239 EXT_CLK_MIO56, 240 EXT_CLK_MIO57, 241 EXT_CLK_MIO58, 242 EXT_CLK_MIO59, 243 EXT_CLK_MIO60, 244 EXT_CLK_MIO61, 245 EXT_CLK_MIO62, 246 EXT_CLK_MIO63, 247 EXT_CLK_MIO64, 248 EXT_CLK_MIO65, 249 EXT_CLK_MIO66, 250 EXT_CLK_MIO67, 251 EXT_CLK_MIO68, 252 EXT_CLK_MIO69, 253 EXT_CLK_MIO70, 254 EXT_CLK_MIO71, 255 EXT_CLK_MIO72, 256 EXT_CLK_MIO73, 257 EXT_CLK_MIO74, 258 EXT_CLK_MIO75, 259 EXT_CLK_MIO76, 260 EXT_CLK_MIO77, 261 END_OF_CLKS, 262 }; 263 264 #define CLK_MAX (unsigned int)(END_OF_CLKS) 265 266 //CLock types 267 #define CLK_TYPE_OUTPUT 0U 268 #define CLK_TYPE_EXTERNAL 1U 269 270 //Topology types 271 #define TYPE_INVALID 0U 272 #define TYPE_MUX 1U 273 #define TYPE_PLL 2U 274 #define TYPE_FIXEDFACTOR 3U 275 #define TYPE_DIV1 4U 276 #define TYPE_DIV2 5U 277 #define TYPE_GATE 6U 278 279 struct pm_pll; 280 struct pm_pll *pm_clock_get_pll(enum clock_id clock_id); 281 struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id); 282 uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id); 283 284 enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name); 285 enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks); 286 enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, 287 unsigned int index, 288 uint32_t *topology); 289 enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, 290 uint32_t *mul, 291 uint32_t *div); 292 enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, 293 unsigned int index, 294 uint32_t *parents); 295 enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, 296 uint32_t *attr); 297 298 enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id, 299 enum pm_node_id *node_id); 300 enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id); 301 302 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll); 303 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll); 304 enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, 305 unsigned int *state); 306 enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, 307 enum clock_id clock_id, 308 unsigned int parent_index); 309 enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll, 310 enum clock_id clock_id, 311 unsigned int *parent_index); 312 enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, 313 unsigned int mode); 314 enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id, 315 unsigned int *mode); 316 317 #endif /* PM_API_CLOCK_H */ 318