1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for clock control. 9 */ 10 11 #ifndef _PM_API_CLOCK_H_ 12 #define _PM_API_CLOCK_H_ 13 14 #include <utils_def.h> 15 #include "pm_common.h" 16 17 #define CLK_NAME_LEN U(15) 18 #define MAX_PARENTS U(100) 19 #define CLK_NA_PARENT -1 20 #define CLK_DUMMY_PARENT -2 21 22 /* Flags for parent id */ 23 #define PARENT_CLK_SELF U(0) 24 #define PARENT_CLK_NODE1 U(1) 25 #define PARENT_CLK_NODE2 U(2) 26 #define PARENT_CLK_NODE3 U(3) 27 #define PARENT_CLK_NODE4 U(4) 28 #define PARENT_CLK_EXTERNAL U(5) 29 #define PARENT_CLK_MIO0_MIO77 U(6) 30 31 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 32 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 33 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 34 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 35 /* unused */ 36 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 37 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 38 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 39 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 40 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 41 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 42 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 43 /* parents need enable during gate/ungate, set rate and re-parent */ 44 #define CLK_OPS_PARENT_ENABLE BIT(12) 45 #define CLK_FRAC BIT(13) 46 47 #define CLK_DIVIDER_ONE_BASED BIT(0) 48 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 49 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 50 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 51 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 52 #define CLK_DIVIDER_READ_ONLY BIT(5) 53 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 54 55 #define END_OF_CLK "END_OF_CLK" 56 57 //CLock Ids 58 enum { 59 CLK_IOPLL, 60 CLK_RPLL, 61 CLK_APLL, 62 CLK_DPLL, 63 CLK_VPLL, 64 CLK_IOPLL_TO_FPD, 65 CLK_RPLL_TO_FPD, 66 CLK_APLL_TO_LPD, 67 CLK_DPLL_TO_LPD, 68 CLK_VPLL_TO_LPD, 69 CLK_ACPU, 70 CLK_ACPU_HALF, 71 CLK_DBG_FPD, 72 CLK_DBG_LPD, 73 CLK_DBG_TRACE, 74 CLK_DBG_TSTMP, 75 CLK_DP_VIDEO_REF, 76 CLK_DP_AUDIO_REF, 77 CLK_DP_STC_REF, 78 CLK_GDMA_REF, 79 CLK_DPDMA_REF, 80 CLK_DDR_REF, 81 CLK_SATA_REF, 82 CLK_PCIE_REF, 83 CLK_GPU_REF, 84 CLK_GPU_PP0_REF, 85 CLK_GPU_PP1_REF, 86 CLK_TOPSW_MAIN, 87 CLK_TOPSW_LSBUS, 88 CLK_GTGREF0_REF, 89 CLK_LPD_SWITCH, 90 CLK_LPD_LSBUS, 91 CLK_USB0_BUS_REF, 92 CLK_USB1_BUS_REF, 93 CLK_USB3_DUAL_REF, 94 CLK_USB0, 95 CLK_USB1, 96 CLK_CPU_R5, 97 CLK_CPU_R5_CORE, 98 CLK_CSU_SPB, 99 CLK_CSU_PLL, 100 CLK_PCAP, 101 CLK_IOU_SWITCH, 102 CLK_GEM_TSU_REF, 103 CLK_GEM_TSU, 104 CLK_GEM0_REF, 105 CLK_GEM1_REF, 106 CLK_GEM2_REF, 107 CLK_GEM3_REF, 108 CLK_GEM0_TX, 109 CLK_GEM1_TX, 110 CLK_GEM2_TX, 111 CLK_GEM3_TX, 112 CLK_QSPI_REF, 113 CLK_SDIO0_REF, 114 CLK_SDIO1_REF, 115 CLK_UART0_REF, 116 CLK_UART1_REF, 117 CLK_SPI0_REF, 118 CLK_SPI1_REF, 119 CLK_NAND_REF, 120 CLK_I2C0_REF, 121 CLK_I2C1_REF, 122 CLK_CAN0_REF, 123 CLK_CAN1_REF, 124 CLK_CAN0, 125 CLK_CAN1, 126 CLK_DLL_REF, 127 CLK_ADMA_REF, 128 CLK_TIMESTAMP_REF, 129 CLK_AMS_REF, 130 CLK_PL0_REF, 131 CLK_PL1_REF, 132 CLK_PL2_REF, 133 CLK_PL3_REF, 134 CLK_WDT, 135 CLK_IOPLL_INT, 136 CLK_IOPLL_PRE_SRC, 137 CLK_IOPLL_HALF, 138 CLK_IOPLL_INT_MUX, 139 CLK_IOPLL_POST_SRC, 140 CLK_RPLL_INT, 141 CLK_RPLL_PRE_SRC, 142 CLK_RPLL_HALF, 143 CLK_RPLL_INT_MUX, 144 CLK_RPLL_POST_SRC, 145 CLK_APLL_INT, 146 CLK_APLL_PRE_SRC, 147 CLK_APLL_HALF, 148 CLK_APLL_INT_MUX, 149 CLK_APLL_POST_SRC, 150 CLK_DPLL_INT, 151 CLK_DPLL_PRE_SRC, 152 CLK_DPLL_HALF, 153 CLK_DPLL_INT_MUX, 154 CLK_DPLL_POST_SRC, 155 CLK_VPLL_INT, 156 CLK_VPLL_PRE_SRC, 157 CLK_VPLL_HALF, 158 CLK_VPLL_INT_MUX, 159 CLK_VPLL_POST_SRC, 160 CLK_CAN0_MIO, 161 CLK_CAN1_MIO, 162 END_OF_OUTPUT_CLKS, 163 }; 164 165 #define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS) 166 167 //External clock ids 168 enum { 169 EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS, 170 EXT_CLK_VIDEO, 171 EXT_CLK_PSS_ALT_REF, 172 EXT_CLK_AUX_REF, 173 EXT_CLK_GT_CRX_REF, 174 EXT_CLK_SWDT0, 175 EXT_CLK_SWDT1, 176 EXT_CLK_GEM0_EMIO, 177 EXT_CLK_GEM1_EMIO, 178 EXT_CLK_GEM2_EMIO, 179 EXT_CLK_GEM3_EMIO, 180 EXT_CLK_MIO50_OR_MIO51, 181 EXT_CLK_MIO0, 182 EXT_CLK_MIO1, 183 EXT_CLK_MIO2, 184 EXT_CLK_MIO3, 185 EXT_CLK_MIO4, 186 EXT_CLK_MIO5, 187 EXT_CLK_MIO6, 188 EXT_CLK_MIO7, 189 EXT_CLK_MIO8, 190 EXT_CLK_MIO9, 191 EXT_CLK_MIO10, 192 EXT_CLK_MIO11, 193 EXT_CLK_MIO12, 194 EXT_CLK_MIO13, 195 EXT_CLK_MIO14, 196 EXT_CLK_MIO15, 197 EXT_CLK_MIO16, 198 EXT_CLK_MIO17, 199 EXT_CLK_MIO18, 200 EXT_CLK_MIO19, 201 EXT_CLK_MIO20, 202 EXT_CLK_MIO21, 203 EXT_CLK_MIO22, 204 EXT_CLK_MIO23, 205 EXT_CLK_MIO24, 206 EXT_CLK_MIO25, 207 EXT_CLK_MIO26, 208 EXT_CLK_MIO27, 209 EXT_CLK_MIO28, 210 EXT_CLK_MIO29, 211 EXT_CLK_MIO30, 212 EXT_CLK_MIO31, 213 EXT_CLK_MIO32, 214 EXT_CLK_MIO33, 215 EXT_CLK_MIO34, 216 EXT_CLK_MIO35, 217 EXT_CLK_MIO36, 218 EXT_CLK_MIO37, 219 EXT_CLK_MIO38, 220 EXT_CLK_MIO39, 221 EXT_CLK_MIO40, 222 EXT_CLK_MIO41, 223 EXT_CLK_MIO42, 224 EXT_CLK_MIO43, 225 EXT_CLK_MIO44, 226 EXT_CLK_MIO45, 227 EXT_CLK_MIO46, 228 EXT_CLK_MIO47, 229 EXT_CLK_MIO48, 230 EXT_CLK_MIO49, 231 EXT_CLK_MIO50, 232 EXT_CLK_MIO51, 233 EXT_CLK_MIO52, 234 EXT_CLK_MIO53, 235 EXT_CLK_MIO54, 236 EXT_CLK_MIO55, 237 EXT_CLK_MIO56, 238 EXT_CLK_MIO57, 239 EXT_CLK_MIO58, 240 EXT_CLK_MIO59, 241 EXT_CLK_MIO60, 242 EXT_CLK_MIO61, 243 EXT_CLK_MIO62, 244 EXT_CLK_MIO63, 245 EXT_CLK_MIO64, 246 EXT_CLK_MIO65, 247 EXT_CLK_MIO66, 248 EXT_CLK_MIO67, 249 EXT_CLK_MIO68, 250 EXT_CLK_MIO69, 251 EXT_CLK_MIO70, 252 EXT_CLK_MIO71, 253 EXT_CLK_MIO72, 254 EXT_CLK_MIO73, 255 EXT_CLK_MIO74, 256 EXT_CLK_MIO75, 257 EXT_CLK_MIO76, 258 EXT_CLK_MIO77, 259 END_OF_CLKS, 260 }; 261 262 #define CLK_MAX (unsigned int)(END_OF_CLKS) 263 264 //CLock types 265 #define CLK_TYPE_OUTPUT 0U 266 #define CLK_TYPE_EXTERNAL 1U 267 268 //Topology types 269 #define TYPE_INVALID 0U 270 #define TYPE_MUX 1U 271 #define TYPE_PLL 2U 272 #define TYPE_FIXEDFACTOR 3U 273 #define TYPE_DIV1 4U 274 #define TYPE_DIV2 5U 275 #define TYPE_GATE 6U 276 277 278 enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name); 279 enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, 280 unsigned int index, 281 uint32_t *topology); 282 enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, 283 uint32_t *mul, 284 uint32_t *div); 285 enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, 286 unsigned int index, 287 uint32_t *parents); 288 enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, 289 uint32_t *attr); 290 enum pm_ret_status pm_api_clock_enable(unsigned int clock_id); 291 enum pm_ret_status pm_api_clock_disable(unsigned int clock_id); 292 enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id, 293 unsigned int *state); 294 enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id, 295 unsigned int divider); 296 enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id, 297 unsigned int *divider); 298 enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id, 299 uint64_t rate); 300 enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id, 301 uint64_t *rate); 302 enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id, 303 unsigned int parent_idx); 304 enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id, 305 unsigned int *parent_idx); 306 enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll, 307 unsigned int mode); 308 enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll, 309 unsigned int *mode); 310 enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll, 311 unsigned int data); 312 enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll, 313 unsigned int *data); 314 315 #endif /* _PM_API_CLOCK_H_ */ 316