1# 2# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 5# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 6# 7# SPDX-License-Identifier: BSD-3-Clause 8 9override ERRATA_A53_855873 := 1 10ERRATA_A53_1530924 := 1 11override PROGRAMMABLE_RESET_ADDRESS := 1 12PSCI_EXTENDED_STATE_ID := 1 13A53_DISABLE_NON_TEMPORAL_HINT := 0 14SEPARATE_CODE_AND_RODATA := 1 15ZYNQMP_WDT_RESTART := 0 16IPI_CRC_CHECK := 0 17override RESET_TO_BL31 := 1 18override WARMBOOT_ENABLE_DCACHE_EARLY := 1 19 20EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT) 21 22# pncd SPD requires secure SGI to be handled at EL1 23ifeq (${SPD}, $(filter ${SPD},pncd tspd)) 24ifeq (${ZYNQMP_WDT_RESTART},1) 25$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible") 26endif 27override GICV2_G0_FOR_EL3 := 0 28else 29override GICV2_G0_FOR_EL3 := 1 30endif 31 32# Do not enable SVE 33ENABLE_SVE_FOR_NS := 0 34 35WORKAROUND_CVE_2017_5715 := 0 36 37ARM_XLAT_TABLES_LIB_V1 := 1 38$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1)) 39$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1)) 40 41ifdef ZYNQMP_ATF_MEM_BASE 42 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE)) 43 44 ifndef ZYNQMP_ATF_MEM_SIZE 45 $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE") 46 endif 47 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE)) 48 49 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 50 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE)) 51 endif 52endif 53 54ifdef ZYNQMP_BL32_MEM_BASE 55 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE)) 56 57 ifndef ZYNQMP_BL32_MEM_SIZE 58 $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE") 59 endif 60 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE)) 61endif 62 63 64ifdef ZYNQMP_WDT_RESTART 65 $(eval $(call add_define,ZYNQMP_WDT_RESTART)) 66endif 67 68ifdef ZYNQMP_IPI_CRC_CHECK 69 $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.") 70endif 71 72ifdef IPI_CRC_CHECK 73 $(eval $(call add_define,IPI_CRC_CHECK)) 74endif 75 76ifdef ZYNQMP_SECURE_EFUSES 77 $(eval $(call add_define,ZYNQMP_SECURE_EFUSES)) 78endif 79 80ifdef XILINX_OF_BOARD_DTB_ADDR 81$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 82endif 83 84PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 85 -Iinclude/plat/arm/common/aarch64/ \ 86 -Iplat/xilinx/common/include/ \ 87 -Iplat/xilinx/common/ipi_mailbox_service/ \ 88 -Iplat/xilinx/zynqmp/include/ \ 89 -Iplat/xilinx/zynqmp/pm_service/ \ 90 91include lib/libfdt/libfdt.mk 92# Include GICv2 driver files 93include drivers/arm/gic/v2/gicv2.mk 94 95PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ 96 lib/xlat_tables/aarch64/xlat_tables.c \ 97 drivers/arm/dcc/dcc_console.c \ 98 drivers/delay_timer/delay_timer.c \ 99 drivers/delay_timer/generic_delay_timer.c \ 100 ${GICV2_SOURCES} \ 101 drivers/cadence/uart/aarch64/cdns_console.S \ 102 plat/arm/common/arm_cci.c \ 103 plat/arm/common/arm_common.c \ 104 plat/arm/common/arm_gicv2.c \ 105 plat/common/plat_gicv2.c \ 106 plat/xilinx/common/ipi.c \ 107 plat/xilinx/zynqmp/zynqmp_ipi.c \ 108 plat/common/aarch64/crash_console_helpers.S \ 109 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \ 110 plat/xilinx/zynqmp/aarch64/zynqmp_common.c 111 112ZYNQMP_CONSOLE ?= cadence 113ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc)) 114else 115 $(error "Please define ZYNQMP_CONSOLE") 116endif 117$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE})) 118 119# Build PM code as a Library 120include plat/xilinx/zynqmp/libpm.mk 121 122BL31_SOURCES += drivers/arm/cci/cci.c \ 123 lib/cpus/aarch64/aem_generic.S \ 124 lib/cpus/aarch64/cortex_a53.S \ 125 plat/common/plat_psci_common.c \ 126 common/fdt_fixup.c \ 127 ${LIBFDT_SRCS} \ 128 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 129 plat/xilinx/common/plat_startup.c \ 130 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ 131 plat/xilinx/zynqmp/plat_psci.c \ 132 plat/xilinx/zynqmp/plat_zynqmp.c \ 133 plat/xilinx/zynqmp/plat_topology.c \ 134 plat/xilinx/zynqmp/sip_svc_setup.c 135 136ifeq (${SDEI_SUPPORT},1) 137BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \ 138 plat/xilinx/zynqmp/zynqmp_sdei.c 139endif 140 141BL31_CPPFLAGS += -fno-jump-tables 142TF_CFLAGS_aarch64 += -mbranch-protection=none 143 144ifdef CUSTOM_PKG_PATH 145include $(CUSTOM_PKG_PATH)/custom_pkg.mk 146else 147BL31_SOURCES += plat/xilinx/zynqmp/custom_sip_svc.c 148endif 149 150ifneq (${RESET_TO_BL31},1) 151 $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.") 152endif 153