1# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 2# 3# Redistribution and use in source and binary forms, with or without 4# modification, are permitted provided that the following conditions are met: 5# 6# Redistributions of source code must retain the above copyright notice, this 7# list of conditions and the following disclaimer. 8# 9# Redistributions in binary form must reproduce the above copyright notice, 10# this list of conditions and the following disclaimer in the documentation 11# and/or other materials provided with the distribution. 12# 13# Neither the name of ARM nor the names of its contributors may be used 14# to endorse or promote products derived from this software without specific 15# prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27# POSSIBILITY OF SUCH DAMAGE. 28 29ENABLE_PLAT_COMPAT := 0 30PROGRAMMABLE_RESET_ADDRESS := 1 31PSCI_EXTENDED_STATE_ID := 1 32A53_DISABLE_NON_TEMPORAL_HINT := 0 33SEPARATE_CODE_AND_RODATA := 1 34 35ifdef ZYNQMP_ATF_MEM_BASE 36 $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE)) 37 38 ifndef ZYNQMP_ATF_MEM_SIZE 39 $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE") 40 endif 41 $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE)) 42 43 ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 44 $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE)) 45 endif 46endif 47 48ifdef ZYNQMP_BL32_MEM_BASE 49 $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE)) 50 51 ifndef ZYNQMP_BL32_MEM_SIZE 52 $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE") 53 endif 54 $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE)) 55endif 56 57ZYNQMP_CONSOLE ?= cadence 58$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE})) 59 60PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 61 -Iinclude/plat/arm/common/aarch64/ \ 62 -Iplat/xilinx/zynqmp/include/ \ 63 -Iplat/xilinx/zynqmp/pm_service/ 64 65PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ 66 lib/xlat_tables/aarch64/xlat_tables.c \ 67 drivers/arm/gic/common/gic_common.c \ 68 drivers/arm/gic/v2/gicv2_main.c \ 69 drivers/arm/gic/v2/gicv2_helpers.c \ 70 drivers/cadence/uart/cdns_console.S \ 71 drivers/console/console.S \ 72 plat/arm/common/aarch64/arm_helpers.S \ 73 plat/arm/common/arm_cci.c \ 74 plat/arm/common/arm_common.c \ 75 plat/arm/common/arm_gicv2.c \ 76 plat/common/plat_gicv2.c \ 77 plat/common/aarch64/plat_common.c \ 78 plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \ 79 plat/xilinx/zynqmp/aarch64/zynqmp_common.c 80 81BL31_SOURCES += drivers/arm/cci/cci.c \ 82 lib/cpus/aarch64/aem_generic.S \ 83 lib/cpus/aarch64/cortex_a53.S \ 84 plat/common/plat_psci_common.c \ 85 plat/common/aarch64/platform_mp_stack.S \ 86 plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ 87 plat/xilinx/zynqmp/plat_psci.c \ 88 plat/xilinx/zynqmp/plat_zynqmp.c \ 89 plat/xilinx/zynqmp/plat_startup.c \ 90 plat/xilinx/zynqmp/plat_topology.c \ 91 plat/xilinx/zynqmp/sip_svc_setup.c \ 92 plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ 93 plat/xilinx/zynqmp/pm_service/pm_api_sys.c \ 94 plat/xilinx/zynqmp/pm_service/pm_ipi.c \ 95 plat/xilinx/zynqmp/pm_service/pm_client.c 96 97ifneq (${RESET_TO_BL31},1) 98 $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.") 99endif 100