1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_cadence 1 14 #define ZYNQMP_CONSOLE_ID_cadence0 1 15 #define ZYNQMP_CONSOLE_ID_cadence1 2 16 #define ZYNQMP_CONSOLE_ID_dcc 3 17 #define ZYNQMP_CONSOLE_ID_dtb 4 18 19 #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 20 21 /* Runtime console */ 22 #define RT_CONSOLE_ID_cadence 1 23 #define RT_CONSOLE_ID_cadence0 1 24 #define RT_CONSOLE_ID_cadence1 2 25 #define RT_CONSOLE_ID_dcc 3 26 #define RT_CONSOLE_ID_dtb 4 27 28 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 29 30 /* Default counter frequency */ 31 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 32 33 /* Firmware Image Package */ 34 #define ZYNQMP_PRIMARY_CPU 0 35 36 /* Memory location options for Shared data and TSP in ZYNQMP */ 37 #define ZYNQMP_IN_TRUSTED_SRAM 0 38 #define ZYNQMP_IN_TRUSTED_DRAM 1 39 40 /******************************************************************************* 41 * ZYNQMP memory map related constants 42 ******************************************************************************/ 43 /* Aggregate of all devices in the first GB */ 44 #define DEVICE0_BASE U(0xFF000000) 45 #define DEVICE0_SIZE U(0x00E00000) 46 #define DEVICE1_BASE U(0xF9000000) 47 #define DEVICE1_SIZE U(0x00800000) 48 49 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 50 #define CRF_APB_BASE U(0xFD1A0000) 51 #define CRF_APB_SIZE U(0x00600000) 52 #define CRF_APB_CLK_BASE U(0xFD1A0020) 53 54 /* CRF registers and bitfields */ 55 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 56 57 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 58 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 59 60 /* CRL registers and bitfields */ 61 #define CRL_APB_BASE U(0xFF5E0000) 62 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 63 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 64 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 65 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 66 #define CRL_APB_CLK_BASE U(0xFF5E0020) 67 68 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 69 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 70 71 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 72 73 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 74 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 75 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 76 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 77 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 78 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 79 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 80 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 81 #define ZYNQMP_BOOTMODE_JTAG U(0) 82 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 83 CRL_APB_BOOT_DRIVE_PIN_1) 84 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 85 86 /* system counter registers and bitfields */ 87 #define IOU_SCNTRS_BASE U(0xFF260000) 88 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 89 90 /* APU registers and bitfields */ 91 #define APU_BASE U(0xFD5C0000) 92 #define APU_CONFIG_0 (APU_BASE + 0x20) 93 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 94 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 95 #define APU_PWRCTL (APU_BASE + 0x90) 96 97 #define APU_CONFIG_0_VINITHI_SHIFT 8 98 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 99 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 100 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 101 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 102 103 /* PMU registers and bitfields */ 104 #define PMU_GLOBAL_BASE U(0xFFD80000) 105 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 106 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 107 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 108 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 109 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 110 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 111 112 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 113 114 /******************************************************************************* 115 * CCI-400 related constants 116 ******************************************************************************/ 117 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 118 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 119 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 120 121 /******************************************************************************* 122 * GIC-400 & interrupt handling related constants 123 ******************************************************************************/ 124 #define BASE_GICD_BASE U(0xF9010000) 125 #define BASE_GICC_BASE U(0xF9020000) 126 #define BASE_GICH_BASE U(0xF9040000) 127 #define BASE_GICV_BASE U(0xF9060000) 128 129 #if ZYNQMP_WDT_RESTART 130 #define IRQ_SEC_IPI_APU 67 131 #define IRQ_TTC3_1 77 132 #define TTC3_BASE_ADDR U(0xFF140000) 133 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 134 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 135 #endif 136 137 #define ARM_IRQ_SEC_PHY_TIMER 29 138 139 #define ARM_IRQ_SEC_SGI_0 8 140 #define ARM_IRQ_SEC_SGI_1 9 141 #define ARM_IRQ_SEC_SGI_2 10 142 #define ARM_IRQ_SEC_SGI_3 11 143 #define ARM_IRQ_SEC_SGI_4 12 144 #define ARM_IRQ_SEC_SGI_5 13 145 #define ARM_IRQ_SEC_SGI_6 14 146 #define ARM_IRQ_SEC_SGI_7 15 147 148 /* number of interrupt handlers. increase as required */ 149 #define MAX_INTR_EL3 2 150 151 /******************************************************************************* 152 * UART related constants 153 ******************************************************************************/ 154 #define ZYNQMP_UART0_BASE U(0xFF000000) 155 #define ZYNQMP_UART1_BASE U(0xFF010000) 156 157 /* Boot console */ 158 #if CONSOLE_IS(cadence) || CONSOLE_IS(dtb) 159 # define UART_BASE ZYNQMP_UART0_BASE 160 # define UART_TYPE CONSOLE_CDNS 161 #elif CONSOLE_IS(cadence1) 162 # define UART_BASE ZYNQMP_UART1_BASE 163 # define UART_TYPE CONSOLE_CDNS 164 #elif CONSOLE_IS(dcc) 165 # define UART_BASE 0x0 166 # define UART_TYPE CONSOLE_DCC 167 #else 168 # error "invalid ZYNQMP_CONSOLE" 169 #endif 170 171 /* Runtime console */ 172 #if defined(CONSOLE_RUNTIME) 173 #if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dtb) 174 # define RT_UART_BASE ZYNQMP_UART0_BASE 175 # define RT_UART_TYPE CONSOLE_CDNS 176 #elif RT_CONSOLE_IS(cadence1) 177 # define RT_UART_BASE ZYNQMP_UART1_BASE 178 # define RT_UART_TYPE CONSOLE_CDNS 179 #elif RT_CONSOLE_IS(dcc) 180 # define RT_UART_BASE 0x0 181 # define RT_UART_TYPE CONSOLE_DCC 182 #else 183 # error "invalid CONSOLE_RUNTIME" 184 #endif 185 #endif 186 187 /* Must be non zero */ 188 #define UART_BAUDRATE 115200 189 190 /* Silicon version detection */ 191 #define ZYNQMP_SILICON_VER_MASK 0xF000 192 #define ZYNQMP_SILICON_VER_SHIFT 12 193 #define ZYNQMP_CSU_VERSION_SILICON 0 194 #define ZYNQMP_CSU_VERSION_QEMU 3 195 196 #define ZYNQMP_RTL_VER_MASK 0xFF0U 197 #define ZYNQMP_RTL_VER_SHIFT 4 198 199 #define ZYNQMP_PS_VER_MASK 0xFU 200 #define ZYNQMP_PS_VER_SHIFT 0 201 202 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 203 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U 204 205 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U 206 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ 207 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 208 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 209 210 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U 211 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ 212 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 213 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U 214 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ 215 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 216 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U 217 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ 218 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 219 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U 220 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ 221 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 222 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 223 224 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U 225 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ 226 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 227 #define ZYNQMP_CSU_IDCODE_REVISION 0U 228 229 #define ZYNQMP_CSU_VERSION_OFFSET 0x44U 230 231 /* Efuse */ 232 #define EFUSE_BASEADDR U(0xFFCC0000) 233 #define EFUSE_IPDISABLE_OFFSET 0x1018 234 #define EFUSE_IPDISABLE_VERSION 0x1FFU 235 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 236 237 /* Access control register defines */ 238 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 239 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 240 241 #define FPD_SLCR_BASEADDR U(0xFD610000) 242 #define IOU_SLCR_BASEADDR U(0xFF180000) 243 244 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 245 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 246 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 247 #define ZYNQMP_SLSPLIT_MASK U(0x08) 248 #define ZYNQMP_TCM_COMB_MASK U(0x40) 249 #define ZYNQMP_SLCLAMP_MASK U(0x10) 250 #define ZYNQMP_VINITHI_MASK U(0x04) 251 252 /* Tap delay bypass */ 253 #define IOU_TAPDLY_BYPASS U(0XFF180390) 254 #define TAP_DELAY_MASK U(0x7) 255 256 /* SD DLL reset */ 257 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 258 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 259 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 260 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 261 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 262 263 /* SD tap delay */ 264 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 265 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 266 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 267 #define ZYNQMP_SD_TAP_OFFSET U(16) 268 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 269 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 270 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 271 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 272 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 273 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 274 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 275 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 276 277 /* Clock control registers */ 278 /* Full power domain clocks */ 279 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 280 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 281 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 282 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 283 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 284 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 285 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 286 /* Peripheral clocks */ 287 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 288 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 289 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 290 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 291 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 292 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 293 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 294 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 295 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 296 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 297 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 298 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 299 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 300 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 301 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 302 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 303 304 /* Low power domain clocks */ 305 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 306 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 307 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 308 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 309 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 310 /* Peripheral clocks */ 311 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 312 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 313 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 314 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 315 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 316 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 317 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 318 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 319 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 320 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 321 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 322 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 323 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 324 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 325 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 326 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 327 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 328 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 329 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 330 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 331 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 332 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 333 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 334 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 335 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 336 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 337 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 338 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 339 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 340 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 341 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 342 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 343 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 344 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 345 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 346 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 347 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 348 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 349 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 350 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 351 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 352 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 353 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 354 355 /* Global general storage register base address */ 356 #define GGS_BASEADDR (0xFFD80030U) 357 #define GGS_NUM_REGS U(4) 358 359 /* Persistent global general storage register base address */ 360 #define PGGS_BASEADDR (0xFFD80050U) 361 #define PGGS_NUM_REGS U(4) 362 363 /* PMU GGS4 register 4 is used for warm restart boot health status */ 364 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 365 /* Warm restart boot health status mask */ 366 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 367 /* WDT restart scope shift and mask */ 368 #define RESTART_SCOPE_SHIFT (3) 369 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 370 371 /* AFI registers */ 372 #define AFIFM6_WRCTRL U(13) 373 #define FABRIC_WIDTH U(3) 374 375 /* CSUDMA Module Base Address*/ 376 #define CSUDMA_BASE U(0xFFC80000) 377 378 /* RSA-CORE Module Base Address*/ 379 #define RSA_CORE_BASE U(0xFFCE0000) 380 381 #endif /* ZYNQMP_DEF_H */ 382