1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_none 0 14 #define ZYNQMP_CONSOLE_ID_cadence 1 15 #define ZYNQMP_CONSOLE_ID_cadence0 1 16 #define ZYNQMP_CONSOLE_ID_cadence1 2 17 #define ZYNQMP_CONSOLE_ID_dcc 3 18 #define ZYNQMP_CONSOLE_ID_dtb 4 19 20 #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 21 22 /* Runtime console */ 23 #define RT_CONSOLE_ID_cadence 1 24 #define RT_CONSOLE_ID_cadence0 1 25 #define RT_CONSOLE_ID_cadence1 2 26 #define RT_CONSOLE_ID_dcc 3 27 #define RT_CONSOLE_ID_dtb 4 28 29 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 30 31 /* Default counter frequency */ 32 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 33 34 /* Firmware Image Package */ 35 #define ZYNQMP_PRIMARY_CPU 0 36 37 /* Memory location options for Shared data and TSP in ZYNQMP */ 38 #define ZYNQMP_IN_TRUSTED_SRAM 0 39 #define ZYNQMP_IN_TRUSTED_DRAM 1 40 41 /******************************************************************************* 42 * ZYNQMP memory map related constants 43 ******************************************************************************/ 44 /* Aggregate of all devices in the first GB */ 45 #define DEVICE0_BASE U(0xFF000000) 46 #define DEVICE0_SIZE U(0x00E00000) 47 #define DEVICE1_BASE U(0xF9000000) 48 #define DEVICE1_SIZE U(0x00800000) 49 50 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 51 #define CRF_APB_BASE U(0xFD1A0000) 52 #define CRF_APB_SIZE U(0x00600000) 53 #define CRF_APB_CLK_BASE U(0xFD1A0020) 54 55 /* CRF registers and bitfields */ 56 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 57 58 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 59 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 60 61 /* CRL registers and bitfields */ 62 #define CRL_APB_BASE U(0xFF5E0000) 63 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + U(0x200)) 64 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + U(0x218)) 65 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + U(0x23C)) 66 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 67 #define CRL_APB_CLK_BASE U(0xFF5E0020) 68 69 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 70 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 71 72 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 73 74 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 75 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 76 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 77 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 78 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 79 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 80 #define ZYNQMP_BOOTMODE_JTAG U(0) 81 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | CRL_APB_BOOT_DRIVE_PIN_1) 82 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 83 84 /* system counter registers and bitfields */ 85 #define IOU_SCNTRS_BASE U(0xFF260000) 86 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + U(0x20)) 87 88 /* APU registers and bitfields */ 89 #define APU_BASE U(0xFD5C0000) 90 #define APU_CONFIG_0 (APU_BASE + 0x20) 91 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 92 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 93 #define APU_PWRCTL (APU_BASE + 0x90) 94 95 #define APU_CONFIG_0_VINITHI_SHIFT 8 96 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 97 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 98 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 99 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 100 101 /* PMU registers and bitfields */ 102 #define PMU_GLOBAL_BASE U(0xFFD80000) 103 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 104 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + U(0x48)) 105 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + U(0x110)) 106 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + U(0x118)) 107 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + U(0x11c)) 108 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + U(0x120)) 109 110 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 111 112 /******************************************************************************* 113 * CCI-400 related constants 114 ******************************************************************************/ 115 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 116 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 117 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 118 119 /******************************************************************************* 120 * GIC-400 & interrupt handling related constants 121 ******************************************************************************/ 122 #define BASE_GICD_BASE U(0xF9010000) 123 #define BASE_GICC_BASE U(0xF9020000) 124 #define BASE_GICH_BASE U(0xF9040000) 125 #define BASE_GICV_BASE U(0xF9060000) 126 127 #if ZYNQMP_WDT_RESTART 128 #define IRQ_SEC_IPI_APU 67 129 #define IRQ_TTC3_1 77 130 #define TTC3_BASE_ADDR U(0xFF140000) 131 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 132 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 133 #endif 134 135 #define ARM_IRQ_SEC_PHY_TIMER 29 136 137 #define ARM_IRQ_SEC_SGI_0 8 138 #define ARM_IRQ_SEC_SGI_1 9 139 #define ARM_IRQ_SEC_SGI_2 10 140 #define ARM_IRQ_SEC_SGI_3 11 141 #define ARM_IRQ_SEC_SGI_4 12 142 #define ARM_IRQ_SEC_SGI_5 13 143 #define ARM_IRQ_SEC_SGI_6 14 144 #define ARM_IRQ_SEC_SGI_7 15 145 146 /* number of interrupt handlers. increase as required */ 147 #define MAX_INTR_EL3 2 148 149 /******************************************************************************* 150 * UART related constants 151 ******************************************************************************/ 152 #define ZYNQMP_UART0_BASE U(0xFF000000) 153 #define ZYNQMP_UART1_BASE U(0xFF010000) 154 155 /* Boot console */ 156 #if CONSOLE_IS(cadence) || CONSOLE_IS(dtb) 157 # define UART_BASE ZYNQMP_UART0_BASE 158 # define UART_TYPE CONSOLE_CDNS 159 #elif CONSOLE_IS(cadence1) 160 # define UART_BASE ZYNQMP_UART1_BASE 161 # define UART_TYPE CONSOLE_CDNS 162 #elif CONSOLE_IS(dcc) 163 # define UART_BASE 0x0 164 # define UART_TYPE CONSOLE_DCC 165 #elif CONSOLE_IS(none) 166 # define UART_TYPE CONSOLE_NONE 167 #else 168 # error "invalid ZYNQMP_CONSOLE" 169 #endif 170 171 /* Runtime console */ 172 #if defined(CONSOLE_RUNTIME) 173 #if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dtb) 174 # define RT_UART_BASE ZYNQMP_UART0_BASE 175 # define RT_UART_TYPE CONSOLE_CDNS 176 #elif RT_CONSOLE_IS(cadence1) 177 # define RT_UART_BASE ZYNQMP_UART1_BASE 178 # define RT_UART_TYPE CONSOLE_CDNS 179 #elif RT_CONSOLE_IS(dcc) 180 # define RT_UART_BASE 0x0 181 # define RT_UART_TYPE CONSOLE_DCC 182 #else 183 # error "invalid CONSOLE_RUNTIME" 184 #endif 185 #endif 186 187 /* Must be non zero */ 188 #define UART_BAUDRATE 115200 189 190 /* Silicon version detection */ 191 #define ZYNQMP_SILICON_VER_MASK U(0xF000) 192 #define ZYNQMP_SILICON_VER_SHIFT 12 193 #define ZYNQMP_CSU_VERSION_SILICON 0 194 #define ZYNQMP_CSU_VERSION_QEMU U(3) 195 196 #define ZYNQMP_RTL_VER_MASK 0xFF0U 197 #define ZYNQMP_RTL_VER_SHIFT 4 198 199 #define ZYNQMP_PS_VER_MASK 0xFU 200 #define ZYNQMP_PS_VER_SHIFT 0 201 202 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 203 #define ZYNQMP_CSU_IDCODE_OFFSET U(0x40) 204 205 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT U(0) 206 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (U(0xFFF) << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 207 #define ZYNQMP_CSU_IDCODE_XILINX_ID U(0x093) 208 209 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT U(12) 210 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << ZYNQMP_CSU_IDCODE_SVD_SHIFT) 211 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT U(15) 212 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 213 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT U(19) 214 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (U(0x3) << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 215 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT U(21) 216 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (U(0x7F) << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 217 #define ZYNQMP_CSU_IDCODE_FAMILY U(0x23) 218 219 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT U(28) 220 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (U(0xF) << ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 221 #define ZYNQMP_CSU_IDCODE_REVISION U(0) 222 223 #define ZYNQMP_CSU_VERSION_OFFSET U(0x44) 224 225 /* Efuse */ 226 #define EFUSE_BASEADDR U(0xFFCC0000) 227 #define EFUSE_IPDISABLE_OFFSET 0x1018 228 #define EFUSE_IPDISABLE_VERSION U(0x1FF) 229 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 230 231 /* Access control register defines */ 232 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 233 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 234 235 #define FPD_SLCR_BASEADDR U(0xFD610000) 236 #define IOU_SLCR_BASEADDR U(0xFF180000) 237 238 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 239 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 240 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 241 #define ZYNQMP_SLSPLIT_MASK U(0x08) 242 #define ZYNQMP_TCM_COMB_MASK U(0x40) 243 #define ZYNQMP_SLCLAMP_MASK U(0x10) 244 #define ZYNQMP_VINITHI_MASK U(0x04) 245 246 /* Tap delay bypass */ 247 #define IOU_TAPDLY_BYPASS U(0XFF180390) 248 #define TAP_DELAY_MASK U(0x7) 249 250 /* SD DLL reset */ 251 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 252 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 253 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 254 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 255 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 256 257 /* SD tap delay */ 258 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 259 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 260 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 261 #define ZYNQMP_SD_TAP_OFFSET U(16) 262 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 263 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 264 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 265 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 266 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 267 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 268 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 269 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 270 271 /* Clock control registers */ 272 /* Full power domain clocks */ 273 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 274 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 275 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 276 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 277 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 278 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 279 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 280 /* Peripheral clocks */ 281 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 282 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 283 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 284 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 285 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 286 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 287 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 288 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 289 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 290 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 291 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 292 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 293 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 294 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 295 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 296 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 297 298 /* Low power domain clocks */ 299 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 300 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 301 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 302 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 303 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 304 /* Peripheral clocks */ 305 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 306 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 307 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 308 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 309 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 310 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 311 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 312 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 313 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 314 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 315 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 316 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 317 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 318 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 319 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 320 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 321 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 322 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 323 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 324 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 325 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 326 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 327 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 328 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 329 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 330 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 331 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 332 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 333 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 334 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 335 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 336 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 337 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 338 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 339 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 340 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 341 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 342 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 343 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 344 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 345 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 346 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 347 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 348 349 /* Global general storage register base address */ 350 #define GGS_BASEADDR U(0xFFD80030) 351 #define GGS_NUM_REGS U(4) 352 353 /* Persistent global general storage register base address */ 354 #define PGGS_BASEADDR U(0xFFD80050) 355 #define PGGS_NUM_REGS U(4) 356 357 /* PMU GGS4 register 4 is used for warm restart boot health status */ 358 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 359 /* Warm restart boot health status mask */ 360 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 361 /* WDT restart scope shift and mask */ 362 #define RESTART_SCOPE_SHIFT (3) 363 #define RESTART_SCOPE_MASK (U(0x3) << RESTART_SCOPE_SHIFT) 364 365 /* AFI registers */ 366 #define AFIFM6_WRCTRL U(13) 367 #define FABRIC_WIDTH U(3) 368 369 /* CSUDMA Module Base Address*/ 370 #define CSUDMA_BASE U(0xFFC80000) 371 372 /* RSA-CORE Module Base Address*/ 373 #define RSA_CORE_BASE U(0xFFCE0000) 374 375 #endif /* ZYNQMP_DEF_H */ 376