1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_cadence 1 14 #define ZYNQMP_CONSOLE_ID_cadence0 1 15 #define ZYNQMP_CONSOLE_ID_cadence1 2 16 #define ZYNQMP_CONSOLE_ID_dcc 3 17 18 #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 19 20 /* Runtime console */ 21 #define RT_CONSOLE_ID_cadence 1 22 #define RT_CONSOLE_ID_cadence0 1 23 #define RT_CONSOLE_ID_cadence1 2 24 #define RT_CONSOLE_ID_dcc 3 25 #define RT_CONSOLE_ID_dtb 4 26 27 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 28 29 /* Default counter frequency */ 30 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 31 32 /* Firmware Image Package */ 33 #define ZYNQMP_PRIMARY_CPU 0 34 35 /* Memory location options for Shared data and TSP in ZYNQMP */ 36 #define ZYNQMP_IN_TRUSTED_SRAM 0 37 #define ZYNQMP_IN_TRUSTED_DRAM 1 38 39 /******************************************************************************* 40 * ZYNQMP memory map related constants 41 ******************************************************************************/ 42 /* Aggregate of all devices in the first GB */ 43 #define DEVICE0_BASE U(0xFF000000) 44 #define DEVICE0_SIZE U(0x00E00000) 45 #define DEVICE1_BASE U(0xF9000000) 46 #define DEVICE1_SIZE U(0x00800000) 47 48 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 49 #define CRF_APB_BASE U(0xFD1A0000) 50 #define CRF_APB_SIZE U(0x00600000) 51 #define CRF_APB_CLK_BASE U(0xFD1A0020) 52 53 /* CRF registers and bitfields */ 54 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 55 56 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 57 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 58 59 /* CRL registers and bitfields */ 60 #define CRL_APB_BASE U(0xFF5E0000) 61 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 62 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 63 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 64 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 65 #define CRL_APB_CLK_BASE U(0xFF5E0020) 66 67 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 68 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 69 70 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 71 72 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 73 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 74 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 75 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 76 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 77 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 78 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 79 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 80 #define ZYNQMP_BOOTMODE_JTAG U(0) 81 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 82 CRL_APB_BOOT_DRIVE_PIN_1) 83 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 84 85 /* system counter registers and bitfields */ 86 #define IOU_SCNTRS_BASE U(0xFF260000) 87 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 88 89 /* APU registers and bitfields */ 90 #define APU_BASE U(0xFD5C0000) 91 #define APU_CONFIG_0 (APU_BASE + 0x20) 92 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 93 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 94 #define APU_PWRCTL (APU_BASE + 0x90) 95 96 #define APU_CONFIG_0_VINITHI_SHIFT 8 97 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 98 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 99 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 100 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 101 102 /* PMU registers and bitfields */ 103 #define PMU_GLOBAL_BASE U(0xFFD80000) 104 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 105 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 106 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 107 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 108 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 109 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 110 111 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 112 113 /******************************************************************************* 114 * CCI-400 related constants 115 ******************************************************************************/ 116 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 117 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 118 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 119 120 /******************************************************************************* 121 * GIC-400 & interrupt handling related constants 122 ******************************************************************************/ 123 #define BASE_GICD_BASE U(0xF9010000) 124 #define BASE_GICC_BASE U(0xF9020000) 125 #define BASE_GICH_BASE U(0xF9040000) 126 #define BASE_GICV_BASE U(0xF9060000) 127 128 #if ZYNQMP_WDT_RESTART 129 #define IRQ_SEC_IPI_APU 67 130 #define IRQ_TTC3_1 77 131 #define TTC3_BASE_ADDR U(0xFF140000) 132 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 133 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 134 #endif 135 136 #define ARM_IRQ_SEC_PHY_TIMER 29 137 138 #define ARM_IRQ_SEC_SGI_0 8 139 #define ARM_IRQ_SEC_SGI_1 9 140 #define ARM_IRQ_SEC_SGI_2 10 141 #define ARM_IRQ_SEC_SGI_3 11 142 #define ARM_IRQ_SEC_SGI_4 12 143 #define ARM_IRQ_SEC_SGI_5 13 144 #define ARM_IRQ_SEC_SGI_6 14 145 #define ARM_IRQ_SEC_SGI_7 15 146 147 /* number of interrupt handlers. increase as required */ 148 #define MAX_INTR_EL3 2 149 150 /******************************************************************************* 151 * UART related constants 152 ******************************************************************************/ 153 #define ZYNQMP_UART0_BASE U(0xFF000000) 154 #define ZYNQMP_UART1_BASE U(0xFF010000) 155 156 #if CONSOLE_IS(cadence) || CONSOLE_IS(dcc) 157 # define UART_BASE ZYNQMP_UART0_BASE 158 #elif CONSOLE_IS(cadence1) 159 # define UART_BASE ZYNQMP_UART1_BASE 160 #else 161 # error "invalid ZYNQMP_CONSOLE" 162 #endif 163 164 /* Runtime console */ 165 #if defined(CONSOLE_RUNTIME) 166 #if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dcc) || RT_CONSOLE_IS(dtb) 167 # define RT_UART_BASE ZYNQMP_UART0_BASE 168 #elif RT_CONSOLE_IS(cadence1) 169 # define RT_UART_BASE ZYNQMP_UART1_BASE 170 #else 171 # error "invalid CONSOLE_RUNTIME" 172 #endif 173 #endif 174 175 /* Must be non zero */ 176 #define UART_BAUDRATE 115200 177 178 /* Silicon version detection */ 179 #define ZYNQMP_SILICON_VER_MASK 0xF000 180 #define ZYNQMP_SILICON_VER_SHIFT 12 181 #define ZYNQMP_CSU_VERSION_SILICON 0 182 #define ZYNQMP_CSU_VERSION_QEMU 3 183 184 #define ZYNQMP_RTL_VER_MASK 0xFF0U 185 #define ZYNQMP_RTL_VER_SHIFT 4 186 187 #define ZYNQMP_PS_VER_MASK 0xFU 188 #define ZYNQMP_PS_VER_SHIFT 0 189 190 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 191 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U 192 193 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U 194 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ 195 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 196 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 197 198 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U 199 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ 200 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 201 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U 202 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ 203 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 204 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U 205 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ 206 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 207 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U 208 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ 209 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 210 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 211 212 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U 213 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ 214 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 215 #define ZYNQMP_CSU_IDCODE_REVISION 0U 216 217 #define ZYNQMP_CSU_VERSION_OFFSET 0x44U 218 219 /* Efuse */ 220 #define EFUSE_BASEADDR U(0xFFCC0000) 221 #define EFUSE_IPDISABLE_OFFSET 0x1018 222 #define EFUSE_IPDISABLE_VERSION 0x1FFU 223 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 224 225 /* Access control register defines */ 226 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 227 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 228 229 #define FPD_SLCR_BASEADDR U(0xFD610000) 230 #define IOU_SLCR_BASEADDR U(0xFF180000) 231 232 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 233 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 234 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 235 #define ZYNQMP_SLSPLIT_MASK U(0x08) 236 #define ZYNQMP_TCM_COMB_MASK U(0x40) 237 #define ZYNQMP_SLCLAMP_MASK U(0x10) 238 #define ZYNQMP_VINITHI_MASK U(0x04) 239 240 /* Tap delay bypass */ 241 #define IOU_TAPDLY_BYPASS U(0XFF180390) 242 #define TAP_DELAY_MASK U(0x7) 243 244 /* SD DLL reset */ 245 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 246 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 247 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 248 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 249 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 250 251 /* SD tap delay */ 252 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 253 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 254 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 255 #define ZYNQMP_SD_TAP_OFFSET U(16) 256 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 257 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 258 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 259 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 260 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 261 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 262 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 263 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 264 265 /* Clock control registers */ 266 /* Full power domain clocks */ 267 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 268 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 269 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 270 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 271 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 272 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 273 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 274 /* Peripheral clocks */ 275 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 276 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 277 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 278 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 279 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 280 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 281 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 282 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 283 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 284 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 285 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 286 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 287 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 288 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 289 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 290 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 291 292 /* Low power domain clocks */ 293 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 294 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 295 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 296 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 297 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 298 /* Peripheral clocks */ 299 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 300 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 301 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 302 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 303 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 304 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 305 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 306 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 307 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 308 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 309 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 310 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 311 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 312 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 313 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 314 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 315 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 316 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 317 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 318 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 319 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 320 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 321 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 322 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 323 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 324 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 325 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 326 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 327 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 328 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 329 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 330 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 331 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 332 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 333 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 334 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 335 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 336 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 337 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 338 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 339 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 340 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 341 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 342 343 /* Global general storage register base address */ 344 #define GGS_BASEADDR (0xFFD80030U) 345 #define GGS_NUM_REGS U(4) 346 347 /* Persistent global general storage register base address */ 348 #define PGGS_BASEADDR (0xFFD80050U) 349 #define PGGS_NUM_REGS U(4) 350 351 /* PMU GGS4 register 4 is used for warm restart boot health status */ 352 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 353 /* Warm restart boot health status mask */ 354 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 355 /* WDT restart scope shift and mask */ 356 #define RESTART_SCOPE_SHIFT (3) 357 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 358 359 /* AFI registers */ 360 #define AFIFM6_WRCTRL U(13) 361 #define FABRIC_WIDTH U(3) 362 363 /* CSUDMA Module Base Address*/ 364 #define CSUDMA_BASE U(0xFFC80000) 365 366 /* RSA-CORE Module Base Address*/ 367 #define RSA_CORE_BASE U(0xFFCE0000) 368 369 #endif /* ZYNQMP_DEF_H */ 370